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| author | Eric Anholt <eric@anholt.net> | 2013-09-17 16:16:20 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2013-09-30 14:35:42 -0700 |
| commit | 9c116d5eacf286cd8548d64ba8ce6528edb889c9 (patch) | |
| tree | 047128f9e0cc97ab2b1330bb8303d594c6bfe0b3 /src | |
| parent | 114ae4747549b5677cca0dbd2b8c8531d8789c49 (diff) | |
| download | external_mesa3d-9c116d5eacf286cd8548d64ba8ce6528edb889c9.zip external_mesa3d-9c116d5eacf286cd8548d64ba8ce6528edb889c9.tar.gz external_mesa3d-9c116d5eacf286cd8548d64ba8ce6528edb889c9.tar.bz2 | |
i965: Always look up from the object's mt when setting up texturing state.
We know that the object's mt is equal to the firstimage's mt because it's
gone through intel_finalize_mipmap_tree(). Saves a lookup of firstimage
on pre-gen7.
v2: Merge in the warning fix that appeared later in the series (noted by
Chad)
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 3 |
2 files changed, 2 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 471fd03..066df9d 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -257,8 +257,6 @@ brw_update_texture_surface(struct gl_context *ctx, struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; struct intel_texture_object *intelObj = intel_texture_object(tObj); struct intel_mipmap_tree *mt = intelObj->mt; - struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel]; - struct intel_texture_image *intel_image = intel_texture_image(firstImage); struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit); uint32_t *surf; @@ -281,7 +279,7 @@ brw_update_texture_surface(struct gl_context *ctx, surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */ - surf[2] = ((intelObj->_MaxLevel - intel_image->mt->first_level) << BRW_SURFACE_LOD_SHIFT | + surf[2] = ((intelObj->_MaxLevel - mt->first_level) << BRW_SURFACE_LOD_SHIFT | (mt->logical_width0 - 1) << BRW_SURFACE_WIDTH_SHIFT | (mt->logical_height0 - 1) << BRW_SURFACE_HEIGHT_SHIFT); diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 7571cbf..f0d87eb 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -306,7 +306,6 @@ gen7_update_texture_surface(struct gl_context *ctx, struct intel_texture_object *intelObj = intel_texture_object(tObj); struct intel_mipmap_tree *mt = intelObj->mt; struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel]; - struct intel_texture_image *intel_image = intel_texture_image(firstImage); struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit); if (tObj->Target == GL_TEXTURE_BUFFER) { @@ -350,7 +349,7 @@ gen7_update_texture_surface(struct gl_context *ctx, surf[5] = (SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) | /* mip count */ - (intelObj->_MaxLevel - intel_image->mt->first_level)); + (intelObj->_MaxLevel - mt->first_level)); if (brw->is_haswell) { /* Handling GL_ALPHA as a surface format override breaks 1.30+ style |