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| author | Marek Olšák <marek.olsak@amd.com> | 2016-06-06 01:29:14 +0200 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2016-06-08 00:22:45 +0200 |
| commit | d4d733e39de2fc75aaa17d95998abdf19219cb38 (patch) | |
| tree | 3eb8b74370b9e5e9a8c642bf41f1f0c4eb9fea58 /src | |
| parent | b42bc90b6add0d0f81d915d49712761d32329afa (diff) | |
| download | external_mesa3d-d4d733e39de2fc75aaa17d95998abdf19219cb38.zip external_mesa3d-d4d733e39de2fc75aaa17d95998abdf19219cb38.tar.gz external_mesa3d-d4d733e39de2fc75aaa17d95998abdf19219cb38.tar.bz2 | |
gallium/radeon: don't allocate DCC for non-renderable texture formats
R9G9B9E5 is the only uncompressed one hopefully.
This fixes incorrect rendering not discovered (due to a lack of tests)
until DCC mipmapping was enabled.
Cc: 11.1 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeon/r600_texture.c | 5 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/radeon_winsys.h | 1 | ||||
| -rw-r--r-- | src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 1 |
3 files changed, 7 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index 920cc21..0f72a6d 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -281,6 +281,11 @@ static int r600_init_surface(struct r600_common_screen *rscreen, if (rscreen->chip_class >= SI) { surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; } + + if (rscreen->chip_class >= VI && + ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT) + surface->flags |= RADEON_SURF_DISABLE_DCC; + return 0; } diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h index 806ea63..a0c7abf 100644 --- a/src/gallium/drivers/radeon/radeon_winsys.h +++ b/src/gallium/drivers/radeon/radeon_winsys.h @@ -342,6 +342,7 @@ enum radeon_feature_id { #define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19) #define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20) #define RADEON_SURF_FMASK (1 << 21) +#define RADEON_SURF_DISABLE_DCC (1 << 22) #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK) #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c index d68c688..f609bf4 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c @@ -343,6 +343,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws, AddrSurfInfoIn.flags.degrade4Space = 1; AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && !(surf->flags & RADEON_SURF_SCANOUT) && + !(surf->flags & RADEON_SURF_DISABLE_DCC) && !compressed && AddrDccIn.numSamples <= 1; AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0; |