diff options
| -rw-r--r-- | src/intel/vulkan/gen7_pipeline.c | 3 | ||||
| -rw-r--r-- | src/intel/vulkan/gen8_pipeline.c | 3 | ||||
| -rw-r--r-- | src/intel/vulkan/genX_pipeline_util.h | 21 |
3 files changed, 25 insertions, 2 deletions
diff --git a/src/intel/vulkan/gen7_pipeline.c b/src/intel/vulkan/gen7_pipeline.c index df8fa28..1da28c0 100644 --- a/src/intel/vulkan/gen7_pipeline.c +++ b/src/intel/vulkan/gen7_pipeline.c @@ -67,7 +67,8 @@ genX(graphics_pipeline_create)( emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra); assert(pCreateInfo->pRasterizationState); - emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra); + emit_rs_state(pipeline, pCreateInfo->pRasterizationState, + pass, subpass, extra); emit_ds_state(pipeline, pCreateInfo->pDepthStencilState, pass, subpass); diff --git a/src/intel/vulkan/gen8_pipeline.c b/src/intel/vulkan/gen8_pipeline.c index e09d8cf..d16ce7b 100644 --- a/src/intel/vulkan/gen8_pipeline.c +++ b/src/intel/vulkan/gen8_pipeline.c @@ -119,7 +119,8 @@ genX(graphics_pipeline_create)( assert(pCreateInfo->pInputAssemblyState); emit_ia_state(pipeline, pCreateInfo->pInputAssemblyState, extra); assert(pCreateInfo->pRasterizationState); - emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra); + emit_rs_state(pipeline, pCreateInfo->pRasterizationState, + pass, subpass, extra); emit_ms_state(pipeline, pCreateInfo->pMultisampleState); emit_ds_state(pipeline, pCreateInfo->pDepthStencilState, pass, subpass); emit_cb_state(pipeline, pCreateInfo->pColorBlendState, diff --git a/src/intel/vulkan/genX_pipeline_util.h b/src/intel/vulkan/genX_pipeline_util.h index 5994120..c17d930 100644 --- a/src/intel/vulkan/genX_pipeline_util.h +++ b/src/intel/vulkan/genX_pipeline_util.h @@ -365,6 +365,8 @@ static const uint32_t vk_to_gen_front_face[] = { static void emit_rs_state(struct anv_pipeline *pipeline, const VkPipelineRasterizationStateCreateInfo *info, + const struct anv_render_pass *pass, + const struct anv_subpass *subpass, const struct anv_graphics_pipeline_create_info *extra) { struct GENX(3DSTATE_SF) sf = { @@ -414,6 +416,25 @@ emit_rs_state(struct anv_pipeline *pipeline, raster.GlobalDepthOffsetEnableWireframe = info->depthBiasEnable; raster.GlobalDepthOffsetEnablePoint = info->depthBiasEnable; +#if GEN_GEN == 7 + /* Gen7 requires that we provide the depth format in 3DSTATE_SF so that it + * can get the depth offsets correct. + */ + if (subpass->depth_stencil_attachment < pass->attachment_count) { + VkFormat vk_format = + pass->attachments[subpass->depth_stencil_attachment].format; + assert(vk_format_is_depth_or_stencil(vk_format)); + if (vk_format_aspects(vk_format) & VK_IMAGE_ASPECT_DEPTH_BIT) { + enum isl_format isl_format = + anv_get_isl_format(&pipeline->device->info, vk_format, + VK_IMAGE_ASPECT_DEPTH_BIT, + VK_IMAGE_TILING_OPTIMAL); + sf.DepthBufferSurfaceFormat = + isl_format_get_depth_format(isl_format, false); + } + } +#endif + #if GEN_GEN >= 8 GENX(3DSTATE_SF_pack)(NULL, pipeline->gen8.sf, &sf); GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gen8.raster, &raster); |