diff options
-rw-r--r-- | include/pci_ids/i965_pci_ids.h | 1 | ||||
-rw-r--r-- | src/mesa/drivers/dri/intel/intel_chipset.h | 4 | ||||
-rw-r--r-- | src/mesa/drivers/dri/intel/intel_context.c | 1 |
3 files changed, 5 insertions, 1 deletions
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index a291509..e38f8d2 100644 --- a/include/pci_ids/i965_pci_ids.h +++ b/include/pci_ids/i965_pci_ids.h @@ -25,6 +25,7 @@ CHIPSET(0x0162, IVYBRIDGE_GT2, ivb_gt2) CHIPSET(0x0156, IVYBRIDGE_M_GT1, ivb_gt1) CHIPSET(0x0166, IVYBRIDGE_M_GT2, ivb_gt2) CHIPSET(0x015a, IVYBRIDGE_S_GT1, ivb_gt1) +CHIPSET(0x016a, IVYBRIDGE_S_GT2, ivb_gt2) CHIPSET(0x0402, HASWELL_GT1, hsw_gt1) CHIPSET(0x0412, HASWELL_GT2, hsw_gt2) CHIPSET(0x0406, HASWELL_M_GT1, hsw_gt1) diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index 424c70c..c1d904e 100644 --- a/src/mesa/drivers/dri/intel/intel_chipset.h +++ b/src/mesa/drivers/dri/intel/intel_chipset.h @@ -85,6 +85,7 @@ #define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* Mobile */ #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 #define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a /* Server */ +#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ #define PCI_CHIP_HASWELL_GT2 0x0412 @@ -153,7 +154,8 @@ devid == PCI_CHIP_IVYBRIDGE_S_GT1) #define IS_IVB_GT2(devid) (devid == PCI_CHIP_IVYBRIDGE_GT2 || \ - devid == PCI_CHIP_IVYBRIDGE_M_GT2) + devid == PCI_CHIP_IVYBRIDGE_M_GT2 || \ + devid == PCI_CHIP_IVYBRIDGE_S_GT2) #define IS_IVYBRIDGE(devid) (IS_IVB_GT1(devid) || IS_IVB_GT2(devid)) diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index ff2b7fe..0a813a4 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -183,6 +183,7 @@ intelGetString(struct gl_context * ctx, GLenum name) chipset = "Intel(R) Ivybridge Mobile"; break; case PCI_CHIP_IVYBRIDGE_S_GT1: + case PCI_CHIP_IVYBRIDGE_S_GT2: chipset = "Intel(R) Ivybridge Server"; break; case PCI_CHIP_HASWELL_GT1: |