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-rw-r--r--src/intel/vulkan/gen7_pipeline.c37
-rw-r--r--src/intel/vulkan/gen8_pipeline.c49
-rw-r--r--src/intel/vulkan/genX_pipeline_util.h59
3 files changed, 60 insertions, 85 deletions
diff --git a/src/intel/vulkan/gen7_pipeline.c b/src/intel/vulkan/gen7_pipeline.c
index 4097abd..ad45ecb 100644
--- a/src/intel/vulkan/gen7_pipeline.c
+++ b/src/intel/vulkan/gen7_pipeline.c
@@ -76,41 +76,6 @@ gen7_emit_rs_state(struct anv_pipeline *pipeline,
}
static void
-gen7_emit_ds_state(struct anv_pipeline *pipeline,
- const VkPipelineDepthStencilStateCreateInfo *info)
-{
- if (info == NULL) {
- /* We're going to OR this together with the dynamic state. We need
- * to make sure it's initialized to something useful.
- */
- memset(pipeline->gen7.depth_stencil_state, 0,
- sizeof(pipeline->gen7.depth_stencil_state));
- return;
- }
-
- struct GENX(DEPTH_STENCIL_STATE) state = {
- .DepthTestEnable = info->depthTestEnable,
- .DepthBufferWriteEnable = info->depthWriteEnable,
- .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
- .DoubleSidedStencilEnable = true,
-
- .StencilTestEnable = info->stencilTestEnable,
- .StencilBufferWriteEnable = info->stencilTestEnable,
- .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
- .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
- .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
- .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
-
- .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
- .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
- .BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.depthFailOp],
- .BackfaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
- };
-
- GENX(DEPTH_STENCIL_STATE_pack)(NULL, &pipeline->gen7.depth_stencil_state, &state);
-}
-
-static void
gen7_emit_cb_state(struct anv_pipeline *pipeline,
const VkPipelineColorBlendStateCreateInfo *info,
const VkPipelineMultisampleStateCreateInfo *ms_info)
@@ -213,7 +178,7 @@ genX(graphics_pipeline_create)(
assert(pCreateInfo->pRasterizationState);
gen7_emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
- gen7_emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
+ emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
pCreateInfo->pMultisampleState);
diff --git a/src/intel/vulkan/gen8_pipeline.c b/src/intel/vulkan/gen8_pipeline.c
index d966694..cbeb791 100644
--- a/src/intel/vulkan/gen8_pipeline.c
+++ b/src/intel/vulkan/gen8_pipeline.c
@@ -216,55 +216,6 @@ emit_cb_state(struct anv_pipeline *pipeline,
}
static void
-emit_ds_state(struct anv_pipeline *pipeline,
- const VkPipelineDepthStencilStateCreateInfo *info)
-{
- uint32_t *dw = GEN_GEN == 8 ?
- pipeline->gen8.wm_depth_stencil : pipeline->gen9.wm_depth_stencil;
-
- if (info == NULL) {
- /* We're going to OR this together with the dynamic state. We need
- * to make sure it's initialized to something useful.
- */
- memset(pipeline->gen8.wm_depth_stencil, 0,
- sizeof(pipeline->gen8.wm_depth_stencil));
- memset(pipeline->gen9.wm_depth_stencil, 0,
- sizeof(pipeline->gen9.wm_depth_stencil));
- return;
- }
-
- /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
-
- struct GENX(3DSTATE_WM_DEPTH_STENCIL) wm_depth_stencil = {
- .DepthTestEnable = info->depthTestEnable,
- .DepthBufferWriteEnable = info->depthWriteEnable,
- .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
- .DoubleSidedStencilEnable = true,
-
- .StencilTestEnable = info->stencilTestEnable,
- .StencilBufferWriteEnable = info->stencilTestEnable,
- .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
- .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
- .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
- .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
- .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
- .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
- .BackfaceStencilPassDepthFailOp =vk_to_gen_stencil_op[info->back.depthFailOp],
- .BackfaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
- };
-
- /* From the Broadwell PRM:
- *
- * "If Depth_Test_Enable = 1 AND Depth_Test_func = EQUAL, the
- * Depth_Write_Enable must be set to 0."
- */
- if (info->depthTestEnable && info->depthCompareOp == VK_COMPARE_OP_EQUAL)
- wm_depth_stencil.DepthBufferWriteEnable = false;
-
- GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dw, &wm_depth_stencil);
-}
-
-static void
emit_ms_state(struct anv_pipeline *pipeline,
const VkPipelineMultisampleStateCreateInfo *info)
{
diff --git a/src/intel/vulkan/genX_pipeline_util.h b/src/intel/vulkan/genX_pipeline_util.h
index 2ed55e0..fe24048 100644
--- a/src/intel/vulkan/genX_pipeline_util.h
+++ b/src/intel/vulkan/genX_pipeline_util.h
@@ -425,3 +425,62 @@ static const uint32_t vk_to_gen_stencil_op[] = {
[VK_STENCIL_OP_INCREMENT_AND_WRAP] = STENCILOP_INCR,
[VK_STENCIL_OP_DECREMENT_AND_WRAP] = STENCILOP_DECR,
};
+
+static void
+emit_ds_state(struct anv_pipeline *pipeline,
+ const VkPipelineDepthStencilStateCreateInfo *info)
+{
+#if GEN_GEN == 7
+# define depth_stencil_dw pipeline->gen7.depth_stencil_state
+#elif GEN_GEN == 8
+# define depth_stencil_dw pipeline->gen8.wm_depth_stencil
+#else
+# define depth_stencil_dw pipeline->gen9.wm_depth_stencil
+#endif
+
+ if (info == NULL) {
+ /* We're going to OR this together with the dynamic state. We need
+ * to make sure it's initialized to something useful.
+ */
+ memset(depth_stencil_dw, 0, sizeof(depth_stencil_dw));
+ return;
+ }
+
+ /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
+
+#if GEN_GEN <= 7
+ struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
+#else
+ struct GENX(3DSTATE_WM_DEPTH_STENCIL) depth_stencil = {
+#endif
+ .DepthTestEnable = info->depthTestEnable,
+ .DepthBufferWriteEnable = info->depthWriteEnable,
+ .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
+ .DoubleSidedStencilEnable = true,
+
+ .StencilTestEnable = info->stencilTestEnable,
+ .StencilBufferWriteEnable = info->stencilTestEnable,
+ .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
+ .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
+ .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
+ .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
+ .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
+ .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
+ .BackfaceStencilPassDepthFailOp =vk_to_gen_stencil_op[info->back.depthFailOp],
+ .BackfaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
+ };
+
+ /* From the Broadwell PRM:
+ *
+ * "If Depth_Test_Enable = 1 AND Depth_Test_func = EQUAL, the
+ * Depth_Write_Enable must be set to 0."
+ */
+ if (info->depthTestEnable && info->depthCompareOp == VK_COMPARE_OP_EQUAL)
+ depth_stencil.DepthBufferWriteEnable = false;
+
+#if GEN_GEN <= 7
+ GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
+#else
+ GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, depth_stencil_dw, &depth_stencil);
+#endif
+}
generated by cgit v1.1 at 2024-06-20 16:19:15 +0000