diff options
| -rw-r--r-- | src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/AMDGPUInstrInfo.h | 4 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/R600InstrInfo.cpp | 40 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/R600InstrInfo.h | 4 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/SIInstrInfo.cpp | 28 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/SIInstrInfo.h | 9 |
6 files changed, 1 insertions, 87 deletions
diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp b/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp index 3c94c3d..d2bb4e1 100644 --- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp +++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp @@ -29,10 +29,9 @@ MachineInstr * AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction MachineInstrBuilder newInstr; MachineRegisterInfo &MRI = MF.getRegInfo(); const AMDGPURegisterInfo & RI = getRegisterInfo(); - unsigned ISAOpcode = getISAOpcode(MI.getOpcode()); // Create the new instruction - newInstr = BuildMI(MF, DL, TM.getInstrInfo()->get(ISAOpcode)); + newInstr = BuildMI(MF, DL, TM.getInstrInfo()->get(MI.getOpcode())); for (unsigned i = 0; i < MI.getNumOperands(); i++) { MachineOperand &MO = MI.getOperand(i); diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h index b0d4e8a..e6b79c8 100644 --- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h +++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h @@ -36,10 +36,6 @@ public: virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0; - /// getISAOpcode - This function takes an AMDIL opcode as an argument and - /// returns an equivalent ISA opcode. - virtual unsigned getISAOpcode(unsigned AMDILopcode) const = 0; - /// convertToISA - Convert the AMDIL MachineInstr to a supported ISA /// MachineInstr virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF, diff --git a/src/gallium/drivers/radeon/R600InstrInfo.cpp b/src/gallium/drivers/radeon/R600InstrInfo.cpp index 363c814..3d65e73 100644 --- a/src/gallium/drivers/radeon/R600InstrInfo.cpp +++ b/src/gallium/drivers/radeon/R600InstrInfo.cpp @@ -61,46 +61,6 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB, } } -unsigned R600InstrInfo::getISAOpcode(unsigned opcode) const -{ - switch (opcode) { - default: return opcode; - case AMDIL::IEQ: - return AMDIL::SETE_INT; - case AMDIL::INE: - return AMDIL::SETNE_INT; - case AMDIL::IGE: - return AMDIL::SETGE_INT; - case AMDIL::MOVE_f32: - case AMDIL::MOVE_i32: - return AMDIL::MOV; - case AMDIL::UGE: - return AMDIL::SETGE_UINT; - case AMDIL::UGT: - return AMDIL::SETGT_UINT; - } -} - -unsigned R600InstrInfo::getASHRop() const -{ - unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration(); - if (gen < AMDILDeviceInfo::HD5XXX) { - return AMDIL::ASHR_r600; - } else { - return AMDIL::ASHR_eg; - } -} - -unsigned R600InstrInfo::getLSHRop() const -{ - unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration(); - if (gen < AMDILDeviceInfo::HD5XXX) { - return AMDIL::LSHR_r600; - } else { - return AMDIL::LSHR_eg; - } -} - MachineInstr * R600InstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg, int64_t Imm) const { diff --git a/src/gallium/drivers/radeon/R600InstrInfo.h b/src/gallium/drivers/radeon/R600InstrInfo.h index 2db10ad..a7a65d5 100644 --- a/src/gallium/drivers/radeon/R600InstrInfo.h +++ b/src/gallium/drivers/radeon/R600InstrInfo.h @@ -41,12 +41,8 @@ namespace llvm { unsigned DestReg, unsigned SrcReg, bool KillSrc) const; - virtual unsigned getISAOpcode(unsigned opcode) const; bool isTrig(const MachineInstr &MI) const; - unsigned getLSHRop() const; - unsigned getASHRop() const; - virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg, int64_t Imm) const; diff --git a/src/gallium/drivers/radeon/SIInstrInfo.cpp b/src/gallium/drivers/radeon/SIInstrInfo.cpp index 058c772..1d464fe 100644 --- a/src/gallium/drivers/radeon/SIInstrInfo.cpp +++ b/src/gallium/drivers/radeon/SIInstrInfo.cpp @@ -77,34 +77,6 @@ unsigned SIInstrInfo::getEncodingBytes(const MachineInstr &MI) const } } -MachineInstr * SIInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF, - DebugLoc DL) const -{ - MachineInstr * newMI = AMDGPUInstrInfo::convertToISA(MI, MF, DL); - const MCInstrDesc &newDesc = get(newMI->getOpcode()); - - /* If this instruction was converted to a VOP3, we need to add the extra - * operands for abs, clamp, omod, and negate. */ - if (getEncodingType(*newMI) == SIInstrEncodingType::VOP3 - && newMI->getNumOperands() < newDesc.getNumOperands()) { - MachineInstrBuilder builder(newMI); - for (unsigned op_idx = newMI->getNumOperands(); - op_idx < newDesc.getNumOperands(); op_idx++) { - builder.addImm(0); - } - } - return newMI; -} - -unsigned SIInstrInfo::getISAOpcode(unsigned AMDILopcode) const -{ - switch (AMDILopcode) { - //XXX We need a better way of detecting end of program - case AMDIL::MOVE_f32: return AMDIL::V_MOV_B32_e32; - default: return AMDILopcode; - } -} - MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg, int64_t Imm) const { diff --git a/src/gallium/drivers/radeon/SIInstrInfo.h b/src/gallium/drivers/radeon/SIInstrInfo.h index 6cfbaf4..aa567b6 100644 --- a/src/gallium/drivers/radeon/SIInstrInfo.h +++ b/src/gallium/drivers/radeon/SIInstrInfo.h @@ -42,15 +42,6 @@ public: /// number of bytes. unsigned getEncodingBytes(const MachineInstr &MI) const; - /// convertToISA - Convert the AMDIL MachineInstr to a supported SI - ///MachineInstr - virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF, - DebugLoc DL) const; - - /// getISAOpcode - This function takes an AMDIL opcode as an argument and - /// returns an equivalent SI opcode. - virtual unsigned getISAOpcode(unsigned AMDILopcode) const; - virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg, int64_t Imm) const; |