diff options
Diffstat (limited to 'src/intel/genxml/gen7.xml')
| -rw-r--r-- | src/intel/genxml/gen7.xml | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml index 268ca3d..960df5e 100644 --- a/src/intel/genxml/gen7.xml +++ b/src/intel/genxml/gen7.xml @@ -2508,4 +2508,31 @@ <field name="SW Tessellation Memory Object Control State" start="40" end="43" type="MEMORY_OBJECT_CONTROL_STATE"/> </instruction> + <register name="L3SQCREG1" length="1" num="0xb010"> + <field name="Convert DC_UC" start="24" end="24" type="uint"/> + <field name="Convert IS_UC" start="25" end="25" type="uint"/> + <field name="Convert C_UC" start="26" end="26" type="uint"/> + <field name="Convert T_UC" start="27" end="27" type="uint"/> + </register> + + <register name="L3CNTLREG2" length="1" num="0xb020"> + <field name="SLM Enable" start="0" end="0" type="uint"/> + <field name="URB Allocation" start="1" end="6" type="uint"/> + <field name="URB Low Bandwidth" start="7" end="7" type="uint"/> + <field name="ALL Allocation" start="8" end="13" type="uint"/> + <field name="RO Allocation" start="14" end="19" type="uint"/> + <field name="RO Low Bandwidth" start="20" end="20" type="uint"/> + <field name="DC Allocation" start="21" end="26" type="uint"/> + <field name="DC Low Bandwidth" start="27" end="27" type="uint"/> + </register> + + <register name="L3CNTLREG3" length="1" num="0xb024"> + <field name="IS Allocation" start="1" end="6" type="uint"/> + <field name="IS Low Bandwidth" start="7" end="7" type="uint"/> + <field name="C Allocation" start="8" end="13" type="uint"/> + <field name="C Low Bandwidth" start="14" end="14" type="uint"/> + <field name="T Allocation" start="15" end="20" type="uint"/> + <field name="T Low Bandwidth" start="21" end="21" type="uint"/> + </register> + </genxml> |