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-rw-r--r--src/intel/genxml/gen8.xml8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 96eda70..694e691 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -3163,4 +3163,12 @@
<field name="SW Tessellation Memory Object Control State" start="40" end="43" type="MEMORY_OBJECT_CONTROL_STATE"/>
</instruction>
+ <register name="L3CNTLREG" length="1" num="0x7034">
+ <field name="SLM Enable" start="0" end="0" type="uint"/>
+ <field name="URB Allocation" start="1" end="7" type="uint"/>
+ <field name="RO Allocation" start="11" end="17" type="uint"/>
+ <field name="DC Allocation" start="18" end="24" type="uint"/>
+ <field name="All Allocation" start="25" end="31" type="uint"/>
+ </register>
+
</genxml>