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-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.cpp13
1 files changed, 9 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 3b311ca..0c11a9e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -710,7 +710,9 @@ fs_visitor::no16(const char *msg)
} else {
simd16_unsupported = true;
- perf_debug("SIMD16 shader failed to compile: %s", msg);
+ struct brw_compiler *compiler = brw->intelScreen->compiler;
+ compiler->shader_perf_log(brw,
+ "SIMD16 shader failed to compile: %s", msg);
}
}
@@ -3800,9 +3802,12 @@ fs_visitor::allocate_registers()
fail("Failure to register allocate. Reduce number of "
"live scalar values to avoid this.");
} else {
- perf_debug("%s shader triggered register spilling. "
- "Try reducing the number of live scalar values to "
- "improve performance.\n", stage_name);
+ struct brw_compiler *compiler = brw->intelScreen->compiler;
+ compiler->shader_perf_log(brw,
+ "%s shader triggered register spilling. "
+ "Try reducing the number of live scalar "
+ "values to improve performance.\n",
+ stage_name);
}
/* Since we're out of heuristics, just go spill registers until we