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-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_builder.h14
1 files changed, 11 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_builder.h b/src/mesa/drivers/dri/i965/brw_fs_builder.h
index b50dda4..c1d13a2 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_builder.h
+++ b/src/mesa/drivers/dri/i965/brw_fs_builder.h
@@ -72,7 +72,7 @@ namespace brw {
fs_builder(backend_shader *shader, bblock_t *block, fs_inst *inst) :
shader(shader), block(block), cursor(inst),
_dispatch_width(inst->exec_size),
- _group(inst->force_sechalf ? 8 : 0),
+ _group(inst->group),
force_writemask_all(inst->force_writemask_all)
{
annotation.str = inst->annotation;
@@ -168,6 +168,15 @@ namespace brw {
}
/**
+ * Get the channel group in use.
+ */
+ unsigned
+ group() const
+ {
+ return _group;
+ }
+
+ /**
* Allocate a virtual register of natural vector size (one for this IR)
* and SIMD width. \p n gives the amount of space to allocate in
* dispatch_width units (which is just enough space for one logical
@@ -353,9 +362,8 @@ namespace brw {
assert(inst->exec_size <= 32);
assert(inst->exec_size == dispatch_width() ||
force_writemask_all);
- assert(_group == 0 || _group == 8);
- inst->force_sechalf = (_group == 8);
+ inst->group = _group;
inst->force_writemask_all = force_writemask_all;
inst->annotation = annotation.str;
inst->ir = annotation.ir;