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Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp')
-rw-r--r--src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp53
1 files changed, 15 insertions, 38 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index fb5df2d..776f75d 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -585,8 +585,7 @@ fs_instruction_scheduler::count_reads_remaining(backend_instruction *be)
if (inst->src[i].file == VGRF) {
reads_remaining[inst->src[i].nr]++;
- } else if (inst->src[i].file == HW_REG &&
- inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
+ } else if (inst->src[i].file == FIXED_GRF) {
if (inst->src[i].nr >= hw_reg_count)
continue;
@@ -670,8 +669,7 @@ fs_instruction_scheduler::update_register_pressure(backend_instruction *be)
if (inst->src[i].file == VGRF) {
reads_remaining[inst->src[i].nr]--;
- } else if (inst->src[i].file == HW_REG &&
- inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE &&
+ } else if (inst->src[i].file == FIXED_GRF &&
inst->src[i].nr < hw_reg_count) {
for (int off = 0; off < inst->regs_read(i); off++)
hw_reads_remaining[inst->src[i].nr + off]--;
@@ -700,8 +698,7 @@ fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction *be)
reads_remaining[inst->src[i].nr] == 1)
benefit += v->alloc.sizes[inst->src[i].nr];
- if (inst->src[i].file == HW_REG &&
- inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE &&
+ if (inst->src[i].file == FIXED_GRF &&
inst->src[i].nr < hw_reg_count) {
for (int off = 0; off < inst->regs_read(i); off++) {
int reg = inst->src[i].nr + off;
@@ -959,9 +956,7 @@ fs_instruction_scheduler::calculate_deps()
add_dep(last_grf_write[inst->src[i].nr * 16 + inst->src[i].reg_offset + r], n);
}
}
- } else if (inst->src[i].file == HW_REG &&
- (inst->src[i].brw_reg::file ==
- BRW_GENERAL_REGISTER_FILE)) {
+ } else if (inst->src[i].file == FIXED_GRF) {
if (post_reg_alloc) {
for (int r = 0; r < inst->regs_read(i); r++)
add_dep(last_grf_write[inst->src[i].nr + r], n);
@@ -972,9 +967,7 @@ fs_instruction_scheduler::calculate_deps()
add_dep(last_accumulator_write, n);
} else if (inst->src[i].file != BAD_FILE &&
inst->src[i].file != IMM &&
- inst->src[i].file != UNIFORM &&
- (inst->src[i].file != HW_REG ||
- inst->src[i].brw_reg::file != BRW_IMMEDIATE_VALUE)) {
+ inst->src[i].file != UNIFORM) {
assert(inst->src[i].file != MRF);
add_barrier_deps(n);
}
@@ -1024,8 +1017,7 @@ fs_instruction_scheduler::calculate_deps()
add_dep(last_mrf_write[reg], n);
last_mrf_write[reg] = n;
}
- } else if (inst->dst.file == HW_REG &&
- inst->dst.brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
+ } else if (inst->dst.file == FIXED_GRF) {
if (post_reg_alloc) {
for (int r = 0; r < inst->regs_written; r++)
last_grf_write[inst->dst.nr + r] = n;
@@ -1085,9 +1077,7 @@ fs_instruction_scheduler::calculate_deps()
add_dep(n, last_grf_write[inst->src[i].nr * 16 + inst->src[i].reg_offset + r], 0);
}
}
- } else if (inst->src[i].file == HW_REG &&
- (inst->src[i].brw_reg::file ==
- BRW_GENERAL_REGISTER_FILE)) {
+ } else if (inst->src[i].file == FIXED_GRF) {
if (post_reg_alloc) {
for (int r = 0; r < inst->regs_read(i); r++)
add_dep(n, last_grf_write[inst->src[i].nr + r], 0);
@@ -1098,9 +1088,7 @@ fs_instruction_scheduler::calculate_deps()
add_dep(n, last_accumulator_write, 0);
} else if (inst->src[i].file != BAD_FILE &&
inst->src[i].file != IMM &&
- inst->src[i].file != UNIFORM &&
- (inst->src[i].file != HW_REG ||
- inst->src[i].brw_reg::file != BRW_IMMEDIATE_VALUE)) {
+ inst->src[i].file != UNIFORM) {
assert(inst->src[i].file != MRF);
add_barrier_deps(n);
}
@@ -1149,8 +1137,7 @@ fs_instruction_scheduler::calculate_deps()
last_mrf_write[reg] = n;
}
- } else if (inst->dst.file == HW_REG &&
- inst->dst.brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
+ } else if (inst->dst.file == FIXED_GRF) {
if (post_reg_alloc) {
for (int r = 0; r < inst->regs_written; r++)
last_grf_write[inst->dst.nr + r] = n;
@@ -1218,18 +1205,14 @@ vec4_instruction_scheduler::calculate_deps()
if (inst->src[i].file == VGRF) {
for (unsigned j = 0; j < inst->regs_read(i); ++j)
add_dep(last_grf_write[inst->src[i].nr + j], n);
- } else if (inst->src[i].file == HW_REG &&
- (inst->src[i].brw_reg::file ==
- BRW_GENERAL_REGISTER_FILE)) {
+ } else if (inst->src[i].file == FIXED_GRF) {
add_dep(last_fixed_grf_write, n);
} else if (inst->src[i].is_accumulator()) {
assert(last_accumulator_write);
add_dep(last_accumulator_write, n);
} else if (inst->src[i].file != BAD_FILE &&
inst->src[i].file != IMM &&
- inst->src[i].file != UNIFORM &&
- (inst->src[i].file != HW_REG ||
- inst->src[i].brw_reg::file != BRW_IMMEDIATE_VALUE)) {
+ inst->src[i].file != UNIFORM) {
/* No reads from MRF, and ATTR is already translated away */
assert(inst->src[i].file != MRF &&
inst->src[i].file != ATTR);
@@ -1266,8 +1249,7 @@ vec4_instruction_scheduler::calculate_deps()
} else if (inst->dst.file == MRF) {
add_dep(last_mrf_write[inst->dst.nr], n);
last_mrf_write[inst->dst.nr] = n;
- } else if (inst->dst.file == HW_REG &&
- inst->dst.brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
+ } else if (inst->dst.file == FIXED_GRF) {
last_fixed_grf_write = n;
} else if (inst->dst.is_accumulator()) {
add_dep(last_accumulator_write, n);
@@ -1316,17 +1298,13 @@ vec4_instruction_scheduler::calculate_deps()
if (inst->src[i].file == VGRF) {
for (unsigned j = 0; j < inst->regs_read(i); ++j)
add_dep(n, last_grf_write[inst->src[i].nr + j]);
- } else if (inst->src[i].file == HW_REG &&
- (inst->src[i].brw_reg::file ==
- BRW_GENERAL_REGISTER_FILE)) {
+ } else if (inst->src[i].file == FIXED_GRF) {
add_dep(n, last_fixed_grf_write);
} else if (inst->src[i].is_accumulator()) {
add_dep(n, last_accumulator_write);
} else if (inst->src[i].file != BAD_FILE &&
inst->src[i].file != IMM &&
- inst->src[i].file != UNIFORM &&
- (inst->src[i].file != HW_REG ||
- inst->src[i].brw_reg::file != BRW_IMMEDIATE_VALUE)) {
+ inst->src[i].file != UNIFORM) {
assert(inst->src[i].file != MRF &&
inst->src[i].file != ATTR);
add_barrier_deps(n);
@@ -1359,8 +1337,7 @@ vec4_instruction_scheduler::calculate_deps()
last_grf_write[inst->dst.nr + j] = n;
} else if (inst->dst.file == MRF) {
last_mrf_write[inst->dst.nr] = n;
- } else if (inst->dst.file == HW_REG &&
- inst->dst.brw_reg::file == BRW_GENERAL_REGISTER_FILE) {
+ } else if (inst->dst.file == FIXED_GRF) {
last_fixed_grf_write = n;
} else if (inst->dst.is_accumulator()) {
last_accumulator_write = n;
generated by cgit v1.1 at 2024-06-12 09:21:15 +0000