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-rw-r--r--src/mesa/drivers/dri/intel/intel_tex_layout.c128
1 files changed, 107 insertions, 21 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.c b/src/mesa/drivers/dri/intel/intel_tex_layout.c
index 64f4a70..65645bc 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_layout.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_layout.c
@@ -33,26 +33,113 @@
#include "intel_mipmap_tree.h"
#include "intel_tex_layout.h"
#include "intel_context.h"
+
+#include "main/image.h"
#include "main/macros.h"
+static unsigned int
+intel_horizontal_texture_alignment_unit(struct intel_context *intel,
+ gl_format format)
+{
+ /**
+ * From the "Alignment Unit Size" section of various specs, namely:
+ * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
+ * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
+ * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
+ * - BSpec (for Ivybridge and slight variations in separate stencil)
+ *
+ * +----------------------------------------------------------------------+
+ * | | alignment unit width ("i") |
+ * | Surface Property |-----------------------------|
+ * | | 915 | 965 | ILK | SNB | IVB |
+ * +----------------------------------------------------------------------+
+ * | YUV 4:2:2 format | 8 | 4 | 4 | 4 | 4 |
+ * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
+ * | FXT1 compressed format | 8 | 8 | 8 | 8 | 8 |
+ * | Depth Buffer (16-bit) | 4 | 4 | 4 | 4 | 8 |
+ * | Depth Buffer (other) | 4 | 4 | 4 | 4 | 4 |
+ * | Separate Stencil Buffer | N/A | N/A | 8 | 8 | 8 |
+ * | All Others | 4 | 4 | 4 | 4 | 4 |
+ * +----------------------------------------------------------------------+
+ *
+ * On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
+ * "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
+ */
+ if (_mesa_is_format_compressed(format)) {
+ /* The hardware alignment requirements for compressed textures
+ * happen to match the block boundaries.
+ */
+ unsigned int i, j;
+ _mesa_get_format_block_size(format, &i, &j);
+ return i;
+ }
+
+ if (format == MESA_FORMAT_S8)
+ return 8;
+
+ if (intel->gen >= 7 && format == MESA_FORMAT_Z16)
+ return 8;
+
+ return 4;
+}
+
+static unsigned int
+intel_vertical_texture_alignment_unit(struct intel_context *intel,
+ gl_format format)
+{
+ /**
+ * From the "Alignment Unit Size" section of various specs, namely:
+ * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
+ * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
+ * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
+ * - BSpec (for Ivybridge and slight variations in separate stencil)
+ *
+ * +----------------------------------------------------------------------+
+ * | | alignment unit height ("j") |
+ * | Surface Property |-----------------------------|
+ * | | 915 | 965 | ILK | SNB | IVB |
+ * +----------------------------------------------------------------------+
+ * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
+ * | FXT1 compressed format | 4 | 4 | 4 | 4 | 4 |
+ * | Depth Buffer | 2 | 2 | 2 | 4 | 4 |
+ * | Separate Stencil Buffer | N/A | N/A | N/A | 4 | 8 |
+ * | Multisampled (4x or 8x) render target | N/A | N/A | N/A | 4 | 4 |
+ * | All Others | 2 | 2 | 2 | 2 | 2 |
+ * +----------------------------------------------------------------------+
+ *
+ * On SNB+, non-special cases can be overridden by setting the SURFACE_STATE
+ * "Surface Vertical Alignment" field to VALIGN_2 or VALIGN_4.
+ *
+ * We currently don't support multisampling.
+ */
+ if (_mesa_is_format_compressed(format))
+ return 4;
+
+ if (format == MESA_FORMAT_S8)
+ return intel->gen >= 7 ? 8 : 4;
+
+ GLenum base_format = _mesa_get_format_base_format(format);
+
+ if (intel->gen >= 6 &&
+ (base_format == GL_DEPTH_COMPONENT ||
+ base_format == GL_DEPTH_STENCIL)) {
+ return 4;
+ }
+
+ return 2;
+}
+
void
-intel_get_texture_alignment_unit(gl_format format,
+intel_get_texture_alignment_unit(struct intel_context *intel,
+ gl_format format,
unsigned int *w, unsigned int *h)
{
- if (_mesa_is_format_compressed(format)) {
- /* The hardware alignment requirements for compressed textures
- * happen to match the block boundaries.
- */
- _mesa_get_format_block_size(format, w, h);
- } else {
- *w = 4;
- *h = 2;
- }
+ *w = intel_horizontal_texture_alignment_unit(intel, format);
+ *h = intel_vertical_texture_alignment_unit(intel, format);
}
-void i945_miptree_layout_2d(struct intel_mipmap_tree *mt, int nr_images)
+void i945_miptree_layout_2d(struct intel_mipmap_tree *mt)
{
- GLuint align_h, align_w;
GLuint level;
GLuint x = 0;
GLuint y = 0;
@@ -61,10 +148,9 @@ void i945_miptree_layout_2d(struct intel_mipmap_tree *mt, int nr_images)
GLuint depth = mt->depth0; /* number of array layers. */
mt->total_width = mt->width0;
- intel_get_texture_alignment_unit(mt->format, &align_w, &align_h);
if (mt->compressed) {
- mt->total_width = ALIGN(mt->width0, align_w);
+ mt->total_width = ALIGN(mt->width0, mt->align_w);
}
/* May need to adjust width to accomodate the placement of
@@ -76,10 +162,10 @@ void i945_miptree_layout_2d(struct intel_mipmap_tree *mt, int nr_images)
GLuint mip1_width;
if (mt->compressed) {
- mip1_width = ALIGN(minify(mt->width0), align_w)
- + ALIGN(minify(minify(mt->width0)), align_w);
+ mip1_width = ALIGN(minify(mt->width0), mt->align_w)
+ + ALIGN(minify(minify(mt->width0)), mt->align_w);
} else {
- mip1_width = ALIGN(minify(mt->width0), align_w)
+ mip1_width = ALIGN(minify(mt->width0), mt->align_w)
+ minify(minify(mt->width0));
}
@@ -93,12 +179,12 @@ void i945_miptree_layout_2d(struct intel_mipmap_tree *mt, int nr_images)
for ( level = mt->first_level ; level <= mt->last_level ; level++ ) {
GLuint img_height;
- intel_miptree_set_level_info(mt, level, nr_images, x, y, width,
+ intel_miptree_set_level_info(mt, level, x, y, width,
height, depth);
- img_height = ALIGN(height, align_h);
+ img_height = ALIGN(height, mt->align_h);
if (mt->compressed)
- img_height /= align_h;
+ img_height /= mt->align_h;
/* Because the images are packed better, the final offset
* might not be the maximal one:
@@ -108,7 +194,7 @@ void i945_miptree_layout_2d(struct intel_mipmap_tree *mt, int nr_images)
/* Layout_below: step right after second mipmap.
*/
if (level == mt->first_level + 1) {
- x += ALIGN(width, align_w);
+ x += ALIGN(width, mt->align_w);
}
else {
y += img_height;
generated by cgit v1.1 at 2025-01-10 20:23:48 +0000