diff options
Diffstat (limited to 'src/mesa/drivers/dri')
| -rw-r--r-- | src/mesa/drivers/dri/i915/i915_texstate.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_vector_splitting.cpp | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_reg.h | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_tex_layout.c | 8 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_blit.c | 8 |
6 files changed, 12 insertions, 12 deletions
diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index aef5ff9..f653f44 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -342,7 +342,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) * Thus, I guess we need do this for other platforms as well. */ if (tObj->Target == GL_TEXTURE_CUBE_MAP_ARB && - !is_power_of_two(firstImage->Height)) + !_mesa_is_pow_two(firstImage->Height)) return false; state[I915_TEXREG_SS3] = ss3; /* SS3_NORMALIZED_COORDS */ diff --git a/src/mesa/drivers/dri/i965/brw_fs_vector_splitting.cpp b/src/mesa/drivers/dri/i965/brw_fs_vector_splitting.cpp index 01d3a56..96d4f37 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_vector_splitting.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_vector_splitting.cpp @@ -173,7 +173,7 @@ ir_vector_reference_visitor::visit_enter(ir_assignment *ir) return visit_continue_with_parent; } if (ir->lhs->as_dereference_variable() && - is_power_of_two(ir->write_mask) && + _mesa_is_pow_two(ir->write_mask) && !ir->condition) { /* If we're writing just a channel, then channel-splitting the LHS is OK. */ diff --git a/src/mesa/drivers/dri/i965/brw_reg.h b/src/mesa/drivers/dri/i965/brw_reg.h index c8b1341..4867148 100644 --- a/src/mesa/drivers/dri/i965/brw_reg.h +++ b/src/mesa/drivers/dri/i965/brw_reg.h @@ -853,7 +853,7 @@ static inline struct brw_reg spread(struct brw_reg reg, unsigned s) { if (s) { - assert(is_power_of_two(s)); + assert(_mesa_is_pow_two(s)); if (reg.hstride) reg.hstride += cvt(s) - 1; diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index 85c0864..fb78b08 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -63,7 +63,7 @@ tr_mode_horizontal_texture_alignment(const struct brw_context *brw, int i = 0; /* Alignment computations below assume bpp >= 8 and a power of 2. */ - assert (bpp >= 8 && bpp <= 128 && is_power_of_two(bpp)); + assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp)); switch(mt->target) { case GL_TEXTURE_1D: @@ -95,7 +95,7 @@ tr_mode_horizontal_texture_alignment(const struct brw_context *brw, ret_align = mt->tr_mode == INTEL_MIPTREE_TRMODE_YF ? align_yf[i] : align_ys[i]; - assert(is_power_of_two(mt->num_samples)); + assert(_mesa_is_pow_two(mt->num_samples)); switch (mt->num_samples) { case 2: @@ -199,7 +199,7 @@ tr_mode_vertical_texture_alignment(const struct brw_context *brw, mt->target != GL_TEXTURE_1D_ARRAY); /* Alignment computations below assume bpp >= 8 and a power of 2. */ - assert (bpp >= 8 && bpp <= 128 && is_power_of_two(bpp)) ; + assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp)) ; switch(mt->target) { case GL_TEXTURE_2D: @@ -226,7 +226,7 @@ tr_mode_vertical_texture_alignment(const struct brw_context *brw, ret_align = mt->tr_mode == INTEL_MIPTREE_TRMODE_YF ? align_yf[i] : align_ys[i]; - assert(is_power_of_two(mt->num_samples)); + assert(_mesa_is_pow_two(mt->num_samples)); switch (mt->num_samples) { case 4: diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp index 0483afc..92050b9 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp @@ -1545,7 +1545,7 @@ vec4_generator::generate_code(const cfg_t *cfg) * * where they pack the four bytes from the low and high four DW. */ - assert(is_power_of_two(dst.dw1.bits.writemask) && + assert(_mesa_is_pow_two(dst.dw1.bits.writemask) && dst.dw1.bits.writemask != 0); unsigned offset = __builtin_ctz(dst.dw1.bits.writemask); diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 4fc3fa8..6d92580 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -121,14 +121,14 @@ get_tr_horizontal_align(uint32_t tr_mode, uint32_t cpp, bool is_src) { return 0; /* Compute array index. */ - assert (bpp >= 8 && bpp <= 128 && is_power_of_two(bpp)); + assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp)); i = ffs(bpp / 8) - 1; align = tr_mode == INTEL_MIPTREE_TRMODE_YF ? align_2d_yf[i] : 4 * align_2d_yf[i]; - assert(is_power_of_two(align)); + assert(_mesa_is_pow_two(align)); /* XY_FAST_COPY_BLT doesn't support horizontal alignment of 16. */ if (align == 16) @@ -150,14 +150,14 @@ get_tr_vertical_align(uint32_t tr_mode, uint32_t cpp, bool is_src) { return 0; /* Compute array index. */ - assert (bpp >= 8 && bpp <= 128 && is_power_of_two(bpp)); + assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp)); i = ffs(bpp / 8) - 1; align = tr_mode == INTEL_MIPTREE_TRMODE_YF ? align_2d_yf[i] : 4 * align_2d_yf[i]; - assert(is_power_of_two(align)); + assert(_mesa_is_pow_two(align)); /* XY_FAST_COPY_BLT doesn't support vertical alignments of 16 and 32. */ if (align == 16 || align == 32) |