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* nouveau: avoid build failures since 0fc21ecfIlia Mirkin2015-08-263-3/+3
* gallium/radeon: read_registers should return bool meaning success or failureMarek Olšák2015-08-262-3/+3
* radeonsi: add IB parser support for CP DMA packetsMarek Olšák2015-08-264-61/+122
* radeonsi: add IB tracing support for debug contextsMarek Olšák2015-08-265-16/+105
* radeonsi: remove old CS tracing codeMarek Olšák2015-08-265-47/+3
* radeonsi: parse and dump status registers on GPU hangMarek Olšák2015-08-261-0/+52
* radeonsi: add an IB parserMarek Olšák2015-08-261-0/+245
* radeonsi: save the contents of indirect buffers for debug contextsMarek Olšák2015-08-263-0/+15
* radeonsi: generate register and packet tables for an IB parser from sid.hMarek Olšák2015-08-264-0/+190
* radeonsi: remove duplicated register definitions and instruction definitionsMarek Olšák2015-08-261-3160/+0
* r600g,radeonsi: remove unused ill-formed register field definitionsMarek Olšák2015-08-262-2/+0
* radeonsi: add an initial dump_debug_state implementation dumping shadersMarek Olšák2015-08-264-0/+64
* radeonsi: allow si_dump_key to write to a fileMarek Olšák2015-08-262-18/+19
* gallium/ddebug: new pipe for hang detection and driver state dumping (v2)Marek Olšák2015-08-267-0/+2123
* gallium: add flags parameter to pipe_screen::context_createMarek Olšák2015-08-2630-37/+45
* radeonsi: mark unreachable paths to avoid warningsGrazvydas Ignotas2015-08-262-3/+3
* freedreno/ir3: fix compile break after splitting out nir_control_flow.hRob Clark2015-08-251-0/+1
* freedreno/ir3: fix compile break after fxn->start_block removalRob Clark2015-08-251-1/+1
* freedreno/a4xx: formats updateRob Clark2015-08-241-5/+5
* freedreno: update generated headersRob Clark2015-08-245-5/+8
* nv50: fix 2d engine blits for 64- and 128-bit formatsIlia Mirkin2015-08-231-0/+4
* nv50: account for the int RT0 rule for alpha-to-one/covIlia Mirkin2015-08-233-11/+23
* nv50,nvc0: disable depth bounds test on blitIlia Mirkin2015-08-232-0/+3
* r600g: Fix assert in tgsi_cmpGlenn Kennard2015-08-231-2/+2
* nouveau: add codegen/unordered_set.h to the tarballEmil Velikov2015-08-221-1/+2
* vc4: Actually allow math results to allocate into r4.Eric Anholt2015-08-212-1/+7
* vc4: Fold the 16-bit integer pack into the instructions generating it.Eric Anholt2015-08-215-30/+22
* vc4: Reuse QPU dumping for packing bits in QIR.Eric Anholt2015-08-213-22/+26
* vc4: Make _dest variants of qir ALU helpers to provide an explicit dest.Eric Anholt2015-08-212-4/+20
* vc4: Use the SSA defs list for figuring out eligible MOVs for copy prop.Eric Anholt2015-08-211-12/+10
* util/u_blitter: implement alpha blending for pipe->blitMarek Olšák2015-08-214-4/+8
* vc4: Add algebraic opt for rcp(1.0).Eric Anholt2015-08-201-0/+8
* vc4: Allow unpack_8[abcd]_f's src to stay in r4.Eric Anholt2015-08-201-1/+15
* vc4: Pack the unorm-packing bits into a src MUL instruction when possible.Eric Anholt2015-08-205-16/+104
* vc4: Add a QIR helper for whether the op is a MUL type.Eric Anholt2015-08-203-4/+16
* vc4: Drop an unused algebraic op.Eric Anholt2015-08-201-9/+0
* vc4: Switch QPU_PACK_SCALED to be two non-SSA instructions.Eric Anholt2015-08-205-21/+19
* vc4: Make the pack-to-unorm instructions be non-SSA.Eric Anholt2015-08-204-42/+36
* vc4: Allow QIR registers to be non-SSA.Eric Anholt2015-08-204-4/+10
* vc4: We can now move TEX_RESULT accesses across other r4 ops.Eric Anholt2015-08-201-16/+0
* nv50/ir: pre-compute BFE arg when both bits and offset are immIlia Mirkin2015-08-201-3/+9
* r600g: Fix handling of TGSI_OPCODE_ARR with SBGlenn Kennard2015-08-211-1/+1
* r600: Turn 'r600_shader_key' struct into unionEdward O'Callaghan2015-08-214-38/+42
* r600: Rewrite r600_shader_selector_key() to use a switch stmtEdward O'Callaghan2015-08-211-7/+17
* nv50/ir: Handle OP_CVT when folding constant expressionsTobias Klausmann2015-08-201-0/+78
* nvc0/ir: undo more shifts still by allowing a pre-SHL to occurIlia Mirkin2015-08-201-15/+33
* nvc0/ir: don't require AND when the high byte is being addressedIlia Mirkin2015-08-201-0/+12
* nvc0/ir: detect i2f/i2i which operate on specific bytes/wordsIlia Mirkin2015-08-204-4/+82
* nvc0/ir: detect AND/SHR pairs and convert into EXTBFIlia Mirkin2015-08-201-20/+46
* nv50/ir: support different unordered_set implementationsChih-Wei Huang2015-08-205-12/+57
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