| Commit message (Expand) | Author | Age | Files | Lines |
* | vc4: Actually allow math results to allocate into r4. | Eric Anholt | 2015-08-21 | 2 | -1/+7 |
* | vc4: Fold the 16-bit integer pack into the instructions generating it. | Eric Anholt | 2015-08-21 | 5 | -30/+22 |
* | vc4: Reuse QPU dumping for packing bits in QIR. | Eric Anholt | 2015-08-21 | 3 | -22/+26 |
* | vc4: Make _dest variants of qir ALU helpers to provide an explicit dest. | Eric Anholt | 2015-08-21 | 2 | -4/+20 |
* | vc4: Use the SSA defs list for figuring out eligible MOVs for copy prop. | Eric Anholt | 2015-08-21 | 1 | -12/+10 |
* | util/u_blitter: implement alpha blending for pipe->blit | Marek Olšák | 2015-08-21 | 4 | -4/+8 |
* | vc4: Add algebraic opt for rcp(1.0). | Eric Anholt | 2015-08-20 | 1 | -0/+8 |
* | vc4: Allow unpack_8[abcd]_f's src to stay in r4. | Eric Anholt | 2015-08-20 | 1 | -1/+15 |
* | vc4: Pack the unorm-packing bits into a src MUL instruction when possible. | Eric Anholt | 2015-08-20 | 5 | -16/+104 |
* | vc4: Add a QIR helper for whether the op is a MUL type. | Eric Anholt | 2015-08-20 | 3 | -4/+16 |
* | vc4: Drop an unused algebraic op. | Eric Anholt | 2015-08-20 | 1 | -9/+0 |
* | vc4: Switch QPU_PACK_SCALED to be two non-SSA instructions. | Eric Anholt | 2015-08-20 | 5 | -21/+19 |
* | vc4: Make the pack-to-unorm instructions be non-SSA. | Eric Anholt | 2015-08-20 | 4 | -42/+36 |
* | vc4: Allow QIR registers to be non-SSA. | Eric Anholt | 2015-08-20 | 4 | -4/+10 |
* | vc4: We can now move TEX_RESULT accesses across other r4 ops. | Eric Anholt | 2015-08-20 | 1 | -16/+0 |
* | nv50/ir: pre-compute BFE arg when both bits and offset are imm | Ilia Mirkin | 2015-08-20 | 1 | -3/+9 |
* | r600g: Fix handling of TGSI_OPCODE_ARR with SB | Glenn Kennard | 2015-08-21 | 1 | -1/+1 |
* | r600: Turn 'r600_shader_key' struct into union | Edward O'Callaghan | 2015-08-21 | 4 | -38/+42 |
* | r600: Rewrite r600_shader_selector_key() to use a switch stmt | Edward O'Callaghan | 2015-08-21 | 1 | -7/+17 |
* | nv50/ir: Handle OP_CVT when folding constant expressions | Tobias Klausmann | 2015-08-20 | 1 | -0/+78 |
* | nvc0/ir: undo more shifts still by allowing a pre-SHL to occur | Ilia Mirkin | 2015-08-20 | 1 | -15/+33 |
* | nvc0/ir: don't require AND when the high byte is being addressed | Ilia Mirkin | 2015-08-20 | 1 | -0/+12 |
* | nvc0/ir: detect i2f/i2i which operate on specific bytes/words | Ilia Mirkin | 2015-08-20 | 4 | -4/+82 |
* | nvc0/ir: detect AND/SHR pairs and convert into EXTBF | Ilia Mirkin | 2015-08-20 | 1 | -20/+46 |
* | nv50/ir: support different unordered_set implementations | Chih-Wei Huang | 2015-08-20 | 5 | -12/+57 |
* | radeonsi: fix a typo as_es -> as_ls in a string | Marek Olšák | 2015-08-19 | 1 | -1/+1 |
* | radeonsi: fix indirect indexing of MSAA textures | Marek Olšák | 2015-08-19 | 1 | -4/+13 |
* | util/ra: Make allocating conflict lists optional | Jason Ekstrand | 2015-08-18 | 3 | -3/+4 |
* | freedreno: use fd_pipe_wait_timeout() | Rob Clark | 2015-08-18 | 2 | -21/+1 |
* | freedreno: fence fix | Rob Clark | 2015-08-18 | 3 | -4/+8 |
* | radeon/uvd: remove unused variables | Grazvydas Ignotas | 2015-08-18 | 1 | -4/+1 |
* | nouveau: recognize tess stages in nouveau_compiler | Marcos Paulo de Souza | 2015-08-17 | 1 | -0/+4 |
* | freedreno/a3xx: add s3tc texture format support | Ilia Mirkin | 2015-08-17 | 1 | -0/+9 |
* | freedreno/a3xx: fix up logic for handling block formats | Ilia Mirkin | 2015-08-17 | 3 | -5/+7 |
* | freedreno/a3xx: double the polygon offset value | Ilia Mirkin | 2015-08-17 | 1 | -1/+1 |
* | nvc0: implement the color buffer 0 is integer rule for alpha-to-one/cov | Ilia Mirkin | 2015-08-17 | 3 | -11/+22 |
* | gk110/ir: fix sched calculator to consider all registers in the ISA | Ilia Mirkin | 2015-08-17 | 1 | -7/+10 |
* | nvc0: program smooth line width when multisampling is enabled | Ilia Mirkin | 2015-08-17 | 1 | -1/+1 |
* | nvc0: bind a fake tess control program when there isn't one available | Ilia Mirkin | 2015-08-17 | 4 | -8/+44 |
* | gm107/ir: avoid letting the lowering pass get out of sync | Ilia Mirkin | 2015-08-17 | 2 | -88/+5 |
* | nv50,nvc0: take level into account when doing eng2d multi-layer blits | Ilia Mirkin | 2015-08-17 | 2 | -8/+20 |
* | freedreno/a3xx: add per-texture seamless cubemap control | Ilia Mirkin | 2015-08-16 | 2 | -1/+2 |
* | freedreno/a4xx: add cube map array support | Ilia Mirkin | 2015-08-15 | 4 | -4/+14 |
* | freedreno/a4xx: fix srgb render targets | Rob Clark | 2015-08-15 | 3 | -8/+22 |
* | freedreno: update generated headers | Rob Clark | 2015-08-15 | 5 | -14/+30 |
* | freedreno: expose OES exts for float linear filtering | Ilia Mirkin | 2015-08-14 | 1 | -2/+4 |
* | nvc0: disable tessellation on maxwell | Ilia Mirkin | 2015-08-14 | 1 | -2/+5 |
* | vc4: Move all of our fixed function fragment color handling to NIR. | Eric Anholt | 2015-08-14 | 6 | -388/+538 |
* | vc4: Add a helper for making driver-specific NIR load_uniform for GL state | Eric Anholt | 2015-08-14 | 2 | -2/+30 |
* | nir: Add a nir_opt_undef() to handle csels with undef. | Eric Anholt | 2015-08-14 | 1 | -0/+1 |