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* intel/isl: Add an assert to check zero width/height surfaceAnuj Phogat2016-10-041-0/+3
| | | | | Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* intel/isl: Allow non-2D HiZ surfacesJason Ekstrand2016-10-031-2/+2
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
* intel/isl: Add a detailed comment about multisampling with HiZJason Ekstrand2016-10-031-2/+58
| | | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Chad Versace <chadversary@chromium.org> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
* intel/isl: Remove tiling checks from choose_msaa_layoutJason Ekstrand2016-10-032-14/+7
| | | | | | | | | | | We already do those checks in filter_tiling. There's no good reason to repeat them in choose_msaa_layout. If anything they should have been asserts and not "return false" checks. Also, this check was causing us to outright reject multisampled HiZ surfaces which wasn't intended. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Chad Versace <chadversary@chromium.org> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
* intel/isl: Handle HiZ and CCS tiling more directlyJason Ekstrand2016-10-032-16/+16
| | | | | | | | | | | | The HiZ and CCS tiling formats are always used for HiZ and CCS surfaces respectively. There's no reason why we should go through filter_tiling and it's much easier to always get HiZ and CCS right if we just handle them directly. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chadversary@chromium.org> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
* intel/isl: Allow multisampling with ISL_FORMAT_HiZJason Ekstrand2016-10-032-3/+12
| | | | | | | | | | | | | HiZ buffers can be multisampled and, on Broadwell and earlier, simply using interleaved multisampling with a compression block size of 8x4 samples yields the correct HiZ surface size calculations. Unfortunately, choose_msaa_layout was rejecting multisampled HiZ buffers because of format checks. Now that we have a simple helper for determining if a format supports multisampling, that's an easy enough issue to fix. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Chad Versace <chadversary@chromium.org> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
* intel/isl: Allow creation of 1-D compressed texturesJason Ekstrand2016-10-032-3/+11
| | | | | | | | | | | Compressed 1-D textures are not well-defined thing in either GL or Vulkan. However, auxiliary surfaces are treated as compressed textures in ISL and we can do HiZ and CCS with 1-D so we need to be able to create them. In order to prevent actually using them (the docs say no), we assert in the state setup code. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
* intel/isl: Fix up asserts in calc_phys_level0_extent_saJason Ekstrand2016-10-031-2/+4
| | | | | | | | | | | | | The assertion that a format is uncompressed in the multisample layouts isn't quite right. What we really want to assert is that the format supports multisampling which is a bit more complicated query. We also want to assert that it has a block size of 1x1 since we do nothing with the block size in the phys_level0_sa assignment. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chadversary@chromium.org> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
* intel/isl: Add a format_supports_multisampling helperJason Ekstrand2016-10-035-36/+33
| | | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Chad Versace <chadversary@chromium.org> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
* intel/i965: make gen_device_info mutableLionel Landwerlin2016-09-231-6/+12
| | | | | | | | | | | | Make gen_device_info a mutable structure so we can update the fields that can be refined by querying the kernel (like subslices and EU numbers). This patch does not make any functional change, it just makes gen_get_device_info() fill a structure rather than returning a const pointer. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* isl: Finish tiling filtering for Gen6.Kenneth Graunke2016-09-153-5/+15
| | | | | | | | | | | | | Gen6 only has one additional restriction over Gen7+, so we just add it to the existing gen7 function (which actually covers later gens too). This should stop FINISHME spew when running GL on Sandybridge. v2: Fix bytes per block vs. bits per block confusion (Jason) and rename function to gen6_filter_tiling (Jason and Chad). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* Revert "intel/isl: Ignore base_array_layer and array_len for 3D storage..."Jason Ekstrand2016-09-131-6/+2
| | | | | | | | | This reverts commit 3943888c94beca69e575b8d3d1ec7a6cbf474ee4. It turns out that commit was pretty-much bogus since it breaks binding a 3-D texture as a 2-D storage image. The correct fix for the Vulkan CTS tests needs to be in the Vulkan driver itself rather than ISL. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
* intel/isl: Divide QPitch by 2 for 3-D stencil textures on SKL+Jason Ekstrand2016-09-131-1/+14
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Chad Versace <chadversary@chromium.org>
* isl/state: Don't set QPitch for GEN4_3D surfacesJason Ekstrand2016-09-131-1/+16
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Chad Versace <chadversary@chromium.org>
* intel/isl: Ignore base_array_layer and array_len for 3D storage surfacesJason Ekstrand2016-09-131-2/+6
| | | | | | | | | | | | | | The time we want to restrict the Z range of a 3-D surface is when rendering to it. For storage surfaces, we always want he full range. However, we still need to set MinimumArrayElement and RenderTargetViewExtent to sensible values so we'll just set them to the reasonable defaults we used before we started respecting the base_array_layer and array_len. This fixes a bunch of Vulkan CTS regressions caused by 48f195d7c6483ed. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97790 Reviewed-by: Chad Versace <chadversary@chromium.org>
* intel/isl: Add support for RGB formats in X and Y-tiled memoryJason Ekstrand2016-09-122-14/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Normally, using a non-linear tiling format helps improve cache locality by ensuring that neighboring pixels are usually close-by in memory. For RGB formats, this still sort-of holds, but it can also lead to rather terrible memory access patterns where a single RGB pixel value crosses a tile boundary and gets split into two pieces in different 4K pages. It also makes for some rather awkward calculations because your tile size is no longer an even multiple of surface element size. For these reasons, we chose to simply never create tiled RGB images in the Vulkan driver. The GL driver, however, is not so kind so we need to support it somehow. I briefly toyed with a couple of different schemes but this is the best one I could come up with. The fundamental problem is that a tile no longer contains an integer number of surface elements. I briefly considered a couple other options but found them wanting: 1) Using floats for the logical tile size. This leads to potential rounding error problems. 2) When presented with a RGB format, just make the tile 3-times as wide. This isn't so nice because now our tiles are no longer power-of-two size. Also, it can force the row_pitch to be larger than needed which, while not strictly a problem for ISL, causes incompatibility problems with the way the GL driver chooses surface pitches. The chosen method requires that you pay attention and not just assume that your tile_info is in the units you think it is. However, it's nice because it provides a nice "these are the units" declaration in isl_tile_info itself. Previously, the tile_info wasn't usable as a stand-alone structure because you had to also know the format. It also forces figuring out how to deal with inconsistencies between tiling and format back to the caller which is good because the two different consumers of isl_tile_info really want to deal with it differently: Computation of the surface size wants the fewest number of horizontal tiles possible while get_intratile_offset is far more concerned with things aligning nicely. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Chad Versace <chadversary@chromium.org>
* intel/isl: Allow valign2 for texture-only Y-tiled surfaces on gen7Jason Ekstrand2016-09-121-1/+2
| | | | | | | | | | The restriction that Y-tiled surfaces must have valign == 4 only aplies to render targets but we were applying it universally. This causes problems if ISL_FORMAT_R32G32B32_FLOAT is used because it requires valign == 2; this should be okay because you can't render to that format. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Chad Versace <chadversary@chromium.org>
* intel/isl: Add a helper for getting the size of an interleaved pixelJason Ekstrand2016-09-122-5/+20
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* intel/isl: Fix an assert in get_intratile_offset_saJason Ekstrand2016-09-121-1/+1
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* intel/isl: Add an isl_swizzle structure and use it for isl_view swizzlesJason Ekstrand2016-09-122-5/+21
| | | | | | | | | This should be more compact than the enum isl_channel_select[4] that we were using before. It's also very convenient because we already had such a structure in the Vulkan driver we just needed to pull it over. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* intel/isl: Treat 3-D textures as 2-D arrays for renderingJason Ekstrand2016-09-122-4/+13
| | | | | | | | | | In particular, this means that isl_view::base_array_layer and isl_view::array_len get applied to 3-D textures but only when rendering. We were already applying isl_view::base_array_layer for rendering into 3-D textures so this isn't a huge deviation. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* isl/gen8+: Allow 1D and 3D auxiliary surfacesTopi Pohjolainen2016-09-121-1/+2
| | | | | | | | | | | | | Otherwise once mcs buffer gets allocated without delay for lossless compression (same as we do for msaa), assert starts to fire in piglit case: tex3d. The test uses depth of one which is in fact supported even now. v2 (Jason): Allow also 1D case as there is nothing in the specs constraining it either. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* intel: Rename brw_get_device_name/info to gen_get_device_name/infoJason Ekstrand2016-09-031-3/+3
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* intel: s/brw_device_info/gen_device_info/Jason Ekstrand2016-09-036-24/+24
| | | | | | | | | | | | | Generated by: sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.c sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.h sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.c sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.cpp sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.h Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* intel: Add a new "common" library for more code sharingJason Ekstrand2016-09-033-3/+3
| | | | | | | The first thing to go in this new library is brw_device_info. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* isl: round format alignment to nearest power of 2Lionel Landwerlin2016-09-012-0/+10
| | | | | | | | | | | | A few inline asserts in anv assume alignments are power of 2, but with formats like R8G8B8 we have odd alignments. v2: round up to power of 2 (Ilia) v3: reuse util_next_power_of_two() from gallium/aux/util/u_math.h (Ilia) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* isl/state: Add some asserts about format capabilitiesJason Ekstrand2016-08-291-0/+5
| | | | | | | | | | This keeps invalid surface states from leaking through and potentially hanging the GPU. We shouldn't actually be hitting this on a regular basis, but a helpful assert is better than a hang. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
* android: intel: Flatten the makefile structureMauro Rossi2016-08-291-217/+0
| | | | | | | | | | | Android porting of commit bebc1a1 "intel: Flatten the makefile structure" Automake approach was followed, by moving makefiles a level up, naming them Android.genxml.mk and Android.isl.mk, performing the necessary adjustments to the paths, adding src/intel/Android.mk and fixing mesa top level makefile. Acked-by: Jason Ekstrand <jason@jlekstrand.net>
* isl: Allow multisampled array texturesJason Ekstrand2016-08-261-4/+4
| | | | | | | | | | | This probably isn't the only thing that needs to be done to get multisampled array textures working in Vulkan but I think this is all that ISL really needs and it does fix 8 of the new CTS tests. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Cc: "12.0" <mesa-stable@lists.freedesktop.org> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chadversary@chromium.org>
* intel: Flatten the makefile structureJason Ekstrand2016-08-253-149/+1
| | | | | | | | | | This pulls isl and genxml into a single make file so that they can properly build in parallel. This isn't terribly important now as genxml just generates sources which happens serially first anyway but it will be more important as we add more stuff to src/intel. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Matt Turner <mattst88@gmail.com>
* isl/tests: Use a longer path for isl.hJason Ekstrand2016-08-251-2/+2
| | | | | | | | | The tests assumed that isl would be in the include path but that usually isn't the case. Instead, we usually have src/intel and you need to add an "isl/" prefix. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Matt Turner <mattst88@gmail.com>
* intel/isl/gen9: Only use the magic 1D alignment for GEN9_1D surfacesJason Ekstrand2016-08-251-1/+1
| | | | | | | | | If the surface has a layout of GEN4_2D then we need to compute a normal 2D alignment and not use the magic linewar 1D alignment. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chadversary@chromium.org>
* intel/isl: Pass the dim_layout into choose_alignment_elJason Ekstrand2016-08-2511-13/+24
| | | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chadversary@chromium.org>
* intel/isl: Use DIM_LAYOUT_GEN4_2D for tiled 1-D surfaces on SKLJason Ekstrand2016-08-251-5/+23
| | | | | | | | | The Sky Lake 1D layout is only used if the surface is linear. For tiled surfaces such as depth and stencil the old gen4 2D layout is used. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chadversary@chromium.org>
* isl/formats: Integer formats are not filterableJason Ekstrand2016-08-231-8/+8
| | | | | | | | | In ca2a8e56285, we updated the format table to add more formats (most of which are new on SKL) but accidentally marked some integer formats as filterable. You can't filter an integer format. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
* isl/formats: Update the table with more samplable formatsJason Ekstrand2016-08-231-15/+15
| | | | | | | | There were a lot of formats where support was added on Haswell or later but we never updated the format table. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
* isl/formats: Report ETC as being samplable on Bay TrailJason Ekstrand2016-08-231-0/+18
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
* isl: automake: use VISIBILITY_CFLAGS to restrict symbol visibilityEmil Velikov2016-08-181-8/+10
| | | | | | | | v2: Add VISIBILITY_CFLAGS to AM_CFLAGS (Ken) Cc: "12.0" <mesa-stable@lists.freedesktop.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v1) Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
* isl/state: Only set clear color if aux is usedJason Ekstrand2016-08-171-25/+27
| | | | | | | Otherwise, the clear color will get ignored. This prevents assertion errors if clear color is set to something invalid and aux is not used. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* isl: Add helpers for creating different types of aux surfacesJason Ekstrand2016-08-172-0/+136
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* isl/state: Add an assertion for IVB multisample array texturesJason Ekstrand2016-08-171-0/+13
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* isl: Add a #define for DEV_IS_BAYTRAILJason Ekstrand2016-08-171-0/+4
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* isl: Add asserts for gen8+ X/YOffset rulesJason Ekstrand2016-08-171-0/+10
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* isl: Take the slice0_extent shortcut for interleaved MSAAJason Ekstrand2016-08-171-1/+1
| | | | | | The shortcut works just fine for MSAA and the comment even says so. Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
* isl: Remove duplicate px->sa conversionsJason Ekstrand2016-08-171-20/+0
| | | | | | | | In all three cases, we start with width and height taken from isl_surf::phys_slice0_extent_sa which is already in samples. There is no need to do the conversion and doing so gives us an incorrect value. Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
* isl: Add functions for computing surface offsets in samplesJason Ekstrand2016-08-172-12/+60
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* isl: Fix get_image_offset_sa_gen4_2d for multisample surfacesJason Ekstrand2016-08-171-4/+9
| | | | | | | | | The function takes a logical array layer but was assuming it was a physical array layer. While we'er here, we also make it not assert-fail on gen9 3-D surfaces. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* isl/state: Use a valid alignment for 1-D texturesJason Ekstrand2016-08-171-1/+1
| | | | | | | The alignment we use doesn't matter (see the comment) but it should at least be an alignment we can represent with the enums. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* isl: Fix the parameter names for get_intratile_offsetJason Ekstrand2016-08-171-4/+4
| | | | | | | | It's been in elements for a while but, for whatever reason, the parameter names in the header file never got updated. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* isl: Add a helper for getting a depth format from an isl_formatJason Ekstrand2016-08-082-0/+26
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
generated by cgit v1.1 at 2025-05-30 14:42:48 +0000