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* intel: s/brw_device_info/gen_device_info/Jason Ekstrand2016-09-031-1/+1
| | | | | | | | | | | | | Generated by: sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.c sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.h sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.c sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.cpp sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.h Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* i965: remove trailing spaces in various filesIago Toral Quiroga2015-11-251-4/+4
| | | | Acked-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Drop #include of main/glheader.h.Matt Turner2015-11-241-1/+0
| | | | | | It's never used. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* i965: Rename brw_compile to brw_codegenJason Ekstrand2015-04-221-8/+8
| | | | | | | | | | | | This name better matches what it's actually used for. The patch was generated with the following command: for file in *; do sed -i -e s/brw_compile/brw_codegen/g $file done Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
* i965: Remove the context field from brw_compilerJason Ekstrand2015-04-221-2/+2
| | | | Reviewed-by: Matt Turner <mattst88@gmail.com>
* i965: Make the brw_inst helpers take a device_info instead of a contextJason Ekstrand2015-04-221-25/+20
| | | | Reviewed-by: Matt Turner <mattst88@gmail.com>
* mesa: Replace IS_NEGATIVE(x) with x < 0.0f.Matt Turner2014-09-251-2/+2
| | | | | | | | I only made IS_NEGATIVE(x) use signbit in commit 0f3ba405 in an attempt to fix 54805, but it didn't help. We didn't use signbit on some platforms and instead defined it to x < 0.0f. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Convert Gen4-5 clipping code to the new brw_inst API.Kenneth Graunke2014-06-261-19/+25
| | | | | Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
* i965: Drop the remaining default predication whacking.Kenneth Graunke2014-06-071-0/+1
| | | | | | | | | | With my earlier cleaning in place (see git log brw_eu_emit.c), nothing relies on the instruction emitters for IF/WHILE/JMPI disabling predication. Drop it in favor of making callers do the right thing explicitly. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* i965: Put '_default_' in the name of functions that set default state.Kenneth Graunke2014-06-021-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
* i965: Eliminate brw_set_conditionalmod from the Gen4-5 compilers.Kenneth Graunke2014-06-021-9/+9
| | | | | | | | | With the predication changes eliminated, all this does is set the conditional modifier on a single instruction. Doing that directly is easy, and avoids mucking about with default state. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
* i965: Stop setting predication from brw_set_conditionalmod.Kenneth Graunke2014-06-021-0/+2
| | | | | | | | | | | | | brw_set_conditionalmod has traditionally been complex: it causes conditionalmod to be set for the next instruction, and then predication to be set on all future instructions after that. We may want to generate a flag condition and not use it immediately, due to instruction scheduling or the like. Even if not, it's easy to set things explicitly, and that's clearer. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
* i965: Drop unnecessary brw_set_conditionalmod() before brw_CMP().Kenneth Graunke2014-06-021-1/+0
| | | | | | | | | | | brw_CMP already takes a conditional modifier as a parameter, and sets it accordingly. brw_set_conditionalmod() also makes everything after the next instruction predicated, but we don't need that: we always emit an IF instruction after load_clip_distance(), and that's already predicated. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
* i965/clip: Use the new brw_last_inst macro instead of temporaries.Kenneth Graunke2014-06-021-18/+16
| | | | | | | | It wasn't too bad before, but the macro is going to be nicer once I start modifying a lot more instructions in this pattern. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
* i965: Don't implicitly set predicate default state in brw_CMP.Kenneth Graunke2014-05-271-16/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, brw_CMP with a null destination implicitly set the default state to make future instructions predicated. This is messy and confusing - emitting a CMP that populates the flag register and later using it to predicate instructions are logically separate. With the main compiler, we may even schedule instructions between the CMP and the user of the flag value. This patch simplifies brw_CMP to just emit a CMP instruction, and not mess with predication. It also updates all necessary callers. These mostly fell into two patterns: 1. brw_CMP followed by brw_IF. We don't need to do anything special here; brw_IF already sets up predication appropriately. 2. brw_CMP followed by a single predicated instruction. The old model was to call brw_CMP, emit the next (predicated) instruction, then disable predication for any instructions beyond that. Instead, just explicitly set predicate_control on the single instruction we want to predicate. It's no more code, and requires less cross-module knowledge. This drops setting flag_value to 0xff as well, which is a field only used by the SF compile. There is only one brw_CMP call in the SF code, which is in do_twoside_caller, and called at the start of brw_emit_tri_setup, where flag_value is already 0xff. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
* i965: Drop unnecessary predication default state resets in clip code.Kenneth Graunke2014-05-271-6/+0
| | | | | | | | | Presumably, this was to reset the default state of predication_control from brw_CMP. But brw_CMP only sets that if dst is ARF null, which it isn't here. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
* s/Tungsten Graphics/VMware/José Fonseca2014-01-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the old copyright name is creating unnecessary confusion, hence this change. This was the sed script I used: $ cat tg2vmw.sed # Run as: # # git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed # # Rename copyrights s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g /Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./ s/TUNGSTEN GRAPHICS/VMWARE/g # Rename emails s/alanh@tungstengraphics.com/alanh@vmware.com/ s/jens@tungstengraphics.com/jowen@vmware.com/g s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/ s/jrfonseca\?@tungstengraphics.com/jfonseca@vmware.com/g s/keithw\?@tungstengraphics.com/keithw@vmware.com/g s/michel@tungstengraphics.com/daenzer@vmware.com/g s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/ s/zack@tungstengraphics.com/zackr@vmware.com/ # Remove dead links s@Tungsten Graphics (http://www.tungstengraphics.com)@Tungsten Graphics@g # C string src/gallium/state_trackers/vega/api_misc.c s/"Tungsten Graphics, Inc"/"VMware, Inc"/ Reviewed-by: Brian Paul <brianp@vmware.com>
* i965: Drop trailing whitespace from the rest of the driver.Kenneth Graunke2013-12-051-40/+40
| | | | | | | Performed via: $ for file in *; do sed -i 's/ *//g'; done Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Combine 4 boolean args of brw_urb_WRITE into a flags bitfield.Paul Berry2013-08-231-3/+3
| | | | | | | | | | | | The arguments to brw_urb_WRITE() were getting pretty unwieldy, and we have to add more flags to support geometry shaders anyhow. Also plumb these flags through brw_clip_emit_vue(), brw_set_urb_message(), and the vec4_instruction class. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
* i965: allow 8 user clip planes on CTG+Chris Forbes2013-08-161-2/+2
| | | | | | | | | | | | | There's no need to use a clip flag for NEGW on these gens, so no reason we can't just enable 8 planes. V2: - Bump (and document!) MAX_VERTS in the clip code. - Fix clip flag masks in the clip unit state and in the shader prolog - Move this to the end of the series for less breakage. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
* i965/clip: remove spurious clipvertex paramChris Forbes2013-08-161-11/+4
| | | | | | | | | | Nothing in the clipper uses gl_ClipVertex any more, so we don't care where it is. V2: Don't bother fishing out the clipvertex offset either. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
* i965/clip: Use clip distances for all user clippingChris Forbes2013-08-161-5/+6
| | | | | | | V2: Adjust explanation of load_clip_distance() Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
* i956/clip: push dp4 into load_clip_distanceChris Forbes2013-08-161-17/+22
| | | | | | | | | | Soon the dp4 is only going to be used for fixed clip planes. V2: Remove old inaccurate comment about the behavior of this function; add a better explanation above. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
* i965/clip: Track offset into the vertex for clipdistanceChris Forbes2013-08-161-0/+9
| | | | | Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
* i965 Gen4/5: clip: correctly handle flat varyingsChris Forbes2013-08-011-9/+9
| | | | | | | | | | | | | | | | Previously we only gave special treatment to the builtin color varyings. This patch adds support for arbitrary flat-shaded varyings, which is required for GLSL 1.30. Based on Olivier Galibert's patch from last year: http://lists.freedesktop.org/archives/mesa-dev/2012-July/024340.html V5: Move key.do_flat_shading to brw_clip_compile.has_flat_shading V6: Real bools. [V1-2]: Signed-off-by: Olivier Galibert <galibert at pobox.com> Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Move intel_context::gen and gt fields to brw_context.Kenneth Graunke2013-07-091-2/+2
| | | | | | | | | | Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
* i965: Replace intel_context:needs_ff_sync with intel->gen == 5.Kenneth Graunke2013-07-091-1/+1
| | | | | | | | | | | | | Technically, needs_ff_sync was set on Gen5+, but it was only consulted in the clipper threads and quad/lineloop decomposition code, which are both Gen4-5 only. So in reality it only identified Ironlake. The named flag doesn't really clarify things, and seems like overkill. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
* i965/clip: Add support for gl_ClipVertexChris Forbes2013-06-071-4/+44
| | | | | | | | | | | When clipping triangles against a user clip plane, and gl_ClipVertex is provided in the vertex, use it instead of hpos. TODO: A similar change should be made at some point for line clipping. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Clarify nomenclature: vert_result -> varyingPaul Berry2013-03-231-3/+2
| | | | | | | | | | | | | | | | | | This patch removes the terminology "vert_result" from the i965 driver, replacing it with "varying". The old terminology, "vert_result", was confusing because (a) it referred to the enum gl_vert_result, which no longer exists (it was replaced with gl_varying_slot), and (b) it implied a vertex output, but with the advent of geometry shaders, it could be either a vertex or a geometry output, depending what shaders are in use. The generic term "varying" is less confusing. No functional change. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> v2: Whitespace fixes.
* Replace gl_vert_result enum with gl_varying_slot.Paul Berry2013-03-151-2/+2
| | | | | | | | | | | This patch makes the following search-and-replace changes: gl_vert_result -> gl_varying_slot VERT_RESULT_* -> VARYING_SLOT_* Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Tested-by: Brian Paul <brianp@vmware.com>
* i965: Don't make consumers of brw_DO()/brw_WHILE() track loop start.Eric Anholt2011-12-211-9/+6
| | | | | | | This is a similar cleanup to what we did for brw_IF(), brw_ELSE(), brw_ENDIF() handling. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
* i965: Clean up misleading defines for DWORD 2 of URB_WRITE header.Paul Berry2011-12-071-3/+8
| | | | | | | | | | | | | R02_PRIM_END and R02_PRIM_START don't actually refer to bits in DWORD 2 of R0 (as the name, and comments in the code, would seem to indicate). Actually they refer to bits in DWORD 2 of the header for URB_WRITE messages. This patch renames the defines to reflect what they actually mean. It also addes a define URB_WRITE_PRIM_TYPE_SHIFT, which previously was just hardcoded in .c files. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* intel: Convert from GLboolean to 'bool' from stdbool.h.Kenneth Graunke2011-10-181-2/+2
| | | | | | | | | | | | | | | | | I initially produced the patch using this bash command: for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i 's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i 's/GL_FALSE/false/g' $file; done Then I manually added #include <stdbool.h> to fix compilation errors, and converted a few functions back to GLboolean that were used in core Mesa's function pointer table to avoid "incompatible pointer" warnings. Finally, I cleaned up some whitespace issues introduced by the change. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chad Versace <chad@chad-versace.us> Acked-by: Paul Berry <stereotype441@gmail.com>
* i965: clip: Convert computations to ..._to_offset() for clarity.Paul Berry2011-09-061-1/+1
| | | | | | | | This patch replaces some ad-hoc computations using ATTR_SIZE and the offset[] array to use the VUE map functions brw_vert_result_to_offset() and brw_vue_slot_to_offset(). Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: clip: Modify brw_clip_tri_alloc_regs() to use the VUE map.Paul Berry2011-09-061-2/+5
| | | | Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: clip: Move hpos_offest and ndc_offset into local functions.Paul Berry2011-09-061-6/+11
| | | | | | | | | The offsets within the VUE of HPOS and NDC are needed only in a few auxiliary clipping functions. This patch moves computation of those offsets into the functions that need them, and does the computation using the VUE map. Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: Move IF stack handling into the EU abstraction layer/brw_compile.Kenneth Graunke2011-05-171-37/+29
| | | | | | | | This hides the IF stack and back-patching of IF/ELSE instructions from each of the code generators, greatly simplifying the interface. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: Reduce repeated calculation of the attribute-offset-in-VUE.Eric Anholt2010-07-191-4/+1
| | | | | | This cleans up some chipset dependency sprinkled around, and fixes a potential overflow of the attribute offset array for many vertex results.
* mesa: rename src/mesa/shader/ to src/mesa/program/Brian Paul2010-06-101-1/+1
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* i965: Set the correct provoking vertex for clipped first-mode trifans.Eric Anholt2010-05-141-3/+17
| | | | Bug #24470: glean clipFlat test.
* intel: Clean up chipset name and gen num for IronlakeZhenyu Wang2010-04-211-1/+1
| | | | | | | | | Rename old IGDNG to Ironlake, and set 'gen' number for Ironlake as 5, so tracking the features with generation num instead of special is_ironlake flag. Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
* Merge branch 'mesa_7_7_branch'Brian Paul2010-01-251-1/+0
|\ | | | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/intel/intel_screen.c src/mesa/drivers/dri/intel/intel_swapbuffers.c src/mesa/drivers/dri/r300/r300_emit.c src/mesa/drivers/dri/r300/r300_ioctl.c src/mesa/drivers/dri/r300/r300_tex.c src/mesa/drivers/dri/r300/r300_texstate.c
| * i965: Remove unnecessary headers.Vinson Lee2010-01-221-1/+0
| |
* | intel: Replace IS_965 checks with context structure usage.Eric Anholt2009-12-221-1/+2
| | | | | | | | Saves another 600 bytes or so of code.
* | intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.Eric Anholt2009-12-221-2/+3
|/ | | | Saves ~480 bytes of code.
* i965: fix EXT_provoking_vertex supportRoland Scheidegger2009-11-111-3/+9
| | | | | | | | This didn't work for quad/quadstrips at all, and for all other primitive types it only worked when they were unclipped. Fix up the former in gs stage (could probably do without these changes and instead set QuadsFollowProvokingVertexConvention to false), and the rest in clip stage.
* i965: Postpone ff_sync message in CLIP kernel on IGDNGXiang, Haihao2009-07-301-2/+6
| | | | In addition, it guarantees ff_sync message is issued
* i965: add support for new chipsetsXiang, Haihao2009-07-131-3/+10
| | | | | | | | | | 1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
* i965: fix for RHW workaroundXiang, Haihao2009-02-261-20/+56
| | | | | | It is possible that an object whose vertices all are outside of a view plane is passed to clip thread due to the RHW workaround. This object should be rejected by clip thread. Fix bug #19879
* i965: Merge GM45 into the G4X chipset define.Eric Anholt2008-11-021-1/+1
| | | | | The mobile and desktop chipsets are the same, and having them separate is more typing and more chances to screw up.
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