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* intel/i965: make gen_device_info mutableLionel Landwerlin2016-09-231-1/+1
| | | | | | | | | | | | Make gen_device_info a mutable structure so we can update the fields that can be refined by querying the kernel (like subslices and EU numbers). This patch does not make any functional change, it just makes gen_get_device_info() fill a structure rather than returning a const pointer. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Rename intelScreen to screen.Kenneth Graunke2016-09-201-1/+1
| | | | | | | | "intelScreen" is wordy and also doesn't fit our style guidelines. "screen" is shorter, which is nice, because we use it fairly often. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
* intel: s/brw_device_info/gen_device_info/Jason Ekstrand2016-09-031-1/+1
| | | | | | | | | | | | | Generated by: sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.c sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.h sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.c sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.cpp sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.h Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* i965/surface_formats: Don't advertise 8 or 16-bit RGB formatsJason Ekstrand2016-08-231-0/+10
| | | | | | | | | | | | | We have implicitly been not advertising these formats since we had them turned off in the format capabilities table. We are about to update that table and this prevents a change in behavior. The only change in behavior created by this patch is that we no longer advertise support for R16G16B16_FLOAT which means that it's now renderable which seems like a bonus. Maybe someday we'll want to change things to start supporting 16-bit RGB formats natively but, at the moment, there's no need. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
* i965: Use ISL for surface format introspectionJason Ekstrand2016-05-231-335/+9
| | | | | With this, we can delete the surface format table in brw_surface_formats.c because all of the information we need is now in ISL.
* i965/surface_formats: Update the VB column for new formats added on BYTJason Ekstrand2016-05-231-20/+20
| | | | | | | Bay Trail and Haswell added a bunch of new vertex formats. There was also the addition of 64-bit passthrough formats for BDW+. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Unset alpha blend for R10G10B10_SNORM_A2_UNORMNanley Chery2016-05-231-1/+1
| | | | | | | This format does not support alpha blending, according to the SNB PRM. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* i965: Enable ARB_texture_stencil8 and OES_texture_stencil8 on Gen8+.Kenneth Graunke2016-04-261-0/+1
| | | | | | | | | | | | | | | | | | | | | Stencil texturing is required by ES 3.1. Apparently we never actually turned it on. Do that now. Also turn on the desktop extension. Fixes nine dEQP-GLES31.functional tests: stencil_texturing.format.stencil_index8_2d texture.border_clamp.formats.stencil_index8.nearest_size_pot texture.border_clamp.formats.stencil_index8.nearest_size_npot texture.border_clamp.formats.stencil_index8.gather_size_pot texture.border_clamp.formats.stencil_index8.gather_size_npot texture.border_clamp.unused_channels.stencil_index8 state_query.internal_format.renderbuffer.stencil_index8_samples state_query.internal_format.texture_2d_multisample.stencil_index8_samples state_query.internal_format.texture_2d_multisample_array.stencil_index8_samples Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
* i965: Disable KHR_texture_compression_astc_hdr on Gen9Nanley Chery2016-04-221-3/+3
| | | | | | | | | | | | Although Gen9 samples from most HDR ASTC surfaces of correctly, there currently are no software workarounds to fix the incorrect sampling that occurs in others of certain color endpoint modes. With this change, we are no longer failing the 14 tests from: dEQP-GLES3.functional.texture.compressed.astc.endpoint_value_hdr_cem_15.* Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/surface_state: Use libisl functions for image format loweringJason Ekstrand2016-04-211-109/+0
| | | | | | | This lets us delete some redundant code and keep all of the image_load_store format lowering logic in one place: libisl. Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965/surface_formats: Update some formats for more recent gensJason Ekstrand2016-04-151-12/+12
| | | | | | | | The surface format table hasn't entirely been kept up-to-date. This commit marks a couple more compressed formats as sampleable on gen8+ and adds the A4B4G4R4 format as renderable on gen9. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Expose the surface format tableJason Ekstrand2016-04-141-18/+4
| | | | Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Allow 8x MSAA on >= 64bpp formats on Gen8+.Kenneth Graunke2016-04-041-1/+2
| | | | | | | | | | | See commit 3b0279a69 - this restriction is documented in the "Surface Format" field of RENDER_SURFACE_STATE. Looking at newer documentation, this restriction appears to exist on Haswell, but no longer applies on Gen8+. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
* i965: Use constant pointer when checking for compressionTopi Pohjolainen2016-02-101-1/+1
| | | | | Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
* i965/gen9: Don't allow the RGBX formats for texturing/renderingNeil Roberts2016-01-131-0/+28
| | | | | | | | | | | | | | | | | The RGBX surface formats aren't renderable so we internally remap them to RGBA when rendering. They are retained as RGBX when used as textures. However since the previous patch fast clears are disabled for surfaces that use a different format for rendering than for texturing. To avoid this situation we can just pretend not to support RGBX formats at all. This will cause the upper layers of mesa to pick an RGBA format internally instead. This should be safe because we always override the alpha component to 1.0 for RGBX in the texture swizzle anyway. We could also do this for all gens except that it's a bit more difficult when the hardware doesn't support texture swizzling. Gens using the blorp have further problems because that doesn't implement this swizzle override. Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
* i965: Add B8G8R8X8_SRGB to the alpha format overrideNeil Roberts2015-12-131-0/+4
| | | | | | | | | | | brw_init_surface_formats overrides the render format for RGBX formats which aren't supported for rendering so that they internally use RGBA instead. However, B8G8R8X8_SRGB was missing so it wasn't marked as a renderable format. This patch just adds it. Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org> Cc: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Add MESA_FORMAT_B8G8R8X8_SRGB to brw_format_for_mesa_formatNeil Roberts2015-12-131-0/+1
| | | | | | | | | This will be used in a subsequent patch as the format for RGB visuals. Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org> Cc: Ilia Mirkin <imirkin@alum.mit.edu> Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/gen8: Allow rendering to B8G8R8X8Neil Roberts2015-12-101-4/+5
| | | | | | | | | Since Gen8 this is allowed as a rendering target so we don't need to override it to B8G8R8A8. This is helpful on Gen9+ where using this override causes fast clears not to work. Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
* i965: Clean up #includes in the compiler.Matt Turner2015-11-241-2/+0
| | | | Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* i965/skl: skip fast clears for certain surface formatsBen Widawsky2015-11-201-26/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the information originally in this commit message is now in the patch before this. SKL adds compressible render targets and as a result mutates some of the programming for fast clears and resolves. There is a new internal surface type called the CCS. The old AUX_MCS bit becomes AUX_CCS_D. "Auxiliary Surfaces For Sampled Tiled Resource". The formats which are supported are defined in the table titled "Render Target Surface Types [SKL+]". There is no PRM yet to reference. The previously implemented helper function already does the right thing provided the table is correct. v2: Use better English in commit message (Matt) s/compressable/compressible/ (Matt) Don't compare bools to true (Matt) Use the helper function and don't increase the context size - this is mostly implemented in the patch just before this (Chad, Neil) Remove an "invalid" assert (Chad) Fix assertion to check num_samples > 1, instead of num_samples (Chad) v3: Use Matt's code as Requested-by: Chad. I didn't even look at it since Chad said he was fine with that, and presumably Matt is fine with it. v4: Use better quote from spec (Topi) Cc: Chad Versace <chad.versace@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Add lossless compression to surface format tableBen Widawsky2015-11-201-251/+274
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Background: Prior to Skylake and since Ivybridge Intel hardware has had the ability to use a MCS (Multisample Control Surface) as auxiliary data in "compression" operations on the surface. This reduces memory bandwidth. This hardware was either used for MSAA compression, or fast clear operations. On Gen8, a similar mechanism exists to allow the hiz buffer to be sampled from, and therefore this feature is sometimes referred to more generally as "AUX buffers". Skylake adds the ability to have the display engine directly source compressed surfaces on top of the ability to sample from them. Inference dictates that enabling this display features adds a restriction to the formats which could actually be compressed. This is backed up by a blurb in the AUX_CCS_D section from the RENDER_SURFACE_STATE: "In addition, if the surface is bound to the sampling engine, Surface Format must be supported for Render Target Compression for surfaces bound to the sampling engine." The current set of surfaces seems to be a subset as compared to previous gens (see the next patch). Also, if I had to guess I would guess that future gens add support for more surface formats. To make handling this a bit easier to read, and more future proof, the support for this is moved into the surface formats table. Along with the modifications to the table, a helper function is also provided to determine if a surface is CCS_E compatible. Because fast clears are currently disabled on SKL, we can plumb the helper all the way through here, and not actually have anything break. v2: - rename ccs to ccs_e; Requested-by: Chad - rename lossless_compression to lossless_compression Requested-by: Chad - change meaning of brw_losslessly_compressible_format Requested-by: Chad - related changes to the code to reflect this. - remove excess ccs (Chad) v3: - Commit message changes (Topi) - Const some things which could be const (Topi) Requested-by: Chad Versace <chad.versace@intel.com> Requested-by: Neil Roberts <neil@linux.intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
* i965/surface_formats: add support for 2D ASTC surface formatsNanley Chery2015-08-261-0/+87
| | | | | | | | | | | | | | | | | | Define two-thirds of the 2D Intel ASTC surface formats (LDR-only). This allows a 1-to-1 mapping from the mesa format to the Intel format. ASTC textures will default to being processed in LDR mode. If there is hardware support for HDR/Full mode and the texture is not sRGB, add the format bit necessary to process it in HDR/Full mode. v2: remove extra newlines. v3: follow existing coding style in translate_tex_format(). v4: expound on the GEN9_SURFACE_ASTC_HDR_FORMAT_BIT comment. update SF table - ASTC is actually supported in Gen8. v5: conform the ASTC MESA_FORMAT enums to the existing naming convention. Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
* i965: Implement surface state set-up for shader images.Francisco Jerez2015-08-111-0/+109
| | | | | | v2: Add SKL support. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
* i965: Add all surface types to the batch decodeBen Widawsky2015-05-181-0/+6
| | | | | | | | | | | | | | | | | | | | | It's true that not all surfaces apply for every gen, but for the most part this is what we want. (The unfortunate case is when we use a valid surface, but not for the specific GEN). This was automated with a vim macro. v2: Shortened common forms such as R8G8B8A8->RGBA8. Note that this makes some of the sample output in subsequent commits slightly incorrect. v3: Use the name from the table (Ken). This requires declaring the surface format array as extern, and declaring the struct in the .h file. v4: Move the struct back and create a helper function to obtain the name (Ken) Get rid of the now useless helper in the state_dump.c Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> (v3) Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Add string for surface format to tableBen Widawsky2015-05-181-217/+219
| | | | | | | Recommended-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Change the order of conditions tested in ifAnuj Phogat2015-05-071-3/+4
| | | | | | | | Reduces the number of conditions tested in if to one in case of non-integer formats. Makes no functional changes. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
* i965: Render R16G16B16X16 as R16G16B16A16Anuj Phogat2015-04-171-0/+6
| | | | | | | | | | This enables using _mesa_meta_pbo_TexSubImage() to upload data to R16G16B16X16 texture. Earlier it fell back to slower paths. Jenkins run shows no piglit regressions. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Refactor brw_is_hiz_depth_format()Chad Versace2015-04-131-19/+0
| | | | | | | | | | | | | | | | | | | | | Every caller of this function uses it to determine if the current miptree needs a hiz buffer to be allocated. Strangely, the function doesn't take a miptree argument. So, this function effectively decides if and when a miptree's hiz buffer gets allocated without inspecting the miptree itself. Luckily, the driver behaves correctly despite the brw_is_hiz_depth_format's quirk. I will soon make some changes to the miptree that will require inspecting the miptree to determine if it needs a hiz buffer. So this patch renames brw_is_hiz_depth_format -> intel_miptree_wants_hiz_buffer and gives it a miptree parameter. This patch shouldn't change any behavior. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Add the ability to render to I8/L8 and I16/L16 UNORM formats.Kenneth Graunke2015-04-071-0/+8
| | | | | | | | This allows those formats to work with the meta PBO upload path. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
* i965: Support MESA_FORMAT_R8G8B8X8_SRGB.Kenneth Graunke2015-01-041-1/+4
| | | | | | | | | | | | | | | | | | | | | Valve games use GL_SRGB8 textures. Instead of supporting that properly, we fell back to MESA_FORMAT_R8G8B8A8_SRGB (with an alpha channel), which meant that we had to use texture swizzling to override the alpha to 1.0 when sampling. This meant shader recompiles on Gen < 7.5 platforms. By supporting MESA_FORMAT_R8G8B8X8_SRGB, the hardware just returns 1.0 for us, so we can just use SWIZZLE_XYZW, and avoid any recompiles. All generations of hardware have supported the format for sampling and filtering; we can easily support rendering by using the R8G8B8A8_SRGB format and writing garbage to the X channel. (We do this already for the non-SRGB version of this format.) This removes all remaining shader recompiles in a time demo of "Counter Strike: Global Offensive" (32 -> 0) on Sandybridge. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87886 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
* i965: Re-enable Z16 on Gen8+.Kenneth Graunke2014-11-041-0/+7
| | | | | | | | | | | | | Improves performance in GLBenchmark 2.7 TRex by 3.88889% +/- 0.336383% (n=80) at 1280x720 on Broadwell GT3. Together with the previous patch, it improves performance by 5.42738% +/- 0.541971% (n=10) at 1920x1080. Note that without the PMA stall fix, this would instead decrease performance by 22%. v2: Update comment (noticed by Kristian Høgsberg). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
* mesa: Add MESA_FORMAT_{A8R8G8B8, X8R8G8B8, X8B8G8R8}_SRGB (v2)Richard Sandiford2014-09-171-0/+3
| | | | | | | | | | | | This means that each 8888 SRGB format has a reversed counterpart, which is necessary for handling big-endian mesa<->gallium mappings. v2: fix missing i965 additions. (Jason) fix 127->255 max alpha for SRGB formats. (Jason) v1: Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* mesa: Add MESA_FORMAT_A8L8_{SNORM,SRGB}Richard Sandiford2014-09-171-0/+2
| | | | | | | | | | | | | The associated UNORM format already existed. This means that each LnAn format has a reversed counterpart, which is necessary for handling big-endian mesa<->gallium mappings. [airlied: rebased onto current master] Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com> Reviewed-by: Brian Paul <brianp@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* i965: Enable the GL_ARB_texture_compression_bptc extensionNeil Roberts2014-08-121-0/+5
| | | | | | | Enables the BPTC extension on Gen>=7 and adds the necessary format mappings to get the right surface type value. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* i965: Use unreachable() instead of unconditional assert().Matt Turner2014-07-011-2/+1
| | | | Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* Remove the ATI_envmap_bumpmap extensionJason Ekstrand2014-06-301-1/+0
| | | | | | | | | | | As far as I can tell, the Intel mesa driver is the only driver in the world still supporting this legacy extension. If someone wants to do bump mapping, they can use shaders. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v1] Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2] Reviewed-by: Ian Romanick <idr@freedesktop.org> [v3]
* i965: Disable Z16 in all APIs.Kenneth Graunke2014-04-151-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We originally thought that GL 3.0 required GL_DEPTH_COMPONENT16 to map exactly to Z16. However, we misread the specification, thanks in part to LaTeX reordering the tables in the PDF. Page 180 of the GL 3.0 specification (glspec30.20080923.pdf) says: "[...] memory allocation per texture component is assigned by the GL to match the allocations listed in tables 3.16-3.18 as closely as possible. [...] Required Texture Formats [...] In addition, implementations are required to support the following sized internal formats. Requesting one of these internal formats for any texture type will allocate exactly the internal component sizes and types shown for that format in tables 3.16-3.17:" Notably, however, GL_DEPTH_COMPONENT16 does /not/ appear in table 3.16 or table 3.17. It appears in table 3.18, where the "exact" rule doesn't apply, and it falls back to the "closely as possible" rule. The confusing part is that the ordering of the tables in the PDF is: Table 3.16 (pages 182-184) Table 3.18 (bottom of page 184 to top of 185) Table 3.17 (page 185) Presumably, people saw table 3.16, then saw the table immediately following with DEPTH_COMPONENT* formats, and assumed it was 3.17. Based on a patch by Chia-I Wu, but without the driconf option to force Z16 to be used. It's not required, and there's apparently no benefit to actually using it. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chia-I Wu <olv@lunarg.com>
* i965: Update comments about Z16 being slow.Kenneth Graunke2014-04-151-7/+10
| | | | | | | | | | | | | | | We've learned a few things since we originally disabled Z16; this attempts to summarize the issue. I am no expert on this subject, though, so the comment may not be totally accurate. I did some benchmarking on GM45 and Ironlake, and discovered that for GLBenchmark 2.7 EgyptHD, using Z16 was 3% slower on GM45 (n=15), and 4.5% slower on Ironlake (n=95). So, we can drop the "on Ivybridge" aspect of the comment - it's always slower. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chia-I Wu <olv@lunarg.com>
* i965: Render R8G8B8X8 as R8G8B8A8Chris Forbes2014-04-101-0/+3
| | | | | | | | | The sampler can handle R8G8B8X8 (and substitute 1.0 for the fourth component) but we can't use it as a render target. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Eric Anholt <eric@anholt.net>
* i965: Pretend we don't support BRW_SURFACEFORMAT_R16G16B16_FLOAT for textures.Chris Forbes2014-04-101-1/+1
| | | | | | | | | | | | | | | | | | | None of the other 3-component 16bpc formats are directly supported, so they get promoted to XRGB equivalents. *Not* promoting RGB16F the same way makes texture views much more fiddly -- we don't want to have to do crazy copying behind the scenes. (with my other master + my experimental ARB_texture_view support) fixes the piglit test: `spec/ARB_texture_view/view compare 48bit formats` No regressions in gpu.tests on Haswell. V4: Don't alter the formats table -- just don't match it to a mesa_format. [Kenneth] Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Eric Anholt <eric@anholt.net>
* i965: Enable R10G10B10A2_UNORM formatChris Forbes2014-04-101-0/+1
| | | | | | | | | This is supported by all generations, and is required for memory layout consistency for texture_view. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Eric Anholt <eric@anholt.net>
* i965: Enable R8G8B8A8_UNORM_SRGB formatChris Forbes2014-04-101-0/+1
| | | | | | | | Now this is the preferred format for GL_SRGB8_ALPHA8. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Eric Anholt <eric@anholt.net>
* mesa: rename MESA_FORMAT_X8Z24_UNORM -> MESA_FORMAT_X8_UINT_Z24_UNORMBrian Paul2014-03-101-1/+1
| | | | | | | To follow the example of MESA_FORMAT_Z24_UNORM_X8_UINT. Reviewed-by: Michel Dänzer <michel@daenzer.net> Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: Implement ARB_stencil_texturing on Gen8+.Kenneth Graunke2014-03-041-1/+1
| | | | | | | | | | | | | | | | | | | | On earlier hardware, we had to implement math in the shader to translate Y-tiled or untiled coordinates to W-tiled coordinates (which is what BLORP does today in order to texture from stencil buffers). On Broadwell, we can simply state that it's W-tiled in SURFACE_STATE, and adjust the pitch. This is much easier. In the surface state code, I chose to handle the "should we sample depth or stencil?" question separately from the setup for sampling from stencil. This should make it work with the BindRenderbufferTexImage hook as well, and hopefully be reusable for GL_ARB_texture_stencil8 someday. v2: Update docs/GL3.txt (caught by Matt). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: Fix S8 and X8 reversal in brw_depthbuffer_format refactor.Kenneth Graunke2014-02-211-3/+3
| | | | | | | | | | | | | | In commit 09d9a8913e8c28fc4c1c60d7da85a2f093786894, I accidentally botched the X8 and S8 cases. (I wrote this patch before realizing that X8 and S8 had been swapped in the big MESA_FORMAT rename, and apparently didn't rebase it properly after fixing that...) Fixes regressions in 13 Piglit tests on Ironlake. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75291 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* i965: Pull format conversion logic out of brw_depthbuffer_format.Kenneth Graunke2014-02-191-0/+41
| | | | | | | | | | | | brw_depthbuffer_format is not very reusable at the moment, since it uses global state (ctx->DrawBuffer) to access a particular depth buffer. For HiZ on Broadwell, I need a function which simply converts the formats. However, at least one existing user of brw_depthbuffer_format really wants the existing interface. So, I've created a new function. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
* mesa: Fix MESA_FORMAT_Z24_UNORM_S8_UINT vs. X8_UINT mix-up.Kenneth Graunke2014-02-091-6/+6
| | | | | | | | | | | | | | | | | | | | In commit eeed49f5f290793870c60b5b635b977a732a1eb4, Mark accidentally renamed MESA_FORMAT_S8_Z24 to MESA_FORMAT_Z24_UNORM_X8_UINT and MESA_FORMAT_X8_Z24 to MESA_FORMAT_Z24_UNORM_S8_UINT, reversing their sense. The commit message was correct, but what sed commands actually got run didn't match that. This patch swaps the two enum names, reversing them. This should undo the damage, but might break things if people have manually fixed a few instances in the meantime... Mark's commit also failed to mention renames: s/MESA_FORMAT_ARGB2101010_UINT\b/MESA_FORMAT_B10G10R10A2_UINT/g s/MESA_FORMAT_ABGR2101010\b/MESA_FORMAT_R10G10B10A2_UNORM/g but those seem okay. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* mesa: Fix Type A _INT formats to MESA_FORMAT naming standardMark Mueller2014-01-271-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | Replace Type A _INT formats names with _SINT to match naming spec, and update type C formats as follows: s/MESA_FORMAT_R_INT8\b/MESA_FORMAT_R_SINT8/g s/MESA_FORMAT_R_INT16\b/MESA_FORMAT_R_SINT16/g s/MESA_FORMAT_R_INT32\b/MESA_FORMAT_R_SINT32/g s/MESA_FORMAT_RG_INT8\b/MESA_FORMAT_RG_SINT8/g s/MESA_FORMAT_RG_INT16\b/MESA_FORMAT_RG_SINT16/g s/MESA_FORMAT_RG_INT32\b/MESA_FORMAT_RG_SINT32/g s/MESA_FORMAT_RGB_INT8\b/MESA_FORMAT_RGB_SINT8/g s/MESA_FORMAT_RGB_INT16\b/MESA_FORMAT_RGB_SINT16/g s/MESA_FORMAT_RGB_INT32\b/MESA_FORMAT_RGB_SINT32/g s/MESA_FORMAT_RGBA_INT8\b/MESA_FORMAT_RGBA_SINT8/g s/MESA_FORMAT_RGBA_INT16\b/MESA_FORMAT_RGBA_SINT16/g s/MESA_FORMAT_RGBA_INT32\b/MESA_FORMAT_RGBA_SINT32/g s/\bMESA_FORMAT_RED_RGTC1\b/MESA_FORMAT_R_RGTC1_UNORM/g s/\bMESA_FORMAT_SIGNED_RED_RGTC1\b/MESA_FORMAT_R_RGTC1_SNORM/g s/\bMESA_FORMAT_RG_RGTC2\b/MESA_FORMAT_RG_RGTC2_UNORM/g s/\bMESA_FORMAT_SIGNED_RG_RGTC2\b/MESA_FORMAT_RG_RGTC2_SNORM/g s/\bMESA_FORMAT_L_LATC1\b/MESA_FORMAT_L_LATC1_UNORM/g s/\bMESA_FORMAT_SIGNED_L_LATC1\b/MESA_FORMAT_L_LATC1_SNORM/g s/\bMESA_FORMAT_LA_LATC2\b/MESA_FORMAT_LA_LATC2_UNORM/g s/\bMESA_FORMAT_SIGNED_LA_LATC2\b/MESA_FORMAT_LA_LATC2_SNORM/g
* mesa: Fix MESA_FORMAT names containg SIGNEDMark Mueller2014-01-271-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | Update comments. Replace format names containing SIGNED with SNORM appended w/decoration per the format name spec: s/MESA_FORMAT_SIGNED_R8\b/MESA_FORMAT_R_SNORM8/g s/MESA_FORMAT_SIGNED_RG88_REV\b/MESA_FORMAT_R8G8_SNORM/g s/MESA_FORMAT_SIGNED_RGBX8888\b/MESA_FORMAT_X8B8G8R8_SNORM/g s/MESA_FORMAT_SIGNED_RGBA8888\b/MESA_FORMAT_A8B8G8R8_SNORM/g s/MESA_FORMAT_SIGNED_RGBA8888_REV\b/MESA_FORMAT_R8G8B8A8_SNORM/g s/MESA_FORMAT_SIGNED_R16\b/MESA_FORMAT_R_SNORM16/g s/MESA_FORMAT_SIGNED_GR1616\b/MESA_FORMAT_R16G16_SNORM/g s/MESA_FORMAT_SIGNED_RGB_16\b/MESA_FORMAT_RGB_SNORM16/g s/MESA_FORMAT_SIGNED_RGBA_16\b/MESA_FORMAT_RGBA_SNORM16/g s/MESA_FORMAT_SIGNED_A8\b/MESA_FORMAT_A_SNORM8/g s/MESA_FORMAT_SIGNED_I8\b/MESA_FORMAT_I_SNORM8/g s/MESA_FORMAT_SIGNED_L8\b/MESA_FORMAT_L_SNORM8/g s/MESA_FORMAT_SIGNED_A16\b/MESA_FORMAT_A_SNORM16/g s/MESA_FORMAT_SIGNED_I16\b/MESA_FORMAT_I_SNORM16/g s/MESA_FORMAT_SIGNED_L16\b/MESA_FORMAT_L_SNORM16/g s/MESA_FORMAT_SIGNED_AL88\b/MESA_FORMAT_L8A8_SNORM/g s/MESA_FORMAT_SIGNED_RG88\b/MESA_FORMAT_G8R8_SNORM/g s/MESA_FORMAT_SIGNED_RG1616\b/MESA_FORMAT_G16R16_SNORM/g
* mesa: Fix MESA_FORMAT names with ALPH, INTENSITY, and LUMINANCEMark Mueller2014-01-271-35/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Compressed spelled out color components ALPHA, INTENSITY, and LUMINANCE to A, I, and L: s/MESA_FORMAT_ALPHA_UINT8\b/MESA_FORMAT_A_UINT8/g' s/MESA_FORMAT_ALPHA_UINT16\b/MESA_FORMAT_A_UINT16/g' s/MESA_FORMAT_ALPHA_UINT32\b/MESA_FORMAT_A_UINT32/g' s/MESA_FORMAT_ALPHA_INT32\b/MESA_FORMAT_A_SINT32/g' s/MESA_FORMAT_ALPHA_INT16\b/MESA_FORMAT_A_SINT16/g' s/MESA_FORMAT_ALPHA_INT8\b/MESA_FORMAT_A_SINT8/g' s/MESA_FORMAT_INTENSITY_UINT8\b/MESA_FORMAT_I_UINT8/g' s/MESA_FORMAT_INTENSITY_UINT16\b/MESA_FORMAT_I_UINT16/g' s/MESA_FORMAT_INTENSITY_UINT32\b/MESA_FORMAT_I_UINT32/g' s/MESA_FORMAT_INTENSITY_INT32\b/MESA_FORMAT_I_SINT32/g' s/MESA_FORMAT_INTENSITY_INT16\b/MESA_FORMAT_I_SINT16/g' s/MESA_FORMAT_INTENSITY_INT8\b/MESA_FORMAT_I_SINT8/g' s/MESA_FORMAT_LUMINANCE_UINT8\b/MESA_FORMAT_L_UINT8/g' s/MESA_FORMAT_LUMINANCE_UINT16\b/MESA_FORMAT_L_UINT16/g' s/MESA_FORMAT_LUMINANCE_UINT32\b/MESA_FORMAT_L_UINT32/g' s/MESA_FORMAT_LUMINANCE_INT32\b/MESA_FORMAT_L_SINT32/g' s/MESA_FORMAT_LUMINANCE_INT16\b/MESA_FORMAT_L_SINT16/g' s/MESA_FORMAT_LUMINANCE_INT8\b/MESA_FORMAT_L_SINT8/g' s/MESA_FORMAT_LUMINANCE_ALPHA_UINT8\b/MESA_FORMAT_LA_UINT8/g' s/MESA_FORMAT_LUMINANCE_ALPHA_UINT16\b/MESA_FORMAT_LA_UINT16/g' s/MESA_FORMAT_LUMINANCE_ALPHA_UINT32\b/MESA_FORMAT_LA_UINT32/g' s/MESA_FORMAT_LUMINANCE_ALPHA_INT32\b/MESA_FORMAT_LA_SINT32/g' s/MESA_FORMAT_LUMINANCE_ALPHA_INT16\b/MESA_FORMAT_LA_SINT16/g' s/MESA_FORMAT_LUMINANCE_ALPHA_INT8\b/MESA_FORMAT_LA_SINT8/g' s/MESA_FORMAT_ALPHA_FLOAT16\b/MESA_FORMAT_A_FLOAT16/g' s/MESA_FORMAT_ALPHA_FLOAT32\b/MESA_FORMAT_A_FLOAT32/g' s/MESA_FORMAT_INTESITY_FLOAT16\b/MESA_FORMAT_I_FLOAT16/g' s/MESA_FORMAT_INTESITY_FLOAT32\b/MESA_FORMAT_I_FLOAT32/g' s/MESA_FORMAT_INTENSITY_FLOAT16\b/MESA_FORMAT_I_FLOAT16/g' s/MESA_FORMAT_INTENSITY_FLOAT32\b/MESA_FORMAT_I_FLOAT32/g' s/MESA_FORMAT_LUMINANCE_FLOAT16\b/MESA_FORMAT_L_FLOAT16/g' s/MESA_FORMAT_LUMINANCE_FLOAT32\b/MESA_FORMAT_L_FLOAT32/g' s/MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16\b/MESA_FORMAT_LA_FLOAT16/g' s/MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32\b/MESA_FORMAT_LA_FLOAT32/g'
generated by cgit v1.1 at 2024-06-12 15:17:47 +0000