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* i965: Assert that a depth_mt exists when using HiZ.Matt Turner2016-05-251-0/+1
| | | | | Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
* i965/gen6: Set up layer constraints properly for depth buffers.Kenneth Graunke2015-07-101-1/+5
| | | | | | | | | | This ports over Chris Forbes' equivalent fixes in gen7_misc_state.c from commit 77d55ef4819436ebbf9786a1e720ec00707bbb19. No Piglit changes on Sandybridge. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Rename intel_emit* to reflect their new location in brw_pipe_controlChris Wilson2015-06-241-1/+1
| | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/hiz: Start to separate miptree out from hiz buffersJordan Justen2015-03-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Today we allocate a miptree's for the hiz buffer. We needed this in the past because we would point the hardware at offsets of the hiz buffer. Since the hiz format is not documented, this is not a good idea. Since moving to support layered rendering on Gen7+, we no longer point at an offset into the buffer on Gen7+. Therefore, to support hiz on Gen7+, we don't need a full miptree structure allocated. This patch starts to create a new auxiliary buffer structure (intel_miptree_aux_buffer) that can be a more simplistic miptree side-band buffer associated with a miptree. (For example, to serve the needs of the hiz buffer.) Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
* i965: Do Sandybridge workaround flushes before each primitive.Kenneth Graunke2015-02-171-7/+0
| | | | | | | | | | | | | | | | | | | | | | | Sandybridge requires the post-sync non-zero workaround in a ton of places, and if you ever miss one, the GPU usually hangs. Currently, we try to track exactly when a workaround flush is necessary (via the brw->batch.need_workaround_flush flag). This is tricky to get right, and we've botched it several times in the past. This patch unconditionally performs the post-sync non-zero flush at the start of each primitive's state upload (including BLORP). We drop the needs_workaround_flush flag, and drop all the other callers, as the flush has already been performed. We have no data to indicate that simply flushing all the time will hurt performance, and it has the potential to help stability. v2: Add post-sync workaround to initial GPU state upload to be extra cautious (suggested by Chad Versace). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
* i965/gen6: Stencil/hiz needs an offset for LOD > 0Jordan Justen2014-08-151-2/+32
| | | | | | | | | | | | Since gen6 separate stencil & hiz only supports LOD0, we need to program an offset to the LOD when emitting the separate stencil/hiz. v3: * Use new array_layout enum Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/gen6 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surfaceJordan Justen2014-08-151-8/+27
| | | | | | | | | | | | | | | | | | | | | | (bf25ee2 for gen6) Previously we would always find the 2D sub-surface of interest, and then program the surface to this location. Now we always program the 3DSTATE_DEPTH_BUFFER at the start of the surface. To select the lod/slice, we utilize the lod & minimum array element fields. We also must disable brw_workaround_depthstencil_alignment for gen >= 6. Now the hardware will handle alignment when rendering to additional slices/LODs. v3: * Set depth_mt bo RELOC offset to 0, as was done in bf25ee2 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56127 Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/gen6 depth surface: calculate minimum array element being renderedJordan Justen2014-08-151-0/+2
| | | | | | | | | | | (a23cfb8 for gen6) In layered rendering this will be 0. Otherwise it will be the selected slice. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/gen6 depth surface: calculate LOD being rendered toJordan Justen2014-08-151-0/+3
| | | | | | | | | | (08ef1dd for gen6) This will be used in 3DSTATE_DEPTH_BUFFER in a later patch. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/gen6 depth surface: calculate depth (array size) for depth surfaceJordan Justen2014-08-151-0/+3
| | | | | | | | | | | | | (bc1acaa for gen6) This will be used in 3DSTATE_DEPTH_BUFFER in a later patch. Note: Cube maps are treated as 2D arrays with 6 times as many array elements as the cube map array would have. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/gen6 depth surface: calculate more specific surface typeJordan Justen2014-08-151-0/+33
| | | | | | | | | | | | | (171e633 for gen6) This will be used in 3DSTATE_DEPTH_BUFFER in a later patch. Note: Cube maps are treated as 2D arrays with 6 times as many array elements as the cube map array would have. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/gen6_depth_state.c: Remove (gen != 6) code pathsJordan Justen2014-08-151-31/+14
| | | | | | | | | Since this code was branched from brw_misc_state.c, it had support for gen != 6. We can now remove this. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Split gen6 depth hiz state out from brwJordan Justen2014-08-151-0/+176
We will program the gen6 hiz depth state differently to enable layered rendering on gen6. v2: * Remove unneeded gen6_emit_depthbuffer as suggested by Topi Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>