external_mesa3d.git - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Expand)	Author	Age	Files	Lines
*	i965: Track that the stencil data was updated when rendering	Jordan Justen	2016-08-26	1	-0/+1
*	i965: Assert that a depth_mt exists when using HiZ.	Matt Turner	2016-05-25	1	-0/+1
*	i965: Make all atoms to track BRW_NEW_BLORP by default	Kenneth Graunke	2016-04-23	1	-1/+2
*	i965: Rename intel_emit* to reflect their new location in brw_pipe_control	Chris Wilson	2015-06-24	1	-1/+1
*	i965/gen7: Don't rely directly on the hiz miptree structure	Jordan Justen	2015-03-09	1	-3/+4
*	i965/hiz: Start to separate miptree out from hiz buffers	Jordan Justen	2015-03-09	1	-1/+1
*	i965: Delete brw_state_flags::cache and related code.	Kenneth Graunke	2014-12-02	1	-1/+0
*	i965: Alphabetize brw_tracked_state flags and use a consistent style.	Kenneth Graunke	2014-11-29	1	-1/+3
*	i965/gen7 depth: Set depth size based on LOD0 for 3D textures	Jordan Justen	2014-05-13	1	-2/+2
*	i965/Gen7: Set up layer constraints properly for depth buffers	Chris Forbes	2014-05-09	1	-9/+6
*	i965: Delete the intel_regions.c code.	Eric Anholt	2014-05-01	1	-1/+0
*	i965: Drop use of intel_region from miptrees.	Eric Anholt	2014-05-01	1	-6/+6
*	i965/gen7: Skip repeated NULL depth/stencil state emits.	Eric Anholt	2014-04-11	1	-0/+8
*	i965: Fix clears of layered framebuffers with mismatched layer counts.	Paul Berry	2014-01-10	1	-1/+1
*	mesa: Track number of layers in layered framebuffers.	Paul Berry	2013-11-21	1	-1/+1
*	gen7: Use logical, not physical, dims in 3DSTATE_DEPTH_BUFFER (v2)	Chad Versace	2013-10-07	1	-2/+2
*	i965/gen7: Set MOCS L3 cacheability for IVB/BYT (v2)	Ville Syrjälä	2013-08-21	1	-1/+1
*	gen7 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surface	Jordan Justen	2013-08-04	1	-8/+28
*	gen7 depth surface: calculate minimum array element being rendered	Jordan Justen	2013-08-04	1	-0/+10
*	gen7 depth surface: calculate LOD being rendered to	Jordan Justen	2013-08-04	1	-0/+3
*	gen7 depth surface: calculate depth (array size) for depth surface	Jordan Justen	2013-08-04	1	-0/+3
*	gen7 depth surface: calculate more specific surface type	Jordan Justen	2013-08-04	1	-0/+31
*	i965/hsw: Change L3 MOCS for depth, hiz, and stencil	Chad Versace	2013-07-18	1	-2/+5
*	i965: Cite the Sandybridge PRM for Gen7 stencil pitch requirements.	Kenneth Graunke	2013-07-15	1	-9/+5
*	i965: Delete intel_context entirely.	Kenneth Graunke	2013-07-09	1	-2/+1
*	i965: Move intel_context::is_<platform> flags to brw_context.	Kenneth Graunke	2013-07-09	1	-1/+1
*	i965: Pass brw_context to functions rather than intel_context.	Kenneth Graunke	2013-07-09	1	-1/+1
*	i965: Remove _NEW_DEPTH state flagging on drawbuffers change.	Eric Anholt	2013-06-25	1	-1/+1
*	intel: Replace checks for hiz_mt with intel_has*hiz()	Chad Versace	2013-04-10	1	-5/+6
*	i965: Fix stencil write enable flag in 3DSTATE_DEPTH_BUFFER on Gen7+.	Kenneth Graunke	2013-04-04	1	-1/+1
*	i965: Reduce code duplication in handling of depth, stencil, and HiZ.	Paul Berry	2013-04-02	1	-62/+31
*	intel: Make intel_region's pitch be bytes instead of pixels.	Eric Anholt	2013-01-18	1	-3/+3
*	i965: Move all the depth/stencil/hiz offset logic into the workaround.	Eric Anholt	2012-11-19	1	-79/+11
*	i965: Fix rendering to small mipmaps of depth/stencil buffers using a temp mt.	Eric Anholt	2012-10-16	1	-60/+40
*	i965: Share the draw x/y offset masking code between main/blorp and all gens.	Eric Anholt	2012-10-16	1	-36/+5
*	intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset.	Paul Berry	2012-09-12	1	-2/+4
*	intel: Add map_stencil_as_y_tiled to intel_region_get_tile_masks.	Paul Berry	2012-09-12	1	-2/+3
*	i965/gen6+: Add support for fast depth clears.	Eric Anholt	2012-05-23	1	-2/+2
*	i965/gen7: Set tile_x/y to 0 in the no-stencil case.	Eric Anholt	2012-05-14	1	-1/+1
*	i965/Gen7: Work around GPU hangs due to misaligned depth coordinate offsets.	Paul Berry	2012-05-07	1	-0/+36
*	i965: Fix mipmap offsets for HiZ and separate stencil buffers.	Paul Berry	2012-05-07	1	-7/+72
*	i965: Stop lying about cpp and height of a stencil buffer.	Paul Berry	2012-04-10	1	-1/+15
*	i965: Set "Stencil Buffer Enable" bit on Haswell.	Kenneth Graunke	2012-03-30	1	-1/+4
*	intel: derive intel_renderbuffer from swrast_renderbuffer	Brian Paul	2012-01-24	1	-4/+4
*	i965/gen7: Fix depth buffer rendering to tile offsets.	Eric Anholt	2012-01-12	1	-2/+2
*	i965: Fix compiler warnings from hiz changes.	Eric Anholt	2012-01-10	1	-2/+0
*	i965/gen7: Fix batch length for 3DSTATE_HIER_DEPTH_BUFFER	Chad Versace	2012-01-10	1	-2/+2
*	i965/gen7: Enable HiZ	Chad Versace	2012-01-10	1	-8/+23
*	i965: Replace references to stencil region size with buffer size	Chad Versace	2012-01-10	1	-2/+4
*	i965: Properly demote the depth mt format for fake packed depth/stencil.	Eric Anholt	2011-12-19	1	-0/+1