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* i965/fs: Add unit tests for copy propagation pass.Matt Turner2016-12-242-0/+211
| | | | | | | | | Pretty basic, but it's a start. Acked-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 091a8a04adb28a2044e3baadba0af52a185b3bd0) [Emil Velikov: nir_shader_create() has only three arguments] Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
* i965/fs: Rename opt_copy_propagate -> opt_copy_propagation.Matt Turner2016-12-163-15/+16
| | | | | | | Matches the vec4 backend, cmod propagation, and saturate propagation. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 6014da50ec41d1ad43fec94a625962ac3f2f10cb)
* i965/mt: Disable aux surfaces after making miptree shareableChad Versace2016-12-141-0/+2
| | | | | | | | | | | | | | | The entire goal of intel_miptree_make_shareable() is to permanently disable the miptree's aux surfaces. So set intel_mipmap_tree:disable_aux_buffers after the function's done with discarding down the aux surfaces. References: https://bugs.freedesktop.org/show_bug.cgi?id=98329 Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: Nanley Chery <nanley.g.chery@intel.com Cc: Haixia Shi <hshi@chromium.org> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 1c8be049bea786c2c054a770025976beba5b8636)
* i965: Allocate at least some URB space even when max_vertices = 0.Kenneth Graunke2016-12-141-1/+7
| | | | | | | | | | | | | | | | | | | | | Allocating zero URB space is a really bad idea. The hardware has to give threads a handle to their URB space, and threads have to use that to terminate the thread. Having it be an empty region just breaks a lot of assumptions. Hence, why we asserted that it isn't possible. Unfortunately, it /is/ possible prior to Gen8, if max_vertices = 0. In theory a geometry shader could do SSBO/image access and maybe still accomplish something. In reality, this is tripped up by conformance tests. Gen8+ already avoids this problem by placing the vertex count DWord in the URB entry header. This fixes things on earlier generations. Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Tested-by: Ian Romanick <ian.d.romanick@intel.com> (cherry picked from commit a41f5dcb141a11ca5ca0c765c305027b0f0b609e)
* i965/hsw: Set integer mode in sampling state for stencil texturingJordan Justen2016-11-242-18/+9
| | | | | | | | | | | | | | | | Fixes: ES31-CTS.functional.texture.border_clamp.formats.depth24_stencil8_sample_stencil.nearest_size_pot ES31-CTS.functional.texture.border_clamp.formats.depth24_stencil8_sample_stencil.nearest_size_npot ES31-CTS.functional.texture.border_clamp.formats.depth32f_stencil8_sample_stencil.nearest_size_pot ES31-CTS.functional.texture.border_clamp.formats.depth32f_stencil8_sample_stencil.nearest_size_npot ES31-CTS.functional.texture.border_clamp.unused_channels.depth24_stencil8_sample_stencil ES31-CTS.functional.texture.border_clamp.unused_channels.depth32f_stencil8_sample_stencil Cc: "13.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit 44c5ed02d1b173c061c3188e245d384fd4c0abba)
* i965: Fix GS push inputs with enhanced layouts.Kenneth Graunke2016-11-241-1/+1
| | | | | | | | | | | | | We weren't taking first_component into account when handling GS push inputs. We hardly ever push GS inputs, so this was not caught by existing tests. When I started using component qualifiers for the gl_ClipDistance arrays, glsl-1.50-transform-feedback-type-and-size started catching this. Cc: "13.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit c4be6e0b8d91746eccf334b9e20861af4036d06a)
* i965: Fix compute shader crash.Kenneth Graunke2016-11-241-1/+1
| | | | | | | | | Fixes crashes when starting Deus Ex: Mankind Divided. Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> (cherry picked from commit ca76e6b5213c92432b9f3a641cb26f5861d53e09)
* i965/gs: Allow primitive id to be a system valueJason Ekstrand2016-11-241-1/+2
| | | | | | | | | | | | | | | This allows for gl_PrimitiveId to come in as a system value rather than as an input. This is the way it will come in from SPIR-V. We keeps the input path working for now so we don't break GL. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: "13.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit a5e88e66e633aaeb587b274d80e21cd46c8ee2cb) [Emil Velikov: nir_shader::info is not a pointer in branch] Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Conflicts: src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
* i965: Fix GPU hang related to multiple render targets and alpha testingAnuj Phogat2016-11-091-0/+6
| | | | | | | | | | | | | | | | | | | | This patch should have been the part of commit e592f7df. In a situation when there are multiple render targets with alpha testing enabled, if fragment shader doesn't write to draw buffer zero, it causes the GPU hang on SKL. No GPU hang is seen on HSW. Simulator gives a warning for all gen6+ h/w: "Illegal render target write message length 0xa expected 0xc" This patch fixes the GPU hang as well as the simulator warning with new piglit test fbo-mrt-alphatest-no-buffer-zero-write: https://patchwork.freedesktop.org/patch/118212 No regressions in Jenkins CI system. Cc: "12.0 13.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> (cherry picked from commit b9df2251c17e3ce52fa55c81f492591e08c3ee04)
* intel/blorp: Pass a brw_stage_prog_data to upload_shaderJason Ekstrand2016-11-091-1/+2
| | | | | | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98012 Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com> Cc: "13.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 4306c10a885bdd833328a2a4eeb0079aa4f4bae3)
* i965/fs/generator: Don't use the address immediate for MOV_INDIRECTJason Ekstrand2016-11-011-28/+27
| | | | | | | | | | | | | | The address immediate field is only 9 bits and, since the value is in bytes, the highest GRF we can point to with it is g15. This makes it pretty close to useless for MOV_INDIRECT. There were already piles of restrictions preventing us from using it prior to Broadwell, so let's get rid of the gen8+ code path entirely. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97779 Cc: "12.0 13.0" <mesa-stable@lists.freedesktop.org> Reviewed-by: Matt Turner <mattst88@gmail.com> (cherry picked from commit 2a4a86862c949055c71637429f6d5f2e725d07d8)
* i965: Drop nir_inputs from fs_visitor.Kenneth Graunke2016-10-271-1/+0
| | | | | | | | | It's unused. Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com> (cherry picked from commit 41034abfe63012784c9e9e36856d878928cecd99)
* i965: Don't use nir_assign_var_locations for VS/TES/GS outputs.Kenneth Graunke2016-10-275-62/+12
| | | | | | | | | | | | Fixes spec/arb_enhanced_layouts/execution/component-layout/vs-fs-array-dvec3. v2: Remove nir_outputs field from fs_visitor (caught by Tim and Iago). Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com> (cherry picked from commit 59864e8e02057cc6fa0448a8af067a3cf53389da)
* i965: Make split_virtual_grfs() call compact_virtual_grfs().Kenneth Graunke2016-10-271-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | Post-splitting, VGRFs have a maximum size (MAX_VGRF_SIZE). This is required by the register allocator, as we have to create classes for each size of VGRF. We can (and do) allocate virtual registers larger than MAX_VGRF_SIZE, but we must ensure that they are splittable. split_virtual_grfs() asserts that the post-splitting register size is in range. Unfortunately, these trip for completely dead registers which are too large - we only set split points for live registers. So dead ones are never split, and if they happened to be too large, they'd trip asserts. To fix this, call compact_virtual_grfs() to eliminate dead registers before splitting. v2: Add a comment written by Iago. Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com> (cherry picked from commit 27715c73ff84349466f62df0023863acd477f262)
* i965: Drop unnecessary switch statement in nir_setup_outputs()Kenneth Graunke2016-10-271-12/+3
| | | | | | | | | | | TCS and FS are skipped above. CS has no output variables. All remaining cases take the same path. Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com> (cherry picked from commit 3728ee000aecb19793dec56d45aff9d6cfce3e5b)
* mesa: remove gl_shader_compiler_options::EmitNoNoiseMarek Olšák2016-10-192-2/+0
| | | | | | | it's always true Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* i965: fix subnr overflow in suboffset()Iago Toral Quiroga2016-10-191-8/+5
| | | | Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* i965: Fix gl_InvocationID in dual object GS where invocations == 1.Kenneth Graunke2016-10-171-1/+4
| | | | | | | | | | | | | | | | | | | | dEQP-GLES31.functional.geometry_shading.instanced.geometry_1_invocations draws using a geometry shader that specifies layout(points, invocations = 1) in; and then uses gl_InvocationID. According to the Haswell PRM, the "GS Instance ID 0" (and 1) thread payload fields are undefined in dual object mode: "If 'dispatch mode' is DUAL_OBJECT this field is not valid." But there's no point in using them - if there's only one invocation, the ID will be 0. So just load a constant. Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
* i965: Silence unused parameter warningsIan Romanick2016-10-177-9/+5
| | | | | | | | | | | | | | | | | | | | brw_link.cpp:76:44: warning: unused parameter ‘shader_type’ [-Wunused-parameter] gl_shader_stage shader_type, ^ brw_nir.c: In function ‘brw_nir_lower_vs_inputs’: brw_nir.c:194:55: warning: unused parameter ‘devinfo’ [-Wunused-parameter] const struct gen_device_info *devinfo, ^ brw_vec4_visitor.cpp:914:37: warning: unused parameter ‘sampler’ [-Wunused-parameter] uint32_t sampler, ^ brw_vec4_visitor.cpp:1146:34: warning: unused parameter ‘stream_id’ [-Wunused-parameter] vec4_visitor::gs_emit_vertex(int stream_id) ^ Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Engestrom <eric@engestrom.ch>
* i965: Enable OpenGL 4.5.Kenneth Graunke2016-10-142-2/+2
| | | | | | | | | Everything is in place. There are still conformance issues to sort out, but we may as well turn it on in master. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Acked-by: Jason Ekstrand <jason@jlekstrand.net>
* intel/blorp: Add a flag to make blorp not re-emit dept/stencil buffersJason Ekstrand2016-10-141-6/+6
| | | | | | | | | | | In Vulkan, we want to be able to use blorp to perform clears inside of a render pass. If blorp stomps the depth/stencil buffers packets then we'll have to re-emit them. This gets tricky when secondary command buffers get involved. Instead, we'll simply guarantee that the depth and stencil buffers we pass to blorp (if any) match those already set in the hardware. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i915: workaround multiple intelFenceExtension definitionsEmil Velikov2016-10-141-0/+1
| | | | | | | | | | | | | Due to conflicting symbol names (between i915 and i965) in the megadriver, we use a set of defines in i915/intel_screen.h. With a recent commit we've introduced a symbol intelFenceExtension which has different implementation for each driver, yet we forgot to add the define. Fixes: d11515ff1b3 ("i915/sync: Implement DRI2_Fence extension") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98264 Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
* i965: Sort some extension namesIan Romanick2016-10-141-3/+3
| | | | | | | Trivial. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
* i915: store reference to the context within struct intel_fence (v2)Mauro Rossi2016-10-141-11/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Porting of the corresponding patch for i965. Here follows the original commit message by Tomasz Figa: "As the spec allows for {server,client}_wait_sync to be called without currently bound context, while our implementation requires context pointer. v2: Add a mutex and acquire it for the duration of brw_fence_client_wait() and brw_fence_is_completed() as suggested by Chad." NOTE: in i915 all references to 'brw' are replaced by 'intel' Marshmallow-x86 boots ok with the following results of Android CTS. Android CTS 6.0_r7 build:2906653 Session Pass Fail Not Executed 0(EGL) 1410 24 0 1(GLES2) 13832 82 0 I get the same results as per i965GM. [Emil Velikov: Include Mauro's test results] Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
* i915/sync: Implement DRI2_Fence extensionMauro Rossi2016-10-143-30/+152
| | | | | | | | | | | Here is the porting of corresponding patch for i965, i.e. commit c636284 i965/sync: Implement DRI2_Fence extension Here follows part of original commit message by Chad Versace: "This enables EGL_KHR_fence_sync and EGL_KHR_wait_sync." Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
* i915/sync: Replace prefix 'intel_sync' -> 'intel_gl_sync'Mauro Rossi2016-10-142-26/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | This is the porting of corresponding patch for i965, i.e. commit 2516d83 i965/sync: Replace prefix 'intel_sync' -> 'intel_gl_sync' The only difference compared to i965 one is that intel_check_sync() was renamed to intel_gl_check_sync() here, as it is more appropriate. Here follows original commit message by Chad Versace: "I'm about to implement DRI2_Fenc in intel_syncobj.c. To prevent madness, we need to prefix functions for GL_ARB_sync with 'gl' and functions for DRI2_Fence with 'dri'. Otherwise, the file will become a jumble of similiarly named functions. For example: old-name: intel_client_wait_sync() new-name: intel_gl_client_wait_sync() soon-to-come: intel_dri_client_wait_sync() I wrote this renaming commit separately from the commit that implements DRI2_Fence because I wanted the latter diff to be reviewable." [Emil Velikov: rename the outstanding intel_sync instances] Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
* mesa: replace gl_framebuffer::_IntegerColor wih _IntegerBuffersBrian Paul2016-10-131-1/+1
| | | | | | | | | | | Use a bitmask to indicate which color buffers are integer-valued, rather than a bool. Also, the old field was mis-computed. If an integer buffer was followed by a non-integer buffer, the _IntegerColor field was wrongly set to false. This fixes the new piglit gl-3.1-mixed-int-float-fbo test. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* mesa: remove 'params' parameter from ctx->Driver.TexParameter()Brian Paul2016-10-133-6/+5
| | | | | | | | | | | None of the drivers which implement this hook do anything with the texture parameter value. Drivers just look at the pname and set a dirty flag if needed. We were doing some ugly casting and type conversion to setup the argument so that all goes away. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* i965: solve cubemap negative x/y/z faces buffer offset issue in dEQP.Xu,Randy2016-10-111-1/+3
| | | | | | | | | | | | | | Add the miptree level/slice x/y_offset when count the surface offset in brw_emit_surface_state. The surface offset has two parts, one is from mt->offset, which should be 32 aligned in width/height for tiled buffer; another is from mt->level[current_level].slice[current_slice]. x/y_offset. This fix will solve 12 deqp failure dEQP-EGL.functional.image.create.gles2_cubemap_negative_*_texture Signed-off-by: Xu,Randy <randy.xu@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* i965: remove remaining tabs in brw_draw.cTimothy Arceri2016-10-061-13/+13
| | | | Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: get inputs read from nir infoTimothy Arceri2016-10-0610-20/+39
| | | | | | | | | | This is a step towards dropping the GLSL IR version of do_set_program_inouts() in i965 and moving towards native nir support. This is important because we want to eventually convert to nir and use its optimisations passes before we can call this GLSL IR pass. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: get outputs written from nir infoTimothy Arceri2016-10-066-22/+34
| | | | | | | | | | This is a step towards dropping the GLSL IR version of do_set_program_inouts() in i965 and moving towards native nir support. This is important because we want to eventually convert to nir and use its optimisations passes before we can call this GLSL IR pass. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: get outputs read from nir infoTimothy Arceri2016-10-062-2/+3
| | | | | | | | | | This is a step towards dropping the GLSL IR version of do_set_program_inouts() in i965 and moving towards native nir support. This is important because we want to eventually convert to nir and use its optimisations passes before we can call this GLSL IR pass. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: remove remaining tabs in brw_wm.cTimothy Arceri2016-10-061-44/+44
| | | | Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: get uses discard from nir infoTimothy Arceri2016-10-061-2/+4
| | | | | | | | | | This is a step towards dropping the GLSL IR version of do_set_program_inouts() in i965 and moving towards native nir support. This is important because we want to eventually convert to nir and use its optimisations passes before we can call this GLSL IR pass. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: get uses texture gather from nir infoTimothy Arceri2016-10-063-9/+11
| | | | | | | | | | This is a step towards dropping the GLSL IR version of do_set_program_inouts() in i965 and moving towards native nir support. This is important because we want to eventually convert to nir and use its optimisations passes before we can call this GLSL IR pass. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Eliminate brw->cs.prog_data pointer.Kenneth Graunke2016-10-056-17/+18
| | | | | | | | | | | | Just say no to: - brw->cs.base.prog_data = &brw->cs.prog_data->base.base; We'll just use the brw_stage_prog_data pointer in brw_stage_state and downcast it to brw_cs_prog_data as needed. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
* i965: Eliminate brw->wm.prog_data pointer.Kenneth Graunke2016-10-0514-50/+68
| | | | | | | | | | | | Just say no to: - brw->wm.base.prog_data = &brw->wm.prog_data->base.base; We'll just use the brw_stage_prog_data pointer in brw_stage_state and downcast it to brw_wm_prog_data as needed. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
* i965: Eliminate brw->gs.prog_data pointer.Kenneth Graunke2016-10-0510-59/+73
| | | | | | | | | | | | Just say no to: - brw->gs.base.prog_data = &brw->gs.prog_data->base.base; We'll just use the brw_stage_prog_data pointer in brw_stage_state and downcast it to brw_gs_prog_data as needed. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
* i965: Eliminate brw->tes.prog_data pointer.Kenneth Graunke2016-10-0510-25/+29
| | | | | | | | | | | | Just say no to: - brw->tes.base.prog_data = &brw->tes.prog_data->base.base; We'll just use the brw_stage_prog_data pointer in brw_stage_state and downcast it to brw_tes_prog_data as needed. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
* i965: Eliminate brw->tcs.prog_data pointer.Kenneth Graunke2016-10-058-25/+28
| | | | | | | | | | | | Just say no to: - brw->tcs.base.prog_data = &brw->tcs.prog_data->base.base; We'll just use the brw_stage_prog_data pointer in brw_stage_state and downcast it to brw_tcs_prog_data as needed. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
* i965: Eliminate brw->vs.prog_data pointer.Kenneth Graunke2016-10-0518-96/+121
| | | | | | | | | | | | Just say no to: - brw->vs.base.prog_data = &brw->vs.prog_data->base.base; We'll just use the brw_stage_prog_data pointer in brw_stage_state and downcast it to brw_vs_prog_data as needed. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
* i965: Introduce downcast helpers for prog_data structures.Kenneth Graunke2016-10-057-62/+66
| | | | | | | Similar to brw_context(...), intel_texture_object(...), and so on. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
* i965/sync: Rename awkward variableChad Versace2016-10-051-6/+6
| | | | | | | | | | What is the difference between a 'driver_fence' and a 'fence'? Do the characters 'driver_' add anything helpful? Nope. They do, though, add an extra 7 chars and pull your eyeballs away to ask "huh? what's that?" one microsecond too many. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/sync: Rename intel_syncobj.c -> brw_sync.cChad Versace2016-10-053-2/+2
| | | | | Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/sync: Replace 'intel' prefix with 'brw'Chad Versace2016-10-053-37/+37
| | | | | | | This is yet another patch for the great renaming begun long ago. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/sync: Fix uninitalized usage and leak of mutexChad Versace2016-10-051-2/+12
| | | | | | | | | | | | | | | | | We locked an unitialized mutex in the callstack glClientWaitSync intel_gl_client_wait_sync brw_fence_client_wait_sync because we forgot to initialize it in intel_gl_fence_sync. (The EGLSync codepath didn't have this bug. It initialized the mutex in intel_dri_create_sync). We also forgot to tear down (mtx_destroy) the mutex when destroying the sync object. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: use L3 data cache for SSBOsLionel Landwerlin2016-10-051-1/+2
| | | | | | | | | | | | | Anv programs the hardware to use L3 data cache if we use either SSBOs or images in the shaders, we can program i965 the same way. gl_shader_program has a bit of a confusing named field with 'NumAtomicBuffers'. It doesn't tell how many buffers are accessed by the shader in an atomic way but instead the number of atomic counters manipulated by the shader. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
* i965: Drop _NEW_TRANSFORM from 3DSTATE_VS atom on Gen7.Kenneth Graunke2016-10-041-1/+1
| | | | | | | | | | | | | | The atom that uploads push constants listens to _NEW_TRANSFORM for legacy clip plane handling. On Sandybridge, the gen6_vs_state atom emits 3DSTATE_CONSTANT_VS as well as 3DSTATE_VS, so it needs to listen to the same set of conditions. However, it looks like Gen7 doesn't need this. The push constant atom emits 3DSTATE_CONSTANT_VS directly, and the gen7_vs_state atom that emits 3DSTATE_VS doesn't have a dependency on ctx->Transform. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* i965: Fix brw_clear_cache to clean up TCS/TES shaders.Kenneth Graunke2016-10-041-0/+2
| | | | | | | We need to free prog_data for TCS/TES too. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
generated by cgit v1.1 at 2024-05-19 22:12:12 +0000