| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | i965: use align1 access mode for instructions with execSize=1 in VS | Xiang, Haihao | 2010-12-24 | 1 | -0/+2 |
| * | i965: fix register region description | Xiang, Haihao | 2010-12-24 | 1 | -1/+1 |
| * | intel: Remove unnecessary headers. | Vinson Lee | 2010-12-23 | 2 | -2/+0 |
| * | i965: Remove unnecessary headers. | Vinson Lee | 2010-12-23 | 1 | -2/+0 |
| * | i965: Keep around a copy of the VS constant surface dumping code. | Eric Anholt | 2010-12-23 | 1 | -0/+9 |
| * | i965: Correct the dp_read message descriptor setup on g4x. | Eric Anholt | 2010-12-23 | 3 | -1/+23 |
| * | i965: upload multisample state for fragment program change | Zhenyu Wang | 2010-12-23 | 3 | -25/+38 |
| * | i965: Use MI_FLUSH_DW for blt ring flush on sandybridge | Zhenyu Wang | 2010-12-23 | 2 | -2/+7 |
| * | i965: explicit tell header present for fb write on sandybridge | Zhenyu Wang | 2010-12-22 | 4 | -8/+8 |
| * | i965: Avoid using float type for raw moves, to work around SNB issue. | Eric Anholt | 2010-12-21 | 2 | -4/+8 |
| * | intel: Check for unsupported texture when finishing using as a render target | Chris Wilson | 2010-12-21 | 1 | -1/+2 |
| * | nouveau: fix includes for latest libdrm | Ben Skeggs | 2010-12-21 | 1 | -1/+1 |
| * | r600c : inline vertex format is not updated in an app, switch to use vfetch c... | richard | 2010-12-16 | 1 | -1/+1 |
| * | intel: Support glCopyTexImage() from XRGB8888 to ARGB8888. | Eric Anholt | 2010-12-16 | 3 | -2/+94 |
| * | intel: Try to sanely check that formats match for CopyTexImage. | Eric Anholt | 2010-12-16 | 1 | -40/+20 |
| * | intel: Drop commented intel_flush from copy_teximage. | Eric Anholt | 2010-12-16 | 1 | -1/+0 |
| * | intel: Update renderbuffers before looking up CopyTexImage's read buffer. | Eric Anholt | 2010-12-16 | 1 | -3/+4 |
| * | i965: Set the alternative floating point mode on gen6 VS and WM. | Eric Anholt | 2010-12-16 | 3 | -0/+8 |
| * | i915: Fix INTEL_DEBUG=wm segmentation fault | Shuang He | 2010-12-16 | 1 | -5/+5 |
| * | i965: Add support for using the BLT ring on gen6. | Eric Anholt | 2010-12-13 | 8 | -56/+72 |
| * | i965: Improve the hacks for ARB_fp scalar^scalar POW on gen6. | Eric Anholt | 2010-12-13 | 1 | -36/+17 |
| * | i965: Fix gl_FragCoord.z setup on gen6. | Eric Anholt | 2010-12-13 | 1 | -2/+7 |
| * | i956: Fix the old FP path fragment position setup on gen6. | Eric Anholt | 2010-12-13 | 1 | -18/+20 |
| * | i965: Fix ARL to work on gen6. | Eric Anholt | 2010-12-13 | 1 | -1/+17 |
| * | intel: Include stdbool so we can stop using GLboolean when we want to. | Eric Anholt | 2010-12-13 | 2 | -14/+12 |
| * | r300/compiler: fix swizzle lowering with a presubtract source operand | Marek Olšák | 2010-12-11 | 1 | -0/+1 |
| * | r300/compiler: fix LIT in VS | Marek Olšák | 2010-12-11 | 1 | -1/+2 |
| * | i965: Put common info on converting MESA_FORMAT to BRW_FORMAT in a table. | Eric Anholt | 2010-12-10 | 1 | -126/+42 |
| * | intel: Just use ChooseTextureFormat for renderbuffer format choice. | Eric Anholt | 2010-12-10 | 1 | -52/+9 |
| * | intel: Add a couple of helper functions to reduce rb code duplication. | Eric Anholt | 2010-12-10 | 5 | -138/+78 |
| * | intel: Add spans code for the ARB_texture_rg support. | Eric Anholt | 2010-12-10 | 2 | -0/+154 |
| * | mesa/meta: fix broken assertion, rename stack depth var | Brian Paul | 2010-12-10 | 1 | -5/+7 |
| * | i965: support for two-sided lighting on Sandybridge | Xiang, Haihao | 2010-12-10 | 5 | -6/+72 |
| * | meta: allow nested meta operations | Xiang, Haihao | 2010-12-10 | 1 | -4/+10 |
| * | i965: Add support for gen6 reladdr VS constant loading. | Eric Anholt | 2010-12-09 | 2 | -11/+17 |
| * | i965: Add support for gen6 constant-index constant loading. | Eric Anholt | 2010-12-09 | 2 | -3/+9 |
| * | intel: Set the swizzling for depth textures using the GL_RED depth mode. | Eric Anholt | 2010-12-09 | 2 | -0/+8 |
| * | intel: Use plain R8 and RG8 for COMPRESSED_RED and COMPRESSED_RG. | Eric Anholt | 2010-12-09 | 1 | -0/+2 |
| * | i965: Silence uninitialized variable warning. | Vinson Lee | 2010-12-09 | 1 | -0/+5 |
| * | i965: remove unused variable since brw_wm_glsl.c removal. | Eric Anholt | 2010-12-09 | 2 | -2/+1 |
| * | i965: Set render_cache_read_write surface state bit on gen6 constant surfs. | Eric Anholt | 2010-12-09 | 2 | -0/+9 |
| * | i965: Set up the correct texture border color state struct for Ironlake. | Eric Anholt | 2010-12-09 | 2 | -5/+45 |
| * | i965: Clean up VS constant buffer location setup. | Eric Anholt | 2010-12-09 | 1 | -15/+3 |
| * | i965: Fix VS constants regression pre-gen6. | Eric Anholt | 2010-12-09 | 1 | -1/+1 |
| * | i965: Drop push-mode reladdr constant loading and always use constant_map. | Eric Anholt | 2010-12-08 | 4 | -93/+96 |
| * | radeon: bump mip tree levels to 15 | Alex Deucher | 2010-12-09 | 1 | -1/+1 |
| * | i965: Drop KIL_NV from the ff/ARB_fp path since it was only used for GLSL. | Eric Anholt | 2010-12-08 | 3 | -21/+0 |
| * | i965: Use the new pixel mask location for gen6 ARB_fp KIL instructions. | Eric Anholt | 2010-12-08 | 1 | -2/+8 |
| * | i965: Set the render target index in gen6 fixed-function/ARB_fp path. | Eric Anholt | 2010-12-08 | 1 | -0/+7 |
| * | i965: Set up the per-render-target blend state on gen6. | Eric Anholt | 2010-12-08 | 1 | -46/+49 |
