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| * | intel-gem: Disable spantmp sse/mmx functions when tile swizzling.Eric Anholt2008-07-152-3/+17
| | | | | | | | | | | | | | | | | | | | | Those functions rely on being able to treat the GET_PTR returned value as an array indexed by x, but that's not the case for our tiling. Bug #16387
| * | i915: fix build after previous commit.Eric Anholt2008-07-141-1/+1
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| * | drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.Eric Anholt2008-07-1118-298/+250
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| * | intel: span rendering requires just a flush before starting, not finish.Eric Anholt2008-07-021-1/+1
| | | | | | | | | | | | The dri_bo_map()s that follow will take care of idling the hardware as needed.
| * | intel-gem: Emit an MI_FLUSH at glFlush() so frontbuffer rendering is flushed.Eric Anholt2008-07-021-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | We have something similar in the X Server that covers X Server rendering, this is the equivalent here for rendering to the front buffer. If we cared about avoiding this at glFlush time, we could only do this when some actual frontbuffer rendering had occurred. Bug #16392.
| * | intel-gem: Fix y-tile swizzling for our G965 with swizzle_mode=1.Eric Anholt2008-07-021-0/+10
| | | | | | | | | | | | | | | Apparently in Y mode we get bit 6 ^ bit 9. The reflect demo in 'd' mode now displays correctly.
| * | intel-gem: Fix Y-tiling span setup.Eric Anholt2008-07-026-27/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | The boolean that the server gives us for whether the region is tiled was getting used as the enum for what tiling mode. Instead, guess the correct tiling in screen setup. Also, fix the Y-tiling pitch setup. The pitch to the next tile in Y is 32 scanlines, not 8.
| * | intel-gem: Move bit 6 x tiling swizzle to a driconf option, and add new mode.Eric Anholt2008-07-014-18/+46
| | | | | | | | | | | | | | | | | | It turns out that it's not just deviceID dependent, and there's some additional undefined factor that determines the bit 6 swizzling. It's now controllable with swizzle_mode=[012] until we get a response on how to automatically detect.
| * | intel: Fix locking when doing intel_region_cow().Eric Anholt2008-06-261-2/+2
| | | | | | | | | | | | | | | This was broken in the merge of 965 blit support. It tried to lock only when things were already locked.
| * | intel: Replace sprinkled intel_batchbuffer_flush with MI_FLUSH or nothing.Eric Anholt2008-06-2613-112/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | Most of these were to ensure that caches got synchronized between 2d (or meta) rendering and later use of the target as a source, such as for texture miptree setup. Those are replaced with intel_batchbuffer_emit_mi_flush(), which just drops an MI_FLUSH. Most of the remainder were to ensure that REFERENCES_CLIPRECTS batchbuffers got flushed before the lock was dropped. Those are now replaced by automatically flushing those when dropping the lock.
| * | Merge commit 'origin/master' into drm-gemEric Anholt2008-06-2488-996/+417
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| * | | i915: Accumulate the VB into a local buffer and subdata it in.Eric Anholt2008-06-237-31/+48
| | | | | | | | | | | | | | | | This lets GEM use pwrite, for an additional 4% or so speedup.
| * | | i915: Convert to using VBs instead of inline prims.Eric Anholt2008-06-239-214/+299
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| * | | i915: Note the non-PBO fallback for textured drawpixels under DEBUG_PIXEL.Eric Anholt2008-06-181-1/+2
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| * | | i915: Restore the accelerated PBO pixel path functions after GEM changes.Eric Anholt2008-06-185-24/+5
| | | | | | | | | | | | | | | | | | | | The fencing code is not required, and waiting on the fences defeated one of the purposes of the extension, which is to allow asynchronous readpixels.
| * | | Merge commit 'origin/master' into drm-gemEric Anholt2008-06-1867-4335/+5961
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| * | | | [intel] Fix no_rast option on non-965.Eric Anholt2008-06-173-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | The no_rast fallback was getting partially overwritten by later TNL init, resulting in a segfault when things were in a mixed-up state.
| * | | | [intel-gem] Bug #16326: Fix X tile unswizzling on 965.Eric Anholt2008-06-171-0/+26
| | | | | | | | | | | | | | | | | | | | Apparently a bit gets flipped in the addressing for some rows of each tile.
| * | | | [intel-gem] Chase domain flag renaming in the DRM.Eric Anholt2008-06-1114-41/+41
| | | | | | | | | | | | | | | | | | | | This is an API breakage only.
| * | | | [gem] Enable bo_reuse by default.Eric Anholt2008-06-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The objects are swappable, so we're less concerned by excessive object allocation now, and it's about a 20% performance improvement. If we get concerns about the memory consumption from others, we can look into a compromise position later.
| * | | | [intel-gem] Call the new throttle ioctl from swap buffersKeith Packard2008-06-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Swap buffers is a fairly reasonable time to wait for the hardware for a while; this keeps us from overrunning the ring.
| * | | | Merge commit 'origin/master' into drm-gemKeith Packard2008-06-03116-3074/+8367
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/common/dri_bufmgr.h src/mesa/drivers/dri/intel/intel_bufmgr_ttm.c src/mesa/drivers/dri/intel/intel_bufmgr_ttm.h src/mesa/drivers/dri/intel/intel_ioctl.c
| * | | | | [intel] Convert drivers to using libdrm bufmgr code.Eric Anholt2008-06-0335-3737/+105
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| * | | | | [intel-gem] Remember last offset of reused BOs to avoid more kernel relocs.Eric Anholt2008-05-301-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | This is good for about 5% on ipers on 965, and should help any cpu-bound app.
| * | | | | [intel-gem] Once mapped, leave buffers mapped.Keith Packard2008-05-281-17/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mapping and unmapping buffers is expensive, and having the map around isn't harmful (other than consuming address space). So, once mapped, just leave buffers mapped in case they get re-used.
| * | | | | [intel] all flushing in intelEmitCopyBlitKeith Packard2008-05-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add both MI_FLUSH and intel_batchbuffer_flush to intelEmitCopyBlit. This ensures that the data are flushed *and* the gem kernel driver sees the various memory domain transitions.
| * | | | | [intel] Enable buffer re-use for gemKeith Packard2008-05-251-12/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the new DRM_IOCTL_I915_GEM_BUSY ioctl to detect idle buffers for re-use.
| * | | | | Remove stale comment about glFlush().Eric Anholt2008-05-231-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't need an MI_FLUSH there, because everything that's been flushed in the batch will eventually hit the hardware.
| * | | | | Emit a flush after the swapbuffers blit, so contents end up on the screen.Eric Anholt2008-05-235-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise, since the MI_FLUSH at the end of every batch had been removed, non-automatic-flushing chips (965) wouldn't get flushed and apps with static rendering would get partial screen contents until the server's blockhandler flush kicked in.
| * | | | | Add back a mostly-correct glFinish for GEM and fake.Eric Anholt2008-05-225-4/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The right solution would probably be keeping a list of regions which have been rendered to.
| * | | | | [intel-gem] Make sure set_domain is called often enough.Keith Packard2008-05-221-31/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The write_domain needs to be set after any batch buffer uses an object, track when that happens in the new 'cpu_domain_set' field.
| * | | | | [intel-gem] Don't calloc reloc buffersKeith Packard2008-05-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only a few relocations are typically used, so don't clear the whole thing.
| * | | | | [GEM] Actually include the presumed offset in initial relocations.Eric Anholt2008-05-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This avoids kernel relocations for most batchbuffer relocs.
| * | | | | [intel] update GEM api. Add bo_subdata and bo_get_subdata driver hooks.Keith Packard2008-05-115-68/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Track DRM GEM name changes. Add driver hooks for bo_subdata and bo_get_subdata so that GEM can use pread and pwrite.
| * | | | | [intel-gem] move domains to relocations. add set_domain to bo_map.Keith Packard2008-05-081-22/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the kernel API to place the read/write domain information in the relocation instead of the buffer.
| * | | | | [intel] intel_batchbuffer_flush using uninit 'used' to check for buffer emptyKeith Packard2008-05-082-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure 'used' tracks the right value through the whole function. Also, use GLint for intel_batchbuffer_space in case we do bad things in the future.
| * | | | | GEM: Remove already-disabled PIPE_CONTROL command.Eric Anholt2008-05-072-35/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This existed to get the icache flushed. However, GEM handles this for us now for sure, and we had disabled it prematurely anyway.
| * | | | | GEM: Make dri_emit_reloc take GEM domain flags instead of TTM flags.Eric Anholt2008-05-0727-115/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GEM flags are much more descriptive for what we need. Since this makes bufmgr_fake rather device-specific, move it to the intel common directory. We've wanted to do device-specific stuff to it before.
| * | | | | GEM: Don't emit an extra MI_FLUSH in the batch since GEM handles it.Eric Anholt2008-05-071-13/+18
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| * | | | | [intel-GEM] partial support for memory domains.Keith Packard2008-05-061-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Doesn't deal with local modifications yet (need new kernel set_domain ioctl for that to work). Also, guesses what domains are affected based on the read/write bits set in the flags. Works for 915, probably not so much for 965.
| * | | | | [intel-GEM] Add tiling support to swrast.Keith Packard2008-05-067-25/+350
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Accessing tiled surfaces without using the fence registers requires that software deal with the address swizzling itself.
| * | | | | Dump buffer tiled status from intelPrintSAREAKeith Packard2008-05-051-6/+6
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| * | | | | GEM: Allocate the right number of relocs, avoiding heap smashing.Eric Anholt2008-05-051-1/+1
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| * | | | | GEM: Include target buffer handle in relocation debug.Eric Anholt2008-05-051-2/+2
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| * | | | | GEM: Set validate index to keep the same buffer from being duped on the list.Eric Anholt2008-05-051-0/+1
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| * | | | | Print GEM handles instead of BO pointers in debugging.Eric Anholt2008-05-051-15/+18
| | | | | | | | | | | | | | | | | | | | | | | | small integers are much prettier, and let me correlate to DRM debug output.
| * | | | | Initialize bufmgr_gem->validate_array[i].offset.Eric Anholt2008-05-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is just cosmetic, to produce less scary values when the ioctl fails and doesn't return values there.
| * | | | | Make intel_{batch,exec}_ioctl return an error code so we can recover better.Eric Anholt2008-05-053-26/+33
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| * | | | | Add intel_bufmgr_gem.c to i915Keith Packard2008-05-051-0/+1
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| * | | | | Temporarily disable intel pixel ops on i915 for GEMKeith Packard2008-05-053-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of attempting to fix these for GEM, just disable until GEM is working.
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