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* glsl: Add shared variable typeJordan Justen2015-11-092-1/+2
| | | | | | | | | | Shared variables are stored in a common pool accessible by all threads in a compute shader local work group. These variables are similar to OpenCL's local/__local variables. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
* glsl: Add space to shader_storage in print_visitorJordan Justen2015-11-091-1/+1
| | | | | Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
* glsl: Align comments on variables typesJordan Justen2015-11-091-7/+7
| | | | | | | | v2: * Split from patch to add ir_var_shader_shared (tarceri) Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
* glsl: Parse shared keyword for compute shader variablesJordan Justen2015-11-095-1/+17
| | | | | | | | | | v2: * Move shared parsing under storage qualifiers (tarceri) * Fail to compile if shared is used in non-compute shader (tarceri) * Use separate shared_storage bit for shared variables (tarceri) Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
* glsl: simplify interface block stream qualifier validationTimothy Arceri2015-11-102-23/+14
| | | | | | | | | Qualifiers on member variables are redundent all we need to do if check if it matches the stream associated with the block and throw an error if its not. Reviewed-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com> Cc: Emil Velikov <emil.l.velikov@gmail.com>
* st/wgl: add null pointer check for HUD textureBrian Paul2015-11-091-1/+3
| | | | | | Fixes crash when using HUD with Nobel Clinician Viewer. Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
* st/wgl: fix double-present on swapbuffers bugBrian Paul2015-11-093-20/+12
| | | | | | | | | | | | | | | | | | The stw_st_framebuffer_present_locked() function was getting called twice per SwapBuffers. First, when st_context_iface::flush() was called from DrvSwapBuffers() because the ST_FLUSH_FRONT flag was given. Second, by stw_st_swap_framebuffer_locked() which does the actual SwapBuffers. Two code changes: 1. Pass ST_FLUSH_END_OF_FRAME, instead of ST_FLUSH_FRONT. 2. Move the implementation of stw_flush_current_locked() into DrvSwapBuffers() since it's not called anywhere else. Not much change in perf for benchmarks like Lightsmark, but some simple Mesa demos are measurably faster. Reviewed-by: José Fonseca <jfonseca@vmware.com>
* st/wgl: reorder pixel formats to put MSAA formats lastBrian Paul2015-11-091-29/+32
| | | | | | | | | | | | | And put 8-bit/channel formats before 5/6/5 formats. The ChoosePixelFormat() function seems to be finicky about format selection. Putting the MSAA formats after the non-MSAA formats means most apps get a low-numbered format. Now we generally get the same pixel format regardless of whether using vgpu9 or 10. VMware bug 1455030 Reviewed-by: José Fonseca <jfonseca@vmware.com>
* st/wgl: Don't rely on GDI to bookkeep pixelformat for us.José Fonseca2015-11-092-7/+6
| | | | | | | This allows to use apitrace's retracediff script on Windows to retrace and compare two builds of a Mesa based opengl32.dll/ICD side-by-side. See also https://github.com/apitrace/apitrace/commit/e4a4f15f5b92e0abbd24d7d053da25f8278c9f64
* winsys/radeon: Use CPU page size instead of hardcoding 4096 bytes v3Michel Dänzer2015-11-091-11/+19
| | | | | | | | | | | | | | | Fixes GPUVM conflicts with non-4K page size. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92738 v2: Replace sanitization of VM base address alignment with comment why that's not necessary. v3: Use unsigned instead of long as the type for the size_align member. (Marek) Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Christian König <christian.koenig@amd.com> (v1) Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* st/omx: add headless supportLeo Liu2015-11-081-10/+35
| | | | | | | | | | | This will allow dec/enc/transcode without X v2: use env override even with X, use loader_open_device instead of open v3: clean up Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
* st/va: use vl screen drm support from vl_wys_drmLeo Liu2015-11-081-21/+3
| | | | | | | v2: move the dup to vl_wys_drm for pipe loader Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
* vl: add drm support for vl_screenLeo Liu2015-11-083-1/+85
| | | | | | | | | | This will allow the state trackers to use render nodes with screen creation v2: dup fd for pipe loader Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
* st/va: fix build fails with pipe loaderLeo Liu2015-11-081-2/+3
| | | | | | | There is no dev in drv, and dev should be from vl_screen here Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
* nvc0: enable compute support on FermiSamuel Pitoiset2015-11-081-2/+2
| | | | | | | | | | | Altough the compute support is still not complete because textures and surfaces need to be implemented, it allows to launch very simple compute kernel like one which reads reading MP performance counters. This turns on PIPE_CAP_COMPUTE and PIPE_SHADER_COMPUTE. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nv50/ir: fix emission of s[] args in certain situationsIlia Mirkin2015-11-071-2/+2
| | | | | | | | | | There might only be a single arg (e.g. cvt), so use mode rather than looking at the source directly. Also we don't want to rely on the type of the value, which can be unreliable, but instead use the instruction's. This works out well since mkSplit doesn't adjust the type. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nv50/ir: only take abs value when computing high resultIlia Mirkin2015-11-071-1/+1
| | | | | | | | Not reachable from TGSI since it only has UMUL, no IMUL. However it's surprising that setting argument types to s32 will cause sign to get lost. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nouveau: avoid queueing too much work onto a single fenceIlia Mirkin2015-11-072-26/+43
| | | | | | | | | | Force the fence to get kicked off, which won't actually wait for its completion, but any additional work will be put onto a fresh list. This fixes crashes in teximage-colors --benchmark with too many active maps. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
* llvmpipe: disable front updates for nowDave Airlie2015-11-081-1/+1
| | | | | | | | As pointed out by Emil, this sometimes hangs, appears to be due to threading need to rethink how this stuff works for llvmpipe. Signed-off-by: Dave Airlie <airlied@redhat.com>
* virgl: wrap ret assignment with braces to do correct thingDave Airlie2015-11-082-2/+2
| | | | | | | Coverity reported that ret could only be 0 or 1, since it was setting ret = fn() > 0, instead of doing (ret = fn()) > 0. Signed-off-by: Dave Airlie <airlied@redhat.com>
* nir: Add a nir_deref_tail helperJason Ekstrand2015-11-073-23/+13
| | | | Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
* nir/types: Add an is_vector_or_scalar helperJason Ekstrand2015-11-072-0/+7
| | | | Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
* i965/fs: Use regs_read/written for post-RA scheduling in calculate_depsJason Ekstrand2015-11-071-11/+4
| | | | | | | | | | | | Previously, we were assuming that everything read/wrote exactly 1 logical GRF (1 in SIMD8 and 2 in SIMD16). This isn't actually true. In particular, the PLN instruction reads 2 logical registers in one of the components. This commit changes post-RA scheduling to use regs_read and regs_written instead so that we add enough dependencies. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92770 Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
* nir/validate: Add better validation of load/store typesJason Ekstrand2015-11-071-2/+14
| | | | Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
* radeonsi: add register definitions for StoneyMarek Olšák2015-11-071-0/+322
| | | | | | There are a few non-stoney changes too. Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* radeonsi: add workarounds for CP DMA to stay on the fast pathMarek Olšák2015-11-071-5/+88
| | | | | | v2: set emit_scratch_reloc, add a NULL check Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: unify CP DMA preparation logicMarek Olšák2015-11-071-37/+34
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: unify CP DMA code determining various flagsMarek Olšák2015-11-071-28/+23
| | | | | | v2: don't call get_flush_flags twice per function Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: only enable write confirmation on the last CP DMA packetMarek Olšák2015-11-071-2/+4
| | | | | | This should improve performance for big copies that need to be split. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* nv50/ir: allow emission of immediates in imul/imad opsIlia Mirkin2015-11-071-2/+8
| | | | | | | Nothing actually uses this yet (due to complications), but the emission logic is right. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nv50/ir: properly set the type of the constant folding resultIlia Mirkin2015-11-061-4/+4
| | | | | | | This removes the hack used for merge, which only covers a fraction of the cases. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nv50/ir: add support for const-folding OP_CVT with F64 source/destIlia Mirkin2015-11-063-0/+45
| | | | Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nv50/ir: add fp64 opcode emission support for G200 (NVA0)Ilia Mirkin2015-11-061-10/+84
| | | | | | Need to emulate rcp/rsq before providing full fp64 support Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nv50/ir: Add support for 64bit immediates to checkSwapSrc01Hans de Goede2015-11-061-5/+6
| | | | | | | | Now that we support 64 bit immediates in insnCanLoad, we need to swap 64 bit immediate sources too for optimal effect. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nvc0/ir: Teach insnCanLoad about double immediatesHans de Goede2015-11-061-6/+19
| | | | | | | | | | | | | | | | Teach insnCanLoad about double immediates, together with the "Add support for merge-s to the ConstantFolding pass" This turns the following (nvc0) code: 1: mov u32 $r2 0x00000000 (8) 2: mov u32 $r3 0x3fe00000 (8) 3: add f64 $r0d $r0d $r2d (8) Into: 1: add f64 $r0d $r0d 0.500000 (8) Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nv50/ir: Add support for merge-s to the ConstantFolding passHans de Goede2015-11-061-0/+15
| | | | | | | | | | | This allows later passes like LoadPropagation to properly deal with 64 bit immediates. If the new 64 bit load this introduces does not get optimized away then split64BitOpPostRA() will split this into 2 instructions again. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nv50/ir: disallow 64-bit immediates on nv50 targetsIlia Mirkin2015-11-061-1/+1
| | | | | | No instructions are able to load short immediates like nvc0 can. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nv50/ir: allow movs with TYPE_F64 destinations to be splitIlia Mirkin2015-11-061-0/+6
| | | | Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
* gm107/ir: Add support for double immediatesHans de Goede2015-11-061-1/+4
| | | | | | | | Add support for encoding double immediates (up to 20 bits of precision) into the generated gm107 machine-code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* nvc0/ir: Add support for double immediatesHans de Goede2015-11-061-0/+8
| | | | | | | | Add support for encoding double immediates (up to 20 bits of precision) into the generated nvc0 machine-code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* i965/nir/fs: Add comment for no-op memory barrier functionsFrancisco Jerez2015-11-061-0/+19
| | | | Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* i965/nir/fs: Implement new barrier functions for compute shadersJordan Justen2015-11-061-0/+7
| | | | | | | | | | | | | | | | | | | | | | For these nir intrinsics, we emit the same code as nir_intrinsic_memory_barrier: * nir_intrinsic_memory_barrier_atomic_counter * nir_intrinsic_memory_barrier_buffer * nir_intrinsic_memory_barrier_image We treat these nir intrinsics as no-ops: * nir_intrinsic_group_memory_barrier * nir_intrinsic_memory_barrier_shared v3: * Add comment for no-op cases (curro) v4: * Moving comment to a separate patch authored by curro Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
* nir: Add new barrier functions for compute shadersJordan Justen2015-11-062-0/+26
| | | | | | | | When these functions are called in glsl-ir, we create a corresponding nir intrinsic function call. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
* glsl: Add new barrier functions for compute shadersJordan Justen2015-11-061-6/+49
| | | | | | | | | | | | | | | | | | | | | When these functions are called in GLSL code, we create an intrinsic function call: * groupMemoryBarrier => __intrinsic_group_memory_barrier * memoryBarrierAtomicCounter => __intrinsic_memory_barrier_atomic_counter * memoryBarrierBuffer => __intrinsic_memory_barrier_buffer * memoryBarrierImage => __intrinsic_memory_barrier_image * memoryBarrierShared => __intrinsic_memory_barrier_shared v2: * Consolidate with memoryBarrier function/intrinsic creation (curro) v3: * Instead of add_memory_barrier_function, add an intrinsic_name parameter to _memory_barrier (curro) Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
* radeon/uvd: fix VC-1 simple/main profile decode v2Boyuan Zhang2015-11-062-2/+7
| | | | | | | | | | | We just needed to set the extra width/height fields to get this working. v2 (chk): rebased, CC stable added, commit message added, fixed coding style Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
* st/vaapi: fix vaapi VC-1 simple/main corruption v2Boyuan Zhang2015-11-061-0/+2
| | | | | | | | | | | Apply the start code fix only to advanced profile. v2 (chk): add commit message Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
* st/va: add support for RGBX and BGRX in VPPJulien Isorce2015-11-062-18/+23
| | | | | | | | | | | | | | Before it was only possible to convert a NV12 surface to RGBA or BGRA. This patch uses the same post processing function, "handleVAProcPipelineParameterBufferType", but add definitions for RGBX and BGRX. This patch also makes vlVaQuerySurfaceAttributes more generic to avoid copy and pasting the same lines. Signed-off-by: Julien Isorce <j.isorce@samsung.com> Reviewed-by: Christian K<C3><B6>nig <christian.koenig@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
* vl/buffers: add RGBX and BGRX to the supported formatsJulien Isorce2015-11-061-0/+18
| | | | | | | | | | Useful is one wants to create RGBX or BGRX surfaces. The infrastructure is such that it required just a few definitions to support these formats. Signed-off-by: Julien Isorce <j.isorce@samsung.com> Reviewed-by: Christian K<C3><B6>nig <christian.koenig@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
* st/va: properly use brackets in vlVaAcquireBufferHandle's switchJulien Isorce2015-11-061-5/+4
| | | | | | | | | In "switch (mem_type)" the brackets were surrounding "case+default" instead of "case" only. Signed-off-by: Julien Isorce <j.isorce@samsung.com> Reviewed-by: Christian K<C3><B6>nig <christian.koenig@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
* st/va: properly indent buffer.c, config.c, image.c and picture.cJulien Isorce2015-11-064-56/+56
| | | | | | | | Some lines were using 4 indentation spaces instead of 3. Signed-off-by: Julien Isorce <j.isorce@samsung.com> Reviewed-by: Christian K<C3><B6>nig <christian.koenig@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
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