summaryrefslogtreecommitdiffstats
path: root/src/gallium/drivers/vc4/vc4_nir_lower_io.c
blob: a98d70da7d8bb3ebcc485be8c60358b118c98a8e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
/*
 * Copyright © 2015 Broadcom
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */

#include "vc4_qir.h"
#include "glsl/nir/nir_builder.h"

/**
 * Walks the NIR generated by TGSI-to-NIR to lower its io intrinsics into
 * something amenable to the VC4 architecture.
 *
 * Currently, it split inputs, outputs, and uniforms into scalars, drops any
 * non-position outputs in coordinate shaders, and fixes up the addressing on
 * indirect uniform loads.
 */

static void
replace_intrinsic_with_vec4(nir_builder *b, nir_intrinsic_instr *intr,
                            nir_ssa_def **comps)
{

        /* Batch things back together into a vec4.  This will get split by the
         * later ALU scalarization pass.
         */
        nir_ssa_def *vec = nir_vec4(b, comps[0], comps[1], comps[2], comps[3]);

        /* Replace the old intrinsic with a reference to our reconstructed
         * vec4.
         */
        nir_ssa_def_rewrite_uses(&intr->dest.ssa, nir_src_for_ssa(vec));
        nir_instr_remove(&intr->instr);
}

static void
vc4_nir_lower_input(struct vc4_compile *c, nir_builder *b,
                    nir_intrinsic_instr *intr)
{
        b->cursor = nir_before_instr(&intr->instr);

        if (c->stage == QSTAGE_FRAG && intr->const_index[0] ==
            VC4_NIR_TLB_COLOR_READ_INPUT) {
                /* This doesn't need any lowering. */
                return;
        }

        nir_variable *input_var = NULL;
        foreach_list_typed(nir_variable, var, node, &c->s->inputs) {
                if (var->data.driver_location == intr->const_index[0]) {
                        input_var = var;
                        break;
                }
        }
        assert(input_var);

        /* All TGSI-to-NIR inputs are vec4. */
        assert(intr->num_components == 4);

        /* Generate scalar loads equivalent to the original VEC4. */
        nir_ssa_def *dests[4];
        for (unsigned i = 0; i < intr->num_components; i++) {
                nir_intrinsic_instr *intr_comp =
                        nir_intrinsic_instr_create(c->s, nir_intrinsic_load_input);
                intr_comp->num_components = 1;
                intr_comp->const_index[0] = intr->const_index[0] * 4 + i;
                nir_ssa_dest_init(&intr_comp->instr, &intr_comp->dest, 1, NULL);
                nir_builder_instr_insert(b, &intr_comp->instr);

                dests[i] = &intr_comp->dest.ssa;
        }

        switch (c->stage) {
        case QSTAGE_FRAG:
                if (input_var->data.location == VARYING_SLOT_FACE) {
                        dests[0] = nir_fsub(b,
                                            nir_imm_float(b, 1.0),
                                            nir_fmul(b,
                                                     nir_i2f(b, dests[0]),
                                                     nir_imm_float(b, 2.0)));
                        dests[1] = nir_imm_float(b, 0.0);
                        dests[2] = nir_imm_float(b, 0.0);
                        dests[3] = nir_imm_float(b, 1.0);
                } else if (input_var->data.location >= VARYING_SLOT_VAR0) {
                        if (c->fs_key->point_sprite_mask &
                            (1 << (input_var->data.location -
                                   VARYING_SLOT_VAR0))) {
                                if (!c->fs_key->is_points) {
                                        dests[0] = nir_imm_float(b, 0.0);
                                        dests[1] = nir_imm_float(b, 0.0);
                                }
                                if (c->fs_key->point_coord_upper_left) {
                                        dests[1] = nir_fsub(b,
                                                            nir_imm_float(b, 1.0),
                                                            dests[1]);
                                }
                                dests[2] = nir_imm_float(b, 0.0);
                                dests[3] = nir_imm_float(b, 1.0);
                        }
                }
                break;
        case QSTAGE_COORD:
        case QSTAGE_VERT:
                break;
        }

        replace_intrinsic_with_vec4(b, intr, dests);
}

static void
vc4_nir_lower_output(struct vc4_compile *c, nir_builder *b,
                     nir_intrinsic_instr *intr)
{
        nir_variable *output_var = NULL;
        foreach_list_typed(nir_variable, var, node, &c->s->outputs) {
                if (var->data.driver_location == intr->const_index[0]) {
                        output_var = var;
                        break;
                }
        }
        assert(output_var);

        if (c->stage == QSTAGE_COORD &&
            output_var->data.location != VARYING_SLOT_POS &&
            output_var->data.location != VARYING_SLOT_PSIZ) {
                nir_instr_remove(&intr->instr);
                return;
        }

        /* Color output is lowered by vc4_nir_lower_blend(). */
        if (c->stage == QSTAGE_FRAG &&
            (output_var->data.location == FRAG_RESULT_COLOR ||
             output_var->data.location == FRAG_RESULT_DATA0)) {
                intr->const_index[0] *= 4;
                return;
        }

        /* All TGSI-to-NIR outputs are VEC4. */
        assert(intr->num_components == 4);

        b->cursor = nir_before_instr(&intr->instr);

        for (unsigned i = 0; i < intr->num_components; i++) {
                nir_intrinsic_instr *intr_comp =
                        nir_intrinsic_instr_create(c->s, nir_intrinsic_store_output);
                intr_comp->num_components = 1;
                intr_comp->const_index[0] = intr->const_index[0] * 4 + i;

                assert(intr->src[0].is_ssa);
                intr_comp->src[0] = nir_src_for_ssa(nir_swizzle(b,
                                                                intr->src[0].ssa,
                                                                &i, 1, false));
                nir_builder_instr_insert(b, &intr_comp->instr);
        }

        nir_instr_remove(&intr->instr);
}

static void
vc4_nir_lower_uniform(struct vc4_compile *c, nir_builder *b,
                      nir_intrinsic_instr *intr)
{
        /* All TGSI-to-NIR uniform loads are vec4, but we may create dword
         * loads in our lowering passes.
         */
        if (intr->num_components == 1)
                return;
        assert(intr->num_components == 4);

        b->cursor = nir_before_instr(&intr->instr);

        /* Generate scalar loads equivalent to the original VEC4. */
        nir_ssa_def *dests[4];
        for (unsigned i = 0; i < intr->num_components; i++) {
                nir_intrinsic_instr *intr_comp =
                        nir_intrinsic_instr_create(c->s, intr->intrinsic);
                intr_comp->num_components = 1;
                nir_ssa_dest_init(&intr_comp->instr, &intr_comp->dest, 1, NULL);

                if (intr->intrinsic == nir_intrinsic_load_uniform_indirect) {
                        /* Convert the variable TGSI register index to a byte
                         * offset.
                         */
                        intr_comp->src[0] =
                                nir_src_for_ssa(nir_ishl(b,
                                                         intr->src[0].ssa,
                                                         nir_imm_int(b, 4)));

                        /* Convert the offset to be a byte index, too. */
                        intr_comp->const_index[0] = (intr->const_index[0] * 16 +
                                                     i * 4);
                } else {
                        /* We want a dword index for non-indirect uniform
                         * loads.
                         */
                        intr_comp->const_index[0] = (intr->const_index[0] * 4 +
                                                     i);
                }

                dests[i] = &intr_comp->dest.ssa;

                nir_builder_instr_insert(b, &intr_comp->instr);
        }

        replace_intrinsic_with_vec4(b, intr, dests);
}

static void
vc4_nir_lower_io_instr(struct vc4_compile *c, nir_builder *b,
                       struct nir_instr *instr)
{
        if (instr->type != nir_instr_type_intrinsic)
                return;
        nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);

        switch (intr->intrinsic) {
        case nir_intrinsic_load_input:
                vc4_nir_lower_input(c, b, intr);
                break;

        case nir_intrinsic_store_output:
                vc4_nir_lower_output(c, b, intr);
                break;

        case nir_intrinsic_load_uniform:
        case nir_intrinsic_load_uniform_indirect:
                vc4_nir_lower_uniform(c, b, intr);
                break;

        default:
                break;
        }
}

static bool
vc4_nir_lower_io_block(nir_block *block, void *arg)
{
        struct vc4_compile *c = arg;
        nir_function_impl *impl =
                nir_cf_node_get_function(&block->cf_node);

        nir_builder b;
        nir_builder_init(&b, impl);

        nir_foreach_instr_safe(block, instr)
                vc4_nir_lower_io_instr(c, &b, instr);

        return true;
}

static bool
vc4_nir_lower_io_impl(struct vc4_compile *c, nir_function_impl *impl)
{
        nir_foreach_block(impl, vc4_nir_lower_io_block, c);

        nir_metadata_preserve(impl, nir_metadata_block_index |
                              nir_metadata_dominance);

        return true;
}

void
vc4_nir_lower_io(struct vc4_compile *c)
{
        nir_foreach_overload(c->s, overload) {
                if (overload->impl)
                        vc4_nir_lower_io_impl(c, overload->impl);
        }
}