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| author | Jiang Yunhong <yunhong.jiang@intel.com> | 2011-08-30 15:50:31 +0800 |
|---|---|---|
| committer | David 'Digit' Turner <digit@google.com> | 2011-09-13 12:08:51 +0200 |
| commit | f1f1f5ff5b87d4f754572e0f05398842f0cde059 (patch) | |
| tree | 197c2e76d3970c7c32ff20196aa07290b25455f6 /hw/goldfish_nand_reg.h | |
| parent | e07ec9adfc33c0cfb2056180960d7e62fc5ea7c7 (diff) | |
| download | external_qemu-f1f1f5ff5b87d4f754572e0f05398842f0cde059.zip external_qemu-f1f1f5ff5b87d4f754572e0f05398842f0cde059.tar.gz external_qemu-f1f1f5ff5b87d4f754572e0f05398842f0cde059.tar.bz2 | |
Accelerate nand device in virtualization environment
Currently NAND device driver need 8 MMIO access for goldfish nand device access.
MMIO access is expensive in virtualization environment because each MMIO access
will cause a context switch from in-kernel module to qemu user space process.
Through introducing a new batch command, these multiple MMIO access can be
combined into one, thus improve virtualization perofrmance. The booting time in
KVM environment is reduced from 25~26 seconds to 20~21 seconds.
A kernel patch is required to utilize this new batch command.
The patched kernel will detect the batch support through a new flags in
goldfish nand device, while current kernel is not impacted.
Change-Id: Ia460b1ba3c6fde5b1fc6101bb66f8f58e46e6a78
Signed-off-by: Xin Xiaohui <xiaohui.xin@intel.com>
Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com>
Signed-off-by: Jiang Yunhong <yunhong.jiang@intel.com>
Signed-off-by: Nakajima Jun <jun.nakajima@intel.com>
Diffstat (limited to 'hw/goldfish_nand_reg.h')
| -rw-r--r-- | hw/goldfish_nand_reg.h | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/hw/goldfish_nand_reg.h b/hw/goldfish_nand_reg.h index ea91461..34d7c44 100644 --- a/hw/goldfish_nand_reg.h +++ b/hw/goldfish_nand_reg.h @@ -18,11 +18,24 @@ enum nand_cmd { NAND_CMD_WRITE, NAND_CMD_ERASE, NAND_CMD_BLOCK_BAD_GET, // NAND_RESULT is 1 if block is bad, 0 if it is not - NAND_CMD_BLOCK_BAD_SET + NAND_CMD_BLOCK_BAD_SET, + NAND_CMD_READ_BATCH, // BATCH OP extensions. + NAND_CMD_WRITE_BATCH, + NAND_CMD_ERASE_BATCH +}; + +struct batch_data{ + uint32_t dev; + uint32_t addr_low; + uint32_t addr_high; + uint32_t transfer_size; + uint32_t data; + uint32_t result; }; enum nand_dev_flags { - NAND_DEV_FLAG_READ_ONLY = 0x00000001 + NAND_DEV_FLAG_READ_ONLY = 0x00000001, + NAND_DEV_FLAG_BATCH_CAP = 0x00000002 }; #define NAND_VERSION_CURRENT (1) @@ -49,6 +62,8 @@ enum nand_reg { NAND_TRANSFER_SIZE = 0x04c, NAND_ADDR_LOW = 0x050, NAND_ADDR_HIGH = 0x054, + NAND_BATCH_ADDR_LOW = 0x058, + NAND_BATCH_ADDR_HIGH= 0x05c, }; #endif |