[MIPS] Add Goldfish target support

Basic Goldfish support for MIPS.

Also, Fix host CPU consumption when guest is idle

When the CPU is in wait state, do not wake-up if an interrupt can't be
taken. This avoid host CPU running at 100% if a device (e.g. timer) has
an interrupt line left enabled.

Also factorize code to check if interrupts are enabled in
cpu_mips_hw_interrupts_pending().

CPU consumption based on a patch from
Edgar E. Iglesias <edgar.iglesias@gmail.com>

Change-Id: Ie8371c8d0c9af1e0c8ba4cac419979350de0f5d9
Signed-off-by: yajin <yajin@mips.com.cm>
Signed-off-by: Douglas Leung <douglas@mips.com>
Signed-off-by: Bhanu Chetlapalli <bhanu@mips.com>
Signed-off-by: Chris Dearman <chris@mips.com>

1 files changed, 39 insertions, 0 deletions

diff --git a/hw/mips_pic.c b/hw/mips_pic.c
new file mode 100644
index 0000000..9d146b8
--- /dev/null
+++ b/hw/mips_pic.c
@@ -0,0 +1,39 @@
+/*
+ * MIPS CPU interrupt support.
+ *
+ */
+
+#include "hw.h"
+
+/* Stub functions for hardware that don't exist.  */
+void pic_info(void)
+{
+}
+
+void irq_info(void)
+{
+}
+
+static void mips_cpu_irq_handler(void *opaque, int irq, int level)
+{
+    CPUState *env = (CPUState *)opaque;
+    int causebit;
+
+    if (irq < 0 || 7 < irq)
+        cpu_abort(env, "mips_pic_cpu_handler: Bad interrupt line %d\n",
+                  irq);
+
+    causebit = 0x00000100 << irq;
+    if (level) {
+        env->CP0_Cause |= causebit;
+        cpu_interrupt(env, CPU_INTERRUPT_HARD);
+    } else {
+        env->CP0_Cause &= ~causebit;
+        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+    }
+}
+
+qemu_irq *mips_cpu_irq_init(CPUState *env)
+{
+    return qemu_allocate_irqs(mips_cpu_irq_handler, env, 8);
+}