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authorDavid 'Digit' Turner <digit@android.com>2010-10-20 19:07:28 +0200
committerDavid 'Digit' Turner <digit@android.com>2010-10-21 17:03:05 +0200
commitd9b6cb97a8a9e93f1bbe5351874b03f7faa81783 (patch)
treeed29b83a936789ffcc40d1170f6ff5c0653831c6 /softmmu_template.h
parent7d98eae200f294f51ada36d9b01591fc4726dd94 (diff)
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Fix linux-x86_64 build.
Fix various 64-bitness issues in the source code to make the --try-64 option work again on Linux. Note that the generated binary is not faster than its 32-bit variant when it comes to benchmarking the boot sequence. Change-Id: Iad248e033757d4cd25524a438a5dbe1cf3aca6cf
Diffstat (limited to 'softmmu_template.h')
-rw-r--r--softmmu_template.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/softmmu_template.h b/softmmu_template.h
index d140b8c..1ea4398 100644
--- a/softmmu_template.h
+++ b/softmmu_template.h
@@ -127,7 +127,7 @@ DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
/* We only validate access to the guest's user space, for which
* mmu_idx is set to 1. */
if (memcheck_instrument_mmu && mmu_idx == 1 &&
- memcheck_validate_ld(addr, DATA_SIZE, (target_ulong)GETPC())) {
+ memcheck_validate_ld(addr, DATA_SIZE, (target_ulong)(ptrdiff_t)GETPC())) {
/* Memory read breaks page boundary. So, if required, we
* must invalidate two caches in TLB. */
invalidate_cache = 2;
@@ -147,7 +147,7 @@ DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
* mmu_idx is set to 1. */
if (memcheck_instrument_mmu && mmu_idx == 1) {
invalidate_cache = memcheck_validate_ld(addr, DATA_SIZE,
- (target_ulong)GETPC());
+ (target_ulong)(ptrdiff_t)GETPC());
}
#endif // CONFIG_MEMCHECK_MMU
/* unaligned/aligned access in the same page */
@@ -303,7 +303,7 @@ void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
* mmu_idx is set to 1. */
if (memcheck_instrument_mmu && mmu_idx == 1 &&
memcheck_validate_st(addr, DATA_SIZE, (uint64_t)val,
- (target_ulong)GETPC())) {
+ (target_ulong)(ptrdiff_t)GETPC())) {
/* Memory write breaks page boundary. So, if required, we
* must invalidate two caches in TLB. */
invalidate_cache = 2;
@@ -323,7 +323,7 @@ void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
if (memcheck_instrument_mmu && mmu_idx == 1) {
invalidate_cache = memcheck_validate_st(addr, DATA_SIZE,
(uint64_t)val,
- (target_ulong)GETPC());
+ (target_ulong)(ptrdiff_t)GETPC());
}
#endif // CONFIG_MEMCHECK_MMU
/* aligned/unaligned access in the same page */