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| author | Bhanu Chetlapalli <bhanu@mips.com> | 2012-01-31 16:25:04 -0800 |
|---|---|---|
| committer | Bhanu Chetlapalli <bhanu@mips.com> | 2012-01-31 16:25:04 -0800 |
| commit | 409c7b66435cf5947cab6bf0710f92507317f22e (patch) | |
| tree | e86657ee8a018de84833634fa425c52e8404f565 /target-mips/TODO | |
| parent | 828b135787a028f6befe56470e7233329cc45e3f (diff) | |
| download | external_qemu-409c7b66435cf5947cab6bf0710f92507317f22e.zip external_qemu-409c7b66435cf5947cab6bf0710f92507317f22e.tar.gz external_qemu-409c7b66435cf5947cab6bf0710f92507317f22e.tar.bz2 | |
[MIPS] Import MIPS target support
From v0.12.5 tag at git://git.sv.gnu.org/qemu.git
CommitID: 174f225e9d62e8f3002e274e4f718bd2a967fbf4
Change-Id: I35b49a4319cee4b69cf9da4e5af1f43327e21056
Signed-off-by: Chris Dearman <chris@mips.com>
Diffstat (limited to 'target-mips/TODO')
| -rw-r--r-- | target-mips/TODO | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/target-mips/TODO b/target-mips/TODO new file mode 100644 index 0000000..4769e2a --- /dev/null +++ b/target-mips/TODO @@ -0,0 +1,53 @@ +Unsolved issues/bugs in the mips/mipsel backend +----------------------------------------------- + +General +------- +- Unimplemented ASEs: + - MIPS16 + - MDMX + - SmartMIPS + - DSP r1 + - DSP r2 +- MT ASE only partially implemented and not functional +- Shadow register support only partially implemented, + lacks set switching on interrupt/exception. +- 34K ITC not implemented. +- A general lack of documentation, especially for technical internals. + Existing documentation is x86-centric. +- Reverse endianness bit not implemented +- The TLB emulation is very inefficient: + Qemu's softmmu implements a x86-style MMU, with separate entries + for read/write/execute, a TLB index which is just a modulo of the + virtual address, and a set of TLBs for each user/kernel/supervisor + MMU mode. + MIPS has a single entry for read/write/execute and only one MMU mode. + But it is fully associative with randomized entry indices, and uses + up to 256 ASID tags as additional matching criterion (which roughly + equates to 256 MMU modes). It also has a global flag which causes + entries to match regardless of ASID. + To cope with these differences, Qemu currently flushes the TLB at + each ASID change. Using the MMU modes to implement ASIDs hinges on + implementing the global bit efficiently. +- save/restore of the CPU state is not implemented (see machine.c). + +MIPS64 +------ +- Userland emulation (both n32 and n64) not functional. + +"Generic" 4Kc system emulation +------------------------------ +- Doesn't correspond to any real hardware. Should be removed some day, + U-Boot is the last remaining user. + +PICA 61 system emulation +------------------------ +- No framebuffer support yet. + +MALTA system emulation +---------------------- +- We fake firmware support instead of doing the real thing +- Real firmware (YAMON) falls over when trying to init RAM, presumably + due to lacking system controller emulation. +- Bonito system controller not implemented +- MSC1 system controller not implemented |