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authorBhanu Chetlapalli <bhanu@mips.com>2012-05-08 17:16:03 -0700
committerBhanu Chetlapalli <bhanu@mips.com>2012-06-07 13:46:03 -0700
commit741dc13597ac064e6a48bb2a6ec069cbc1cd0dbb (patch)
tree7e0851da5038a2579bc1270e6d3d1c899703ced7 /target-mips/cpu.h
parentcf9ba9a06006592bf47ce5837188986172e1a925 (diff)
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[MIPS] Add Goldfish target support
Basic Goldfish support for MIPS. Also, Fix host CPU consumption when guest is idle When the CPU is in wait state, do not wake-up if an interrupt can't be taken. This avoid host CPU running at 100% if a device (e.g. timer) has an interrupt line left enabled. Also factorize code to check if interrupts are enabled in cpu_mips_hw_interrupts_pending(). CPU consumption based on a patch from Edgar E. Iglesias <edgar.iglesias@gmail.com> Change-Id: Ie8371c8d0c9af1e0c8ba4cac419979350de0f5d9 Signed-off-by: yajin <yajin@mips.com.cm> Signed-off-by: Douglas Leung <douglas@mips.com> Signed-off-by: Bhanu Chetlapalli <bhanu@mips.com> Signed-off-by: Chris Dearman <chris@mips.com>
Diffstat (limited to 'target-mips/cpu.h')
-rw-r--r--target-mips/cpu.h31
1 files changed, 31 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 27bdc95..7c04fbe 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -518,6 +518,37 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
env->active_tc.gpr[2] = 0;
}
+static inline int cpu_mips_hw_interrupts_pending(CPUState *env)
+{
+ int32_t pending;
+ int32_t status;
+ int r;
+
+ if (!(env->CP0_Status & (1 << CP0St_IE)) ||
+ (env->CP0_Status & (1 << CP0St_EXL)) ||
+ (env->CP0_Status & (1 << CP0St_ERL)) ||
+ (env->hflags & MIPS_HFLAG_DM)) {
+ /* Interrupts are disabled */
+ return 0;
+ }
+
+ pending = env->CP0_Cause & CP0Ca_IP_mask;
+ status = env->CP0_Status & CP0Ca_IP_mask;
+
+ if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
+ /* A MIPS configured with a vectorizing external interrupt controller
+ will feed a vector into the Cause pending lines. The core treats
+ the status lines as a vector level, not as indiviual masks. */
+ r = pending > status;
+ } else {
+ /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
+ treats the pending lines as individual interrupt lines, the status
+ lines are individual masks. */
+ r = pending & status;
+ }
+ return r;
+}
+
#include "cpu-all.h"
#include "exec-all.h"