diff options
| author | The Android Open Source Project <initial-contribution@android.com> | 2008-10-21 07:00:00 -0700 |
|---|---|---|
| committer | The Android Open Source Project <initial-contribution@android.com> | 2008-10-21 07:00:00 -0700 |
| commit | 55f4e4a5ec657a017e3bf75299ad71fd1c968dd3 (patch) | |
| tree | 550ce922ea0e125ac6a9738210ce2939bf2fe901 /target-mips | |
| parent | 413f05aaf54fa08c0ae7e997327a4f4a473c0a8d (diff) | |
| download | external_qemu-55f4e4a5ec657a017e3bf75299ad71fd1c968dd3.zip external_qemu-55f4e4a5ec657a017e3bf75299ad71fd1c968dd3.tar.gz external_qemu-55f4e4a5ec657a017e3bf75299ad71fd1c968dd3.tar.bz2 | |
Initial Contribution
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/cpu.h | 279 | ||||
| -rw-r--r-- | target-mips/exec.h | 119 | ||||
| -rw-r--r-- | target-mips/fop_template.c | 99 | ||||
| -rw-r--r-- | target-mips/helper.c | 432 | ||||
| -rw-r--r-- | target-mips/mips-defs.h | 67 | ||||
| -rw-r--r-- | target-mips/op.c | 1155 | ||||
| -rw-r--r-- | target-mips/op_helper.c | 786 | ||||
| -rw-r--r-- | target-mips/op_helper_mem.c | 141 | ||||
| -rw-r--r-- | target-mips/op_mem.c | 149 | ||||
| -rw-r--r-- | target-mips/op_template.c | 65 | ||||
| -rw-r--r-- | target-mips/translate.c | 2443 |
11 files changed, 0 insertions, 5735 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h deleted file mode 100644 index 330f9eb..0000000 --- a/target-mips/cpu.h +++ /dev/null @@ -1,279 +0,0 @@ -#if !defined (__MIPS_CPU_H__) -#define __MIPS_CPU_H__ - -#define TARGET_HAS_ICE 1 - -#include "config.h" -#include "mips-defs.h" -#include "cpu-defs.h" -#include "softfloat.h" - -// uint_fast8_t and uint_fast16_t not in <sys/int_types.h> -// XXX: move that elsewhere -#if defined(HOST_SOLARIS) && SOLARISREV < 10 -typedef unsigned char uint_fast8_t; -typedef unsigned int uint_fast16_t; -#endif - -typedef union fpr_t fpr_t; -union fpr_t { - float64 fd; /* ieee double precision */ - float32 fs[2];/* ieee single precision */ - uint64_t d; /* binary single fixed-point */ - uint32_t w[2]; /* binary single fixed-point */ -}; -/* define FP_ENDIAN_IDX to access the same location - * in the fpr_t union regardless of the host endianess - */ -#if defined(WORDS_BIGENDIAN) -# define FP_ENDIAN_IDX 1 -#else -# define FP_ENDIAN_IDX 0 -#endif - -#if defined(MIPS_USES_R4K_TLB) -typedef struct tlb_t tlb_t; -struct tlb_t { - target_ulong VPN; - target_ulong end; - target_ulong end2; - uint_fast8_t ASID; - uint_fast16_t G:1; - uint_fast16_t C0:3; - uint_fast16_t C1:3; - uint_fast16_t V0:1; - uint_fast16_t V1:1; - uint_fast16_t D0:1; - uint_fast16_t D1:1; - target_ulong PFN[2]; -}; -#endif - -typedef struct CPUMIPSState CPUMIPSState; -struct CPUMIPSState { - /* General integer registers */ - target_ulong gpr[32]; - /* Special registers */ - target_ulong PC; - uint32_t HI, LO; - uint32_t DCR; /* ? */ -#if defined(MIPS_USES_FPU) - /* Floating point registers */ - fpr_t fpr[16]; -#define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2]) -#define FPR_FD(cpu, n) (FPR(cpu, n)->fd) -#define FPR_FS(cpu, n) (FPR(cpu, n)->fs[((n) & 1) ^ FP_ENDIAN_IDX]) -#define FPR_D(cpu, n) (FPR(cpu, n)->d) -#define FPR_W(cpu, n) (FPR(cpu, n)->w[((n) & 1) ^ FP_ENDIAN_IDX]) - -#ifndef USE_HOST_FLOAT_REGS - fpr_t ft0; - fpr_t ft1; - fpr_t ft2; -#endif - float_status fp_status; - /* fpu implementation/revision register */ - uint32_t fcr0; - /* fcsr */ - uint32_t fcr31; -#define SET_FP_COND(reg) do { (reg) |= (1<<23); } while(0) -#define CLEAR_FP_COND(reg) do { (reg) &= ~(1<<23); } while(0) -#define IS_FP_COND_SET(reg) (((reg) & (1<<23)) != 0) -#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) -#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) -#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) -#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v) << 12); } while(0) -#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v) << 7); } while(0) -#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v) << 2); } while(0) -#define FP_INEXACT 1 -#define FP_UNDERFLOW 2 -#define FP_OVERFLOW 4 -#define FP_DIV0 8 -#define FP_INVALID 16 -#define FP_UNIMPLEMENTED 32 - -#endif -#if defined(MIPS_USES_R4K_TLB) - tlb_t tlb[MIPS_TLB_NB]; -#endif - uint32_t CP0_index; - uint32_t CP0_random; - uint32_t CP0_EntryLo0; - uint32_t CP0_EntryLo1; - uint32_t CP0_Context; - uint32_t CP0_PageMask; - uint32_t CP0_Wired; - uint32_t CP0_BadVAddr; - uint32_t CP0_Count; - uint32_t CP0_EntryHi; - uint32_t CP0_Compare; - uint32_t CP0_Status; -#define CP0St_CU3 31 -#define CP0St_CU2 30 -#define CP0St_CU1 29 -#define CP0St_CU0 28 -#define CP0St_RP 27 -#define CP0St_FR 26 -#define CP0St_RE 25 -#define CP0St_BEV 22 -#define CP0St_TS 21 -#define CP0St_SR 20 -#define CP0St_NMI 19 -#define CP0St_IM 8 -#define CP0St_UM 4 -#define CP0St_ERL 2 -#define CP0St_EXL 1 -#define CP0St_IE 0 - uint32_t CP0_Cause; -#define CP0Ca_IV 23 - uint32_t CP0_EPC; - uint32_t CP0_PRid; - uint32_t CP0_Config0; -#define CP0C0_M 31 -#define CP0C0_K23 28 -#define CP0C0_KU 25 -#define CP0C0_MDU 20 -#define CP0C0_MM 17 -#define CP0C0_BM 16 -#define CP0C0_BE 15 -#define CP0C0_AT 13 -#define CP0C0_AR 10 -#define CP0C0_MT 7 -#define CP0C0_K0 0 - uint32_t CP0_Config1; -#define CP0C1_MMU 25 -#define CP0C1_IS 22 -#define CP0C1_IL 19 -#define CP0C1_IA 16 -#define CP0C1_DS 13 -#define CP0C1_DL 10 -#define CP0C1_DA 7 -#define CP0C1_PC 4 -#define CP0C1_WR 3 -#define CP0C1_CA 2 -#define CP0C1_EP 1 -#define CP0C1_FP 0 - uint32_t CP0_LLAddr; - uint32_t CP0_WatchLo; - uint32_t CP0_WatchHi; - uint32_t CP0_Debug; -#define CPDB_DBD 31 -#define CP0DB_DM 30 -#define CP0DB_LSNM 28 -#define CP0DB_Doze 27 -#define CP0DB_Halt 26 -#define CP0DB_CNT 25 -#define CP0DB_IBEP 24 -#define CP0DB_DBEP 21 -#define CP0DB_IEXI 20 -#define CP0DB_VER 15 -#define CP0DB_DEC 10 -#define CP0DB_SSt 8 -#define CP0DB_DINT 5 -#define CP0DB_DIB 4 -#define CP0DB_DDBS 3 -#define CP0DB_DDBL 2 -#define CP0DB_DBp 1 -#define CP0DB_DSS 0 - uint32_t CP0_DEPC; - uint32_t CP0_TagLo; - uint32_t CP0_DataLo; - uint32_t CP0_ErrorEPC; - uint32_t CP0_DESAVE; - /* Qemu */ - struct QEMUTimer *timer; /* Internal timer */ - int interrupt_request; - jmp_buf jmp_env; - int exception_index; - int error_code; - int user_mode_only; /* user mode only simulation */ - uint32_t hflags; /* CPU State */ - /* TMASK defines different execution modes */ -#define MIPS_HFLAG_TMASK 0x007F -#define MIPS_HFLAG_MODE 0x001F /* execution modes */ -#define MIPS_HFLAG_UM 0x0001 /* user mode */ -#define MIPS_HFLAG_ERL 0x0002 /* Error mode */ -#define MIPS_HFLAG_EXL 0x0004 /* Exception mode */ -#define MIPS_HFLAG_DM 0x0008 /* Debug mode */ -#define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */ -#define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */ - /* If translation is interrupted between the branch instruction and - * the delay slot, record what type of branch it is so that we can - * resume translation properly. It might be possible to reduce - * this from three bits to two. */ -#define MIPS_HFLAG_BMASK 0x0380 -#define MIPS_HFLAG_B 0x0080 /* Unconditional branch */ -#define MIPS_HFLAG_BC 0x0100 /* Conditional branch */ -#define MIPS_HFLAG_BL 0x0180 /* Likely branch */ -#define MIPS_HFLAG_BR 0x0200 /* branch to register (can't link TB) */ - target_ulong btarget; /* Jump / branch target */ - int bcond; /* Branch condition (if needed) */ - - int halted; /* TRUE if the CPU is in suspend state */ - - CPU_COMMON -}; - -#include "cpu-all.h" - -/* Memory access type : - * may be needed for precise access rights control and precise exceptions. - */ -enum { - /* 1 bit to define user level / supervisor access */ - ACCESS_USER = 0x00, - ACCESS_SUPER = 0x01, - /* 1 bit to indicate direction */ - ACCESS_STORE = 0x02, - /* Type of instruction that generated the access */ - ACCESS_CODE = 0x10, /* Code fetch access */ - ACCESS_INT = 0x20, /* Integer load/store access */ - ACCESS_FLOAT = 0x30, /* floating point load/store access */ -}; - -/* Exceptions */ -enum { - EXCP_NONE = -1, - EXCP_RESET = 0, - EXCP_SRESET, - EXCP_DSS, - EXCP_DINT, - EXCP_NMI, - EXCP_MCHECK, - EXCP_EXT_INTERRUPT, - EXCP_DFWATCH, - EXCP_DIB, /* 8 */ - EXCP_IWATCH, - EXCP_AdEL, - EXCP_AdES, - EXCP_TLBF, - EXCP_IBE, - EXCP_DBp, - EXCP_SYSCALL, - EXCP_BREAK, /* 16 */ - EXCP_CpU, - EXCP_RI, - EXCP_OVERFLOW, - EXCP_TRAP, - EXCP_DDBS, - EXCP_DWATCH, - EXCP_LAE, - EXCP_SAE, /* 24 */ - EXCP_LTLBL, - EXCP_TLBL, - EXCP_TLBS, - EXCP_DBE, - EXCP_DDBL, - EXCP_MTCP0 = 0x104, /* mtmsr instruction: */ - /* may change privilege level */ - EXCP_BRANCH = 0x108, /* branch instruction */ - EXCP_ERET = 0x10C, /* return from interrupt */ - EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */ - EXCP_FLUSH = 0x109, -}; - -int cpu_mips_exec(CPUMIPSState *s); -CPUMIPSState *cpu_mips_init(void); -uint32_t cpu_mips_get_clock (void); - -#endif /* !defined (__MIPS_CPU_H__) */ diff --git a/target-mips/exec.h b/target-mips/exec.h deleted file mode 100644 index 93014d6..0000000 --- a/target-mips/exec.h +++ /dev/null @@ -1,119 +0,0 @@ -#if !defined(__QEMU_MIPS_EXEC_H__) -#define __QEMU_MIPS_EXEC_H__ - -//#define DEBUG_OP - -#include "mips-defs.h" -#include "dyngen-exec.h" - -register struct CPUMIPSState *env asm(AREG0); - -#if defined (USE_64BITS_REGS) -typedef int64_t host_int_t; -typedef uint64_t host_uint_t; -#else -typedef int32_t host_int_t; -typedef uint32_t host_uint_t; -#endif - -register host_uint_t T0 asm(AREG1); -register host_uint_t T1 asm(AREG2); -register host_uint_t T2 asm(AREG3); - -#if defined (USE_HOST_FLOAT_REGS) -#error "implement me." -#else -#define FDT0 (env->ft0.fd) -#define FDT1 (env->ft1.fd) -#define FDT2 (env->ft2.fd) -#define FST0 (env->ft0.fs[FP_ENDIAN_IDX]) -#define FST1 (env->ft1.fs[FP_ENDIAN_IDX]) -#define FST2 (env->ft2.fs[FP_ENDIAN_IDX]) -#define DT0 (env->ft0.d) -#define DT1 (env->ft1.d) -#define DT2 (env->ft2.d) -#define WT0 (env->ft0.w[FP_ENDIAN_IDX]) -#define WT1 (env->ft1.w[FP_ENDIAN_IDX]) -#define WT2 (env->ft2.w[FP_ENDIAN_IDX]) -#endif - -#if defined (DEBUG_OP) -#define RETURN() __asm__ __volatile__("nop"); -#else -#define RETURN() __asm__ __volatile__(""); -#endif - -#include "cpu.h" -#include "exec-all.h" - -#if !defined(CONFIG_USER_ONLY) -#include "softmmu_exec.h" -#endif /* !defined(CONFIG_USER_ONLY) */ - -static inline void env_to_regs(void) -{ -} - -static inline void regs_to_env(void) -{ -} - -#if (HOST_LONG_BITS == 32) -void do_mult (void); -void do_multu (void); -void do_madd (void); -void do_maddu (void); -void do_msub (void); -void do_msubu (void); -#endif -void do_mfc0(int reg, int sel); -void do_mtc0(int reg, int sel); -void do_tlbwi (void); -void do_tlbwr (void); -void do_tlbp (void); -void do_tlbr (void); -#ifdef MIPS_USES_FPU -void dump_fpu(CPUState *env); -void fpu_dump_state(CPUState *env, FILE *f, - int (*fpu_fprintf)(FILE *f, const char *fmt, ...), - int flags); -#endif -void dump_sc (void); -void do_lwl_raw (uint32_t); -void do_lwr_raw (uint32_t); -uint32_t do_swl_raw (uint32_t); -uint32_t do_swr_raw (uint32_t); -#if !defined(CONFIG_USER_ONLY) -void do_lwl_user (uint32_t); -void do_lwl_kernel (uint32_t); -void do_lwr_user (uint32_t); -void do_lwr_kernel (uint32_t); -uint32_t do_swl_user (uint32_t); -uint32_t do_swl_kernel (uint32_t); -uint32_t do_swr_user (uint32_t); -uint32_t do_swr_kernel (uint32_t); -#endif -void do_pmon (int function); - -void dump_sc (void); - -int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, - int is_user, int is_softmmu); -void do_interrupt (CPUState *env); - -void cpu_loop_exit(void); -void do_raise_exception_err (uint32_t exception, int error_code); -void do_raise_exception (uint32_t exception); -void do_raise_exception_direct (uint32_t exception); - -void cpu_dump_state(CPUState *env, FILE *f, - int (*cpu_fprintf)(FILE *f, const char *fmt, ...), - int flags); -void cpu_mips_irqctrl_init (void); -uint32_t cpu_mips_get_random (CPUState *env); -uint32_t cpu_mips_get_count (CPUState *env); -void cpu_mips_store_count (CPUState *env, uint32_t value); -void cpu_mips_store_compare (CPUState *env, uint32_t value); -void cpu_mips_clock_init (CPUState *env); - -#endif /* !defined(__QEMU_MIPS_EXEC_H__) */ diff --git a/target-mips/fop_template.c b/target-mips/fop_template.c deleted file mode 100644 index bc0a6e0..0000000 --- a/target-mips/fop_template.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * MIPS emulation micro-operations templates for floating point reg - * load & store for qemu. - * - * Copyright (c) 2006 Marius Groeger - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#if defined(SFREG) - -#define OP_WLOAD_FREG(treg, tregname, SFREG) \ - void glue(glue(op_load_fpr_,tregname), SFREG) (void) \ - { \ - treg = FPR_W(env, SFREG); \ - RETURN(); \ - } - -#define OP_WSTORE_FREG(treg, tregname, SFREG) \ - void glue(glue(op_store_fpr_,tregname), SFREG) (void)\ - { \ - FPR_W(env, SFREG) = treg; \ - RETURN(); \ - } - -/* WT0 = SFREG.w: op_load_fpr_WT0_fprSFREG */ -OP_WLOAD_FREG(WT0, WT0_fpr, SFREG) -/* SFREG.w = WT0: op_store_fpr_WT0_fprSFREG */ -OP_WSTORE_FREG(WT0, WT0_fpr, SFREG) - -OP_WLOAD_FREG(WT1, WT1_fpr, SFREG) -OP_WSTORE_FREG(WT1, WT1_fpr, SFREG) - -OP_WLOAD_FREG(WT2, WT2_fpr, SFREG) -OP_WSTORE_FREG(WT2, WT2_fpr, SFREG) - -#endif - -#if defined(DFREG) - -#define OP_DLOAD_FREG(treg, tregname, DFREG) \ - void glue(glue(op_load_fpr_,tregname), DFREG) (void) \ - { \ - treg = FPR_D(env, DFREG); \ - RETURN(); \ - } - -#define OP_DSTORE_FREG(treg, tregname, DFREG) \ - void glue(glue(op_store_fpr_,tregname), DFREG) (void)\ - { \ - FPR_D(env, DFREG) = treg; \ - RETURN(); \ - } - -OP_DLOAD_FREG(DT0, DT0_fpr, DFREG) -OP_DSTORE_FREG(DT0, DT0_fpr, DFREG) - -OP_DLOAD_FREG(DT1, DT1_fpr, DFREG) -OP_DSTORE_FREG(DT1, DT1_fpr, DFREG) - -OP_DLOAD_FREG(DT2, DT2_fpr, DFREG) -OP_DSTORE_FREG(DT2, DT2_fpr, DFREG) - -#endif - -#if defined (FTN) - -#define SET_RESET(treg, tregname) \ - void glue(op_set, tregname)(void) \ - { \ - treg = PARAM1; \ - RETURN(); \ - } \ - void glue(op_reset, tregname)(void) \ - { \ - treg = 0; \ - RETURN(); \ - } \ - -SET_RESET(WT0, _WT0) -SET_RESET(WT1, _WT1) -SET_RESET(WT2, _WT2) -SET_RESET(DT0, _DT0) -SET_RESET(DT1, _DT1) -SET_RESET(DT2, _DT2) - -#endif diff --git a/target-mips/helper.c b/target-mips/helper.c deleted file mode 100644 index 9c8e4f6..0000000 --- a/target-mips/helper.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * MIPS emulation helpers for qemu. - * - * Copyright (c) 2004-2005 Jocelyn Mayer - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include <stdarg.h> -#include <stdlib.h> -#include <stdio.h> -#include <string.h> -#include <inttypes.h> -#include <signal.h> -#include <assert.h> - -#include "cpu.h" -#include "exec-all.h" - -enum { - TLBRET_DIRTY = -4, - TLBRET_INVALID = -3, - TLBRET_NOMATCH = -2, - TLBRET_BADADDR = -1, - TLBRET_MATCH = 0 -}; - -/* MIPS32 4K MMU emulation */ -#ifdef MIPS_USES_R4K_TLB -static int map_address (CPUState *env, target_ulong *physical, int *prot, - target_ulong address, int rw, int access_type) -{ - target_ulong tag = address & (TARGET_PAGE_MASK << 1); - uint8_t ASID = env->CP0_EntryHi & 0xFF; - tlb_t *tlb; - int i, n; - - for (i = 0; i < MIPS_TLB_NB; i++) { - tlb = &env->tlb[i]; - /* Check ASID, virtual page number & size */ - if ((tlb->G == 1 || tlb->ASID == ASID) && - tlb->VPN == tag && address < tlb->end2) { - /* TLB match */ - n = (address >> TARGET_PAGE_BITS) & 1; - /* Check access rights */ - if (!(n ? tlb->V1 : tlb->V0)) - return TLBRET_INVALID; - if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { - *physical = tlb->PFN[n] | (address & ~TARGET_PAGE_MASK); - *prot = PAGE_READ; - if (n ? tlb->D1 : tlb->D0) - *prot |= PAGE_WRITE; - return TLBRET_MATCH; - } - return TLBRET_DIRTY; - } - } - return TLBRET_NOMATCH; -} -#endif - -static int get_physical_address (CPUState *env, target_ulong *physical, - int *prot, target_ulong address, - int rw, int access_type) -{ - /* User mode can only access useg */ - int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM; - int ret = TLBRET_MATCH; - -#if 0 - if (logfile) { - fprintf(logfile, "user mode %d h %08x\n", - user_mode, env->hflags); - } -#endif - if (user_mode && address > 0x7FFFFFFFUL) - return TLBRET_BADADDR; - if (address < 0x80000000UL) { - if (!(env->hflags & MIPS_HFLAG_ERL)) { -#ifdef MIPS_USES_R4K_TLB - ret = map_address(env, physical, prot, address, rw, access_type); -#else - *physical = address + 0x40000000UL; - *prot = PAGE_READ | PAGE_WRITE; -#endif - } else { - *physical = address; - *prot = PAGE_READ | PAGE_WRITE; - } - } else if (address < 0xA0000000UL) { - /* kseg0 */ - /* XXX: check supervisor mode */ - *physical = address - 0x80000000UL; - *prot = PAGE_READ | PAGE_WRITE; - } else if (address < 0xC0000000UL) { - /* kseg1 */ - /* XXX: check supervisor mode */ - *physical = address - 0xA0000000UL; - *prot = PAGE_READ | PAGE_WRITE; - } else if (address < 0xE0000000UL) { - /* kseg2 */ -#ifdef MIPS_USES_R4K_TLB - ret = map_address(env, physical, prot, address, rw, access_type); -#else - *physical = address; - *prot = PAGE_READ | PAGE_WRITE; -#endif - } else { - /* kseg3 */ - /* XXX: check supervisor mode */ - /* XXX: debug segment is not emulated */ -#ifdef MIPS_USES_R4K_TLB - ret = map_address(env, physical, prot, address, rw, access_type); -#else - *physical = address; - *prot = PAGE_READ | PAGE_WRITE; -#endif - } -#if 0 - if (logfile) { - fprintf(logfile, "%08x %d %d => %08x %d (%d)\n", address, rw, - access_type, *physical, *prot, ret); - } -#endif - - return ret; -} - -#if defined(CONFIG_USER_ONLY) -target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) -{ - return addr; -} -#else -target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) -{ - target_ulong phys_addr; - int prot; - - if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) - return -1; - return phys_addr; -} - -void cpu_mips_init_mmu (CPUState *env) -{ -} -#endif /* !defined(CONFIG_USER_ONLY) */ - -int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, - int is_user, int is_softmmu) -{ - target_ulong physical; - int prot; - int exception = 0, error_code = 0; - int access_type; - int ret = 0; - - if (logfile) { -#if 0 - cpu_dump_state(env, logfile, fprintf, 0); -#endif - fprintf(logfile, "%s pc %08x ad %08x rw %d is_user %d smmu %d\n", - __func__, env->PC, address, rw, is_user, is_softmmu); - } - - rw &= 1; - - /* data access */ - /* XXX: put correct access by using cpu_restore_state() - correctly */ - access_type = ACCESS_INT; - if (env->user_mode_only) { - /* user mode only emulation */ - ret = TLBRET_NOMATCH; - goto do_fault; - } - ret = get_physical_address(env, &physical, &prot, - address, rw, access_type); - if (logfile) { - fprintf(logfile, "%s address=%08x ret %d physical %08x prot %d\n", - __func__, address, ret, physical, prot); - } - if (ret == TLBRET_MATCH) { - ret = tlb_set_page(env, address & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot, - is_user, is_softmmu); - } else if (ret < 0) { - do_fault: - switch (ret) { - default: - case TLBRET_BADADDR: - /* Reference to kernel address from user mode or supervisor mode */ - /* Reference to supervisor address from user mode */ - if (rw) - exception = EXCP_AdES; - else - exception = EXCP_AdEL; - break; - case TLBRET_NOMATCH: - /* No TLB match for a mapped address */ - if (rw) - exception = EXCP_TLBS; - else - exception = EXCP_TLBL; - error_code = 1; - break; - case TLBRET_INVALID: - /* TLB match with no valid bit */ - if (rw) - exception = EXCP_TLBS; - else - exception = EXCP_TLBL; - break; - case TLBRET_DIRTY: - /* TLB match but 'D' bit is cleared */ - exception = EXCP_LTLBL; - break; - - } - /* Raise exception */ - env->CP0_BadVAddr = address; - env->CP0_Context = (env->CP0_Context & 0xff800000) | - ((address >> 9) & 0x007ffff0); - env->CP0_EntryHi = - (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); - env->exception_index = exception; - env->error_code = error_code; - ret = 1; - } - - return ret; -} - -void do_interrupt (CPUState *env) -{ - target_ulong pc, offset; - int cause = -1; - - if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) { - fprintf(logfile, "%s enter: PC %08x EPC %08x cause %d excp %d\n", - __func__, env->PC, env->CP0_EPC, cause, env->exception_index); - } - if (env->exception_index == EXCP_EXT_INTERRUPT && - (env->hflags & MIPS_HFLAG_DM)) - env->exception_index = EXCP_DINT; - offset = 0x180; - switch (env->exception_index) { - case EXCP_DSS: - env->CP0_Debug |= 1 << CP0DB_DSS; - /* Debug single step cannot be raised inside a delay slot and - * resume will always occur on the next instruction - * (but we assume the pc has always been updated during - * code translation). - */ - env->CP0_DEPC = env->PC; - goto enter_debug_mode; - case EXCP_DINT: - env->CP0_Debug |= 1 << CP0DB_DINT; - goto set_DEPC; - case EXCP_DIB: - env->CP0_Debug |= 1 << CP0DB_DIB; - goto set_DEPC; - case EXCP_DBp: - env->CP0_Debug |= 1 << CP0DB_DBp; - goto set_DEPC; - case EXCP_DDBS: - env->CP0_Debug |= 1 << CP0DB_DDBS; - goto set_DEPC; - case EXCP_DDBL: - env->CP0_Debug |= 1 << CP0DB_DDBL; - goto set_DEPC; - set_DEPC: - if (env->hflags & MIPS_HFLAG_BMASK) { - /* If the exception was raised from a delay slot, - * come back to the jump - */ - env->CP0_DEPC = env->PC - 4; - env->hflags &= ~MIPS_HFLAG_BMASK; - } else { - env->CP0_DEPC = env->PC; - } - enter_debug_mode: - env->hflags |= MIPS_HFLAG_DM; - /* EJTAG probe trap enable is not implemented... */ - pc = 0xBFC00480; - break; - case EXCP_RESET: -#ifdef MIPS_USES_R4K_TLB - env->CP0_random = MIPS_TLB_NB - 1; -#endif - env->CP0_Wired = 0; - env->CP0_Config0 = MIPS_CONFIG0; -#if defined (MIPS_CONFIG1) - env->CP0_Config1 = MIPS_CONFIG1; -#endif -#if defined (MIPS_CONFIG2) - env->CP0_Config2 = MIPS_CONFIG2; -#endif -#if defined (MIPS_CONFIG3) - env->CP0_Config3 = MIPS_CONFIG3; -#endif - env->CP0_WatchLo = 0; - env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV); - goto set_error_EPC; - case EXCP_SRESET: - env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) | - (1 << CP0St_SR); - env->CP0_WatchLo = 0; - goto set_error_EPC; - case EXCP_NMI: - env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) | - (1 << CP0St_NMI); - set_error_EPC: - if (env->hflags & MIPS_HFLAG_BMASK) { - /* If the exception was raised from a delay slot, - * come back to the jump - */ - env->CP0_ErrorEPC = env->PC - 4; - env->hflags &= ~MIPS_HFLAG_BMASK; - } else { - env->CP0_ErrorEPC = env->PC; - } - env->hflags |= MIPS_HFLAG_ERL; - env->CP0_Status |= (1 << CP0St_ERL); - pc = 0xBFC00000; - break; - case EXCP_MCHECK: - cause = 24; - goto set_EPC; - case EXCP_EXT_INTERRUPT: - cause = 0; - if (env->CP0_Cause & (1 << CP0Ca_IV)) - offset = 0x200; - goto set_EPC; - case EXCP_DWATCH: - cause = 23; - /* XXX: TODO: manage defered watch exceptions */ - goto set_EPC; - case EXCP_AdEL: - case EXCP_AdES: - cause = 4; - goto set_EPC; - case EXCP_TLBL: - cause = 2; - if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL)) - offset = 0x000; - goto set_EPC; - case EXCP_IBE: - cause = 6; - goto set_EPC; - case EXCP_DBE: - cause = 7; - goto set_EPC; - case EXCP_SYSCALL: - cause = 8; - goto set_EPC; - case EXCP_BREAK: - cause = 9; - goto set_EPC; - case EXCP_RI: - cause = 10; - goto set_EPC; - case EXCP_CpU: - cause = 11; - env->CP0_Cause = (env->CP0_Cause & ~0x03000000) | (env->error_code << 28); - goto set_EPC; - case EXCP_OVERFLOW: - cause = 12; - goto set_EPC; - case EXCP_TRAP: - cause = 13; - goto set_EPC; - case EXCP_LTLBL: - cause = 1; - goto set_EPC; - case EXCP_TLBS: - cause = 3; - if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL)) - offset = 0x000; - goto set_EPC; - set_EPC: - if (env->CP0_Status & (1 << CP0St_BEV)) { - pc = 0xBFC00200; - } else { - pc = 0x80000000; - } - env->hflags |= MIPS_HFLAG_EXL; - env->CP0_Status |= (1 << CP0St_EXL); - pc += offset; - env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2); - if (env->hflags & MIPS_HFLAG_BMASK) { - /* If the exception was raised from a delay slot, - * come back to the jump - */ - env->CP0_EPC = env->PC - 4; - env->CP0_Cause |= 0x80000000; - env->hflags &= ~MIPS_HFLAG_BMASK; - } else { - env->CP0_EPC = env->PC; - env->CP0_Cause &= ~0x80000000; - } - break; - default: - if (logfile) { - fprintf(logfile, "Invalid MIPS exception %d. Exiting\n", - env->exception_index); - } - printf("Invalid MIPS exception %d. Exiting\n", env->exception_index); - exit(1); - } - env->PC = pc; - if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) { - fprintf(logfile, "%s: PC %08x EPC %08x cause %d excp %d\n" - " S %08x C %08x A %08x D %08x\n", - __func__, env->PC, env->CP0_EPC, cause, env->exception_index, - env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, - env->CP0_DEPC); - } - env->exception_index = EXCP_NONE; -} diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h deleted file mode 100644 index c6f9e9c..0000000 --- a/target-mips/mips-defs.h +++ /dev/null @@ -1,67 +0,0 @@ -#if !defined (__QEMU_MIPS_DEFS_H__) -#define __QEMU_MIPS_DEFS_H__ - -/* If we want to use 64 bits host regs... */ -//#define USE_64BITS_REGS -/* If we want to use host float regs... */ -//#define USE_HOST_FLOAT_REGS - -#define MIPS_R4Kc 0x00018000 -#define MIPS_R4Kp 0x00018300 - -/* Emulate MIPS R4Kc for now */ -#define MIPS_CPU MIPS_R4Kc - -#if (MIPS_CPU == MIPS_R4Kc) -/* 32 bits target */ -#define TARGET_LONG_BITS 32 -/* real pages are variable size... */ -#define TARGET_PAGE_BITS 12 -/* Uses MIPS R4Kx enhancements to MIPS32 architecture */ -#define MIPS_USES_R4K_EXT -/* Uses MIPS R4Kc TLB model */ -#define MIPS_USES_R4K_TLB -#define MIPS_TLB_NB 16 -/* basic FPU register support */ -#define MIPS_USES_FPU 1 -/* Define a implementation number of 1. - * Define a major version 1, minor version 0. - */ -#define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0) -/* Have config1, uses TLB */ -#define MIPS_CONFIG0_1 \ -((1 << CP0C0_M) | (0 << CP0C0_K23) | (0 << CP0C0_KU) | \ - (1 << CP0C0_MT) | (2 << CP0C0_K0)) -#ifdef TARGET_WORDS_BIGENDIAN -#define MIPS_CONFIG0 (MIPS_CONFIG0_1 | (1 << CP0C0_BE)) -#else -#define MIPS_CONFIG0 MIPS_CONFIG0_1 -#endif -/* 16 TLBs, 64 sets Icache, 16 bytes Icache line, 2-way Icache, - * 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache, - * no performance counters, watch registers present, no code compression, - * EJTAG present, FPU enable bit depending on MIPS_USES_FPU - */ -#define MIPS_CONFIG1 \ -((15 << CP0C1_MMU) | \ - (0x000 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x01 << CP0C1_IA) | \ - (0x000 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x01 << CP0C1_DA) | \ - (0 << CP0C1_PC) | (1 << CP0C1_WR) | (0 << CP0C1_CA) | \ - (1 << CP0C1_EP) | (MIPS_USES_FPU << CP0C1_FP)) -#elif (MIPS_CPU == MIPS_R4Kp) -/* 32 bits target */ -#define TARGET_LONG_BITS 32 -/* real pages are variable size... */ -#define TARGET_PAGE_BITS 12 -/* Uses MIPS R4Kx enhancements to MIPS32 architecture */ -#define MIPS_USES_R4K_EXT -/* Uses MIPS R4Km FPM MMU model */ -#define MIPS_USES_R4K_FPM -#else -#error "MIPS CPU not defined" -/* Remainder for other flags */ -//#define TARGET_MIPS64 -//#define MIPS_USES_FPU -#endif - -#endif /* !defined (__QEMU_MIPS_DEFS_H__) */ diff --git a/target-mips/op.c b/target-mips/op.c deleted file mode 100644 index 4575517..0000000 --- a/target-mips/op.c +++ /dev/null @@ -1,1155 +0,0 @@ -/* - * MIPS emulation micro-operations for qemu. - * - * Copyright (c) 2004-2005 Jocelyn Mayer - * Copyright (c) 2006 Marius Groeger (FPU operations) - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include "config.h" -#include "exec.h" - -#ifndef CALL_FROM_TB0 -#define CALL_FROM_TB0(func) func(); -#endif -#ifndef CALL_FROM_TB1 -#define CALL_FROM_TB1(func, arg0) func(arg0); -#endif -#ifndef CALL_FROM_TB1_CONST16 -#define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0); -#endif -#ifndef CALL_FROM_TB2 -#define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1); -#endif -#ifndef CALL_FROM_TB2_CONST16 -#define CALL_FROM_TB2_CONST16(func, arg0, arg1) \ -CALL_FROM_TB2(func, arg0, arg1); -#endif -#ifndef CALL_FROM_TB3 -#define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2); -#endif -#ifndef CALL_FROM_TB4 -#define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \ - func(arg0, arg1, arg2, arg3); -#endif - -#define REG 1 -#include "op_template.c" -#undef REG -#define REG 2 -#include "op_template.c" -#undef REG -#define REG 3 -#include "op_template.c" -#undef REG -#define REG 4 -#include "op_template.c" -#undef REG -#define REG 5 -#include "op_template.c" -#undef REG -#define REG 6 -#include "op_template.c" -#undef REG -#define REG 7 -#include "op_template.c" -#undef REG -#define REG 8 -#include "op_template.c" -#undef REG -#define REG 9 -#include "op_template.c" -#undef REG -#define REG 10 -#include "op_template.c" -#undef REG -#define REG 11 -#include "op_template.c" -#undef REG -#define REG 12 -#include "op_template.c" -#undef REG -#define REG 13 -#include "op_template.c" -#undef REG -#define REG 14 -#include "op_template.c" -#undef REG -#define REG 15 -#include "op_template.c" -#undef REG -#define REG 16 -#include "op_template.c" -#undef REG -#define REG 17 -#include "op_template.c" -#undef REG -#define REG 18 -#include "op_template.c" -#undef REG -#define REG 19 -#include "op_template.c" -#undef REG -#define REG 20 -#include "op_template.c" -#undef REG -#define REG 21 -#include "op_template.c" -#undef REG -#define REG 22 -#include "op_template.c" -#undef REG -#define REG 23 -#include "op_template.c" -#undef REG -#define REG 24 -#include "op_template.c" -#undef REG -#define REG 25 -#include "op_template.c" -#undef REG -#define REG 26 -#include "op_template.c" -#undef REG -#define REG 27 -#include "op_template.c" -#undef REG -#define REG 28 -#include "op_template.c" -#undef REG -#define REG 29 -#include "op_template.c" -#undef REG -#define REG 30 -#include "op_template.c" -#undef REG -#define REG 31 -#include "op_template.c" -#undef REG - -#define TN T0 -#include "op_template.c" -#undef TN -#define TN T1 -#include "op_template.c" -#undef TN -#define TN T2 -#include "op_template.c" -#undef TN - -#ifdef MIPS_USES_FPU - -#define SFREG 0 -#define DFREG 0 -#include "fop_template.c" -#undef SFREG -#undef DFREG -#define SFREG 1 -#include "fop_template.c" -#undef SFREG -#define SFREG 2 -#define DFREG 2 -#include "fop_template.c" -#undef SFREG -#undef DFREG -#define SFREG 3 -#include "fop_template.c" -#undef SFREG -#define SFREG 4 -#define DFREG 4 -#include "fop_template.c" -#undef SFREG -#undef DFREG -#define SFREG 5 -#include "fop_template.c" -#undef SFREG -#define SFREG 6 -#define DFREG 6 -#include "fop_template.c" -#undef SFREG -#undef DFREG -#define SFREG 7 -#include "fop_template.c" -#undef SFREG -#define SFREG 8 -#define DFREG 8 -#include "fop_template.c" -#undef SFREG -#undef DFREG -#define SFREG 9 -#include "fop_template.c" -#undef SFREG -#define SFREG 10 -#define DFREG 10 -#include "fop_template.c" -#undef SFREG -#undef DFREG -#define SFREG 11 -#include "fop_template.c" -#undef SFREG -#define SFREG 12 -#define DFREG 12 -#include "fop_template.c" -#undef SFREG -#undef DFREG -#define SFREG 13 -#include "fop_template.c" -#undef SFREG -#define SFREG 14 -#define DFREG 14 -#include "fop_template.c" -#undef SFREG -#undef DFREG -#define SFREG 15 -#include "fop_template.c" -#undef SFREG -#define SFREG 16 -#define DFREG 16 -#include "fop_template.c" -#undef SFREG -#undef DFREG -#define SFREG 17 -#include "fop_template.c" -#undef SFREG -#define SFREG 18 -#define DFREG 18 -#include "fop_template.c" -#undef SFREG -#undef DFREG -#define SFREG 19 -#include "fop_template.c" -#undef SFREG -#define SFREG 20 -#define DFREG 20 -#include "fop_template.c" -#undef SFREG -#undef DFREG -#define SFREG 21 -#include "fop_template.c" -#undef SFREG -#define SFREG 22 -#define DFREG 22 -#include "fop_template.c" -#undef SFREG -#undef DFREG -#define SFREG 23 -#include "fop_template.c" -#undef SFREG -#define SFREG 24 -#define DFREG 24 -#include "fop_template.c" -#undef SFREG -#undef DFREG -#define SFREG 25 -#include "fop_template.c" -#undef SFREG -#define SFREG 26 -#define DFREG 26 -#include "fop_template.c" -#undef SFREG -#undef DFREG -#define SFREG 27 -#include "fop_template.c" -#undef SFREG -#define SFREG 28 -#define DFREG 28 -#include "fop_template.c" -#undef SFREG -#undef DFREG -#define SFREG 29 -#include "fop_template.c" -#undef SFREG -#define SFREG 30 -#define DFREG 30 -#include "fop_template.c" -#undef SFREG -#undef DFREG -#define SFREG 31 -#include "fop_template.c" -#undef SFREG - -#define FTN -#include "fop_template.c" -#undef FTN - -#endif - -void op_dup_T0 (void) -{ - T2 = T0; - RETURN(); -} - -void op_load_HI (void) -{ - T0 = env->HI; - RETURN(); -} - -void op_store_HI (void) -{ - env->HI = T0; - RETURN(); -} - -void op_load_LO (void) -{ - T0 = env->LO; - RETURN(); -} - -void op_store_LO (void) -{ - env->LO = T0; - RETURN(); -} - -/* Load and store */ -#define MEMSUFFIX _raw -#include "op_mem.c" -#undef MEMSUFFIX -#if !defined(CONFIG_USER_ONLY) -#define MEMSUFFIX _user -#include "op_mem.c" -#undef MEMSUFFIX - -#define MEMSUFFIX _kernel -#include "op_mem.c" -#undef MEMSUFFIX -#endif - -/* Arithmetic */ -void op_add (void) -{ - T0 += T1; - RETURN(); -} - -void op_addo (void) -{ - target_ulong tmp; - - tmp = T0; - T0 += T1; - if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) { - /* operands of same sign, result different sign */ - CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW); - } - RETURN(); -} - -void op_sub (void) -{ - T0 -= T1; - RETURN(); -} - -void op_subo (void) -{ - target_ulong tmp; - - tmp = T0; - T0 = (int32_t)T0 - (int32_t)T1; - if (((tmp ^ T1) & (tmp ^ T0)) >> 31) { - /* operands of different sign, first operand and result different sign */ - CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW); - } - RETURN(); -} - -void op_mul (void) -{ - T0 = (int32_t)T0 * (int32_t)T1; - RETURN(); -} - -void op_div (void) -{ - if (T1 != 0) { - env->LO = (int32_t)T0 / (int32_t)T1; - env->HI = (int32_t)T0 % (int32_t)T1; - } - RETURN(); -} - -void op_divu (void) -{ - if (T1 != 0) { - env->LO = T0 / T1; - env->HI = T0 % T1; - } - RETURN(); -} - -/* Logical */ -void op_and (void) -{ - T0 &= T1; - RETURN(); -} - -void op_nor (void) -{ - T0 = ~(T0 | T1); - RETURN(); -} - -void op_or (void) -{ - T0 |= T1; - RETURN(); -} - -void op_xor (void) -{ - T0 ^= T1; - RETURN(); -} - -void op_sll (void) -{ - T0 = T0 << T1; - RETURN(); -} - -void op_sra (void) -{ - T0 = (int32_t)T0 >> T1; - RETURN(); -} - -void op_srl (void) -{ - T0 = T0 >> T1; - RETURN(); -} - -void op_sllv (void) -{ - T0 = T1 << (T0 & 0x1F); - RETURN(); -} - -void op_srav (void) -{ - T0 = (int32_t)T1 >> (T0 & 0x1F); - RETURN(); -} - -void op_srlv (void) -{ - T0 = T1 >> (T0 & 0x1F); - RETURN(); -} - -void op_clo (void) -{ - int n; - - if (T0 == (target_ulong)-1) { - T0 = 32; - } else { - for (n = 0; n < 32; n++) { - if (!(T0 & (1 << 31))) - break; - T0 = T0 << 1; - } - T0 = n; - } - RETURN(); -} - -void op_clz (void) -{ - int n; - - if (T0 == 0) { - T0 = 32; - } else { - for (n = 0; n < 32; n++) { - if (T0 & (1 << 31)) - break; - T0 = T0 << 1; - } - T0 = n; - } - RETURN(); -} - -/* 64 bits arithmetic */ -#if (HOST_LONG_BITS == 64) -static inline uint64_t get_HILO (void) -{ - return ((uint64_t)env->HI << 32) | (uint64_t)env->LO; -} - -static inline void set_HILO (uint64_t HILO) -{ - env->LO = HILO & 0xFFFFFFFF; - env->HI = HILO >> 32; -} - -void op_mult (void) -{ - set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); - RETURN(); -} - -void op_multu (void) -{ - set_HILO((uint64_t)T0 * (uint64_t)T1); - RETURN(); -} - -void op_madd (void) -{ - int64_t tmp; - - tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); - set_HILO((int64_t)get_HILO() + tmp); - RETURN(); -} - -void op_maddu (void) -{ - uint64_t tmp; - - tmp = ((uint64_t)T0 * (uint64_t)T1); - set_HILO(get_HILO() + tmp); - RETURN(); -} - -void op_msub (void) -{ - int64_t tmp; - - tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); - set_HILO((int64_t)get_HILO() - tmp); - RETURN(); -} - -void op_msubu (void) -{ - uint64_t tmp; - - tmp = ((uint64_t)T0 * (uint64_t)T1); - set_HILO(get_HILO() - tmp); - RETURN(); -} -#else -void op_mult (void) -{ - CALL_FROM_TB0(do_mult); - RETURN(); -} - -void op_multu (void) -{ - CALL_FROM_TB0(do_multu); - RETURN(); -} - -void op_madd (void) -{ - CALL_FROM_TB0(do_madd); - RETURN(); -} - -void op_maddu (void) -{ - CALL_FROM_TB0(do_maddu); - RETURN(); -} - -void op_msub (void) -{ - CALL_FROM_TB0(do_msub); - RETURN(); -} - -void op_msubu (void) -{ - CALL_FROM_TB0(do_msubu); - RETURN(); -} -#endif - -/* Conditional moves */ -void op_movn (void) -{ - if (T1 != 0) - env->gpr[PARAM1] = T0; - RETURN(); -} - -void op_movz (void) -{ - if (T1 == 0) - env->gpr[PARAM1] = T0; - RETURN(); -} - -/* Tests */ -#define OP_COND(name, cond) \ -void glue(op_, name) (void) \ -{ \ - if (cond) { \ - T0 = 1; \ - } else { \ - T0 = 0; \ - } \ - RETURN(); \ -} - -OP_COND(eq, T0 == T1); -OP_COND(ne, T0 != T1); -OP_COND(ge, (int32_t)T0 >= (int32_t)T1); -OP_COND(geu, T0 >= T1); -OP_COND(lt, (int32_t)T0 < (int32_t)T1); -OP_COND(ltu, T0 < T1); -OP_COND(gez, (int32_t)T0 >= 0); -OP_COND(gtz, (int32_t)T0 > 0); -OP_COND(lez, (int32_t)T0 <= 0); -OP_COND(ltz, (int32_t)T0 < 0); - -/* Branchs */ -//#undef USE_DIRECT_JUMP - -void OPPROTO op_goto_tb0(void) -{ - GOTO_TB(op_goto_tb0, PARAM1, 0); -} - -void OPPROTO op_goto_tb1(void) -{ - GOTO_TB(op_goto_tb1, PARAM1, 1); -} - -/* Branch to register */ -void op_save_breg_target (void) -{ - env->btarget = T2; -} - -void op_restore_breg_target (void) -{ - T2 = env->btarget; -} - -void op_breg (void) -{ - env->PC = T2; - RETURN(); -} - -void op_save_btarget (void) -{ - env->btarget = PARAM1; - RETURN(); -} - -/* Conditional branch */ -void op_set_bcond (void) -{ - T2 = T0; - RETURN(); -} - -void op_save_bcond (void) -{ - env->bcond = T2; - RETURN(); -} - -void op_restore_bcond (void) -{ - T2 = env->bcond; - RETURN(); -} - -void op_jnz_T2 (void) -{ - if (T2) - GOTO_LABEL_PARAM(1); - RETURN(); -} - -/* CP0 functions */ -void op_mfc0 (void) -{ - CALL_FROM_TB2(do_mfc0, PARAM1, PARAM2); - RETURN(); -} - -void op_mtc0 (void) -{ - CALL_FROM_TB2(do_mtc0, PARAM1, PARAM2); - RETURN(); -} - -#ifdef MIPS_USES_FPU - -#if 0 -# define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env) -#else -# define DEBUG_FPU_STATE() do { } while(0) -#endif - -void op_cp1_enabled(void) -{ - if (!(env->CP0_Status & (1 << CP0St_CU1))) { - CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 1); - } - RETURN(); -} - -/* CP1 functions */ -void op_cfc1 (void) -{ - if (T1 == 0) { - T0 = env->fcr0; - } - else { - /* fetch fcr31, masking unused bits */ - T0 = env->fcr31 & 0x0183FFFF; - } - DEBUG_FPU_STATE(); - RETURN(); -} - -/* convert MIPS rounding mode in FCR31 to IEEE library */ -unsigned int ieee_rm[] = { - float_round_nearest_even, - float_round_to_zero, - float_round_up, - float_round_down -}; - -#define RESTORE_ROUNDING_MODE \ - set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status) - -void op_ctc1 (void) -{ - if (T1 == 0) { - /* XXX should this throw an exception? - * don't write to FCR0. - * env->fcr0 = T0; - */ - } - else { - /* store new fcr31, masking unused bits */ - env->fcr31 = T0 & 0x0183FFFF; - - /* set rounding mode */ - RESTORE_ROUNDING_MODE; - -#ifndef CONFIG_SOFTFLOAT - /* no floating point exception for native float */ - SET_FP_ENABLE(env->fcr31, 0); -#endif - } - DEBUG_FPU_STATE(); - RETURN(); -} - -void op_mfc1 (void) -{ - T0 = WT0; - DEBUG_FPU_STATE(); - RETURN(); -} - -void op_mtc1 (void) -{ - WT0 = T0; - DEBUG_FPU_STATE(); - RETURN(); -} - -/* Float support. - Single precition routines have a "s" suffix, double precision a - "d" suffix. */ - -#define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void) - -FLOAT_OP(cvtd, w) -{ - FDT2 = int32_to_float64(WT0, &env->fp_status); - DEBUG_FPU_STATE(); - RETURN(); -} -FLOAT_OP(cvts, w) -{ - FST2 = int32_to_float32(WT0, &env->fp_status); - DEBUG_FPU_STATE(); - RETURN(); -} -FLOAT_OP(cvtw, s) -{ - WT2 = float32_to_int32(FST0, &env->fp_status); - DEBUG_FPU_STATE(); - RETURN(); -} -FLOAT_OP(cvtw, d) -{ - WT2 = float64_to_int32(FDT0, &env->fp_status); - DEBUG_FPU_STATE(); - RETURN(); -} - -FLOAT_OP(roundw, d) -{ - set_float_rounding_mode(float_round_nearest_even, &env->fp_status); - WT2 = float64_round_to_int(FDT0, &env->fp_status); - RESTORE_ROUNDING_MODE; - - DEBUG_FPU_STATE(); - RETURN(); -} -FLOAT_OP(roundw, s) -{ - set_float_rounding_mode(float_round_nearest_even, &env->fp_status); - WT2 = float32_round_to_int(FST0, &env->fp_status); - RESTORE_ROUNDING_MODE; - DEBUG_FPU_STATE(); - RETURN(); -} - -FLOAT_OP(truncw, d) -{ - WT2 = float64_to_int32_round_to_zero(FDT0, &env->fp_status); - DEBUG_FPU_STATE(); - RETURN(); -} -FLOAT_OP(truncw, s) -{ - WT2 = float32_to_int32_round_to_zero(FST0, &env->fp_status); - DEBUG_FPU_STATE(); - RETURN(); -} - -FLOAT_OP(ceilw, d) -{ - set_float_rounding_mode(float_round_up, &env->fp_status); - WT2 = float64_round_to_int(FDT0, &env->fp_status); - RESTORE_ROUNDING_MODE; - - DEBUG_FPU_STATE(); - RETURN(); -} -FLOAT_OP(ceilw, s) -{ - set_float_rounding_mode(float_round_up, &env->fp_status); - WT2 = float32_round_to_int(FST0, &env->fp_status); - RESTORE_ROUNDING_MODE; - DEBUG_FPU_STATE(); - RETURN(); -} - -FLOAT_OP(floorw, d) -{ - set_float_rounding_mode(float_round_down, &env->fp_status); - WT2 = float64_round_to_int(FDT0, &env->fp_status); - RESTORE_ROUNDING_MODE; - - DEBUG_FPU_STATE(); - RETURN(); -} -FLOAT_OP(floorw, s) -{ - set_float_rounding_mode(float_round_down, &env->fp_status); - WT2 = float32_round_to_int(FST0, &env->fp_status); - RESTORE_ROUNDING_MODE; - DEBUG_FPU_STATE(); - RETURN(); -} - -/* binary operations */ -#define FLOAT_BINOP(name) \ -FLOAT_OP(name, d) \ -{ \ - FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status); \ - DEBUG_FPU_STATE(); \ -} \ -FLOAT_OP(name, s) \ -{ \ - FST2 = float32_ ## name (FST0, FST1, &env->fp_status); \ - DEBUG_FPU_STATE(); \ -} -FLOAT_BINOP(add) -FLOAT_BINOP(sub) -FLOAT_BINOP(mul) -FLOAT_BINOP(div) -#undef FLOAT_BINOP - -/* unary operations, modifying fp status */ -#define FLOAT_UNOP(name) \ -FLOAT_OP(name, d) \ -{ \ - FDT2 = float64_ ## name(FDT0, &env->fp_status); \ - DEBUG_FPU_STATE(); \ -} \ -FLOAT_OP(name, s) \ -{ \ - FST2 = float32_ ## name(FST0, &env->fp_status); \ - DEBUG_FPU_STATE(); \ -} -FLOAT_UNOP(sqrt) -#undef FLOAT_UNOP - -/* unary operations, not modifying fp status */ -#define FLOAT_UNOP(name) \ -FLOAT_OP(name, d) \ -{ \ - FDT2 = float64_ ## name(FDT0); \ - DEBUG_FPU_STATE(); \ -} \ -FLOAT_OP(name, s) \ -{ \ - FST2 = float32_ ## name(FST0); \ - DEBUG_FPU_STATE(); \ -} -FLOAT_UNOP(abs) -FLOAT_UNOP(chs) -#undef FLOAT_UNOP - -FLOAT_OP(mov, d) -{ - FDT2 = FDT0; - DEBUG_FPU_STATE(); - RETURN(); -} -FLOAT_OP(mov, s) -{ - FST2 = FST0; - DEBUG_FPU_STATE(); - RETURN(); -} - -#ifdef CONFIG_SOFTFLOAT -#define clear_invalid() do { \ - int flags = get_float_exception_flags(&env->fp_status); \ - flags &= ~float_flag_invalid; \ - set_float_exception_flags(flags, &env->fp_status); \ -} while(0) -#else -#define clear_invalid() do { } while(0) -#endif - -extern void dump_fpu_s(CPUState *env); - -#define FOP_COND(fmt, op, sig, cond) \ -void op_cmp_ ## fmt ## _ ## op (void) \ -{ \ - if (cond) \ - SET_FP_COND(env->fcr31); \ - else \ - CLEAR_FP_COND(env->fcr31); \ - if (!sig) \ - clear_invalid(); \ - /*CALL_FROM_TB1(dump_fpu_s, env);*/ \ - DEBUG_FPU_STATE(); \ - RETURN(); \ -} - -flag float64_is_unordered(float64 a, float64 b STATUS_PARAM) -{ - extern flag float64_is_nan( float64 a ); - if (float64_is_nan(a) || float64_is_nan(b)) { - float_raise(float_flag_invalid, status); - return 1; - } - else { - return 0; - } -} - -FOP_COND(d, f, 0, 0) -FOP_COND(d, un, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status)) -FOP_COND(d, eq, 0, float64_eq(FDT0, FDT1, &env->fp_status)) -FOP_COND(d, ueq, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status)) -FOP_COND(d, olt, 0, float64_lt(FDT0, FDT1, &env->fp_status)) -FOP_COND(d, ult, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status)) -FOP_COND(d, ole, 0, float64_le(FDT0, FDT1, &env->fp_status)) -FOP_COND(d, ule, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status)) -/* NOTE: the comma operator will make "cond" to eval to false, - * but float*_is_unordered() is still called - */ -FOP_COND(d, sf, 1, (float64_is_unordered(FDT0, FDT1, &env->fp_status), 0)) -FOP_COND(d, ngle,1, float64_is_unordered(FDT1, FDT0, &env->fp_status)) -FOP_COND(d, seq, 1, float64_eq(FDT0, FDT1, &env->fp_status)) -FOP_COND(d, ngl, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status)) -FOP_COND(d, lt, 1, float64_lt(FDT0, FDT1, &env->fp_status)) -FOP_COND(d, nge, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status)) -FOP_COND(d, le, 1, float64_le(FDT0, FDT1, &env->fp_status)) -FOP_COND(d, ngt, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status)) - -flag float32_is_unordered(float32 a, float32 b STATUS_PARAM) -{ - extern flag float32_is_nan( float32 a ); - if (float32_is_nan(a) || float32_is_nan(b)) { - float_raise(float_flag_invalid, status); - return 1; - } - else { - return 0; - } -} - -/* NOTE: the comma operator will make "cond" to eval to false, - * but float*_is_unordered() is still called - */ -FOP_COND(s, f, 0, 0) -FOP_COND(s, un, 0, float32_is_unordered(FST1, FST0, &env->fp_status)) -FOP_COND(s, eq, 0, float32_eq(FST0, FST1, &env->fp_status)) -FOP_COND(s, ueq, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status)) -FOP_COND(s, olt, 0, float32_lt(FST0, FST1, &env->fp_status)) -FOP_COND(s, ult, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status)) -FOP_COND(s, ole, 0, float32_le(FST0, FST1, &env->fp_status)) -FOP_COND(s, ule, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status)) -/* NOTE: the comma operator will make "cond" to eval to false, - * but float*_is_unordered() is still called - */ -FOP_COND(s, sf, 1, (float32_is_unordered(FST0, FST1, &env->fp_status), 0)) -FOP_COND(s, ngle,1, float32_is_unordered(FST1, FST0, &env->fp_status)) -FOP_COND(s, seq, 1, float32_eq(FST0, FST1, &env->fp_status)) -FOP_COND(s, ngl, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status)) -FOP_COND(s, lt, 1, float32_lt(FST0, FST1, &env->fp_status)) -FOP_COND(s, nge, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status)) -FOP_COND(s, le, 1, float32_le(FST0, FST1, &env->fp_status)) -FOP_COND(s, ngt, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status)) - -void op_bc1f (void) -{ - T0 = ! IS_FP_COND_SET(env->fcr31); - DEBUG_FPU_STATE(); - RETURN(); -} - -void op_bc1t (void) -{ - T0 = IS_FP_COND_SET(env->fcr31); - DEBUG_FPU_STATE(); - RETURN(); -} -#endif /* MIPS_USES_FPU */ - -#if defined(MIPS_USES_R4K_TLB) -void op_tlbwi (void) -{ - CALL_FROM_TB0(do_tlbwi); - RETURN(); -} - -void op_tlbwr (void) -{ - CALL_FROM_TB0(do_tlbwr); - RETURN(); -} - -void op_tlbp (void) -{ - CALL_FROM_TB0(do_tlbp); - RETURN(); -} - -void op_tlbr (void) -{ - CALL_FROM_TB0(do_tlbr); - RETURN(); -} -#endif - -/* Specials */ -void op_pmon (void) -{ - CALL_FROM_TB1(do_pmon, PARAM1); -} - -void op_trap (void) -{ - if (T0) { - CALL_FROM_TB1(do_raise_exception_direct, EXCP_TRAP); - } - RETURN(); -} - -void op_debug (void) -{ - CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG); -} - -void op_set_lladdr (void) -{ - env->CP0_LLAddr = T2; -} - -void debug_eret (void); -void op_eret (void) -{ - CALL_FROM_TB0(debug_eret); - if (env->hflags & MIPS_HFLAG_ERL) { - env->PC = env->CP0_ErrorEPC; - env->hflags &= ~MIPS_HFLAG_ERL; - env->CP0_Status &= ~(1 << CP0St_ERL); - } else { - env->PC = env->CP0_EPC; - env->hflags &= ~MIPS_HFLAG_EXL; - env->CP0_Status &= ~(1 << CP0St_EXL); - } - env->CP0_LLAddr = 1; -} - -void op_deret (void) -{ - CALL_FROM_TB0(debug_eret); - env->PC = env->CP0_DEPC; -} - -void op_save_state (void) -{ - env->hflags = PARAM1; - RETURN(); -} - -void op_save_pc (void) -{ - env->PC = PARAM1; - RETURN(); -} - -void op_raise_exception (void) -{ - CALL_FROM_TB1(do_raise_exception, PARAM1); - RETURN(); -} - -void op_raise_exception_err (void) -{ - CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2); - RETURN(); -} - -void op_exit_tb (void) -{ - EXIT_TB(); -} - -void op_wait (void) -{ - env->halted = 1; - CALL_FROM_TB1(do_raise_exception, EXCP_HLT); -} diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c deleted file mode 100644 index bf397c9..0000000 --- a/target-mips/op_helper.c +++ /dev/null @@ -1,786 +0,0 @@ -/* - * MIPS emulation helpers for qemu. - * - * Copyright (c) 2004-2005 Jocelyn Mayer - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include "exec.h" - -#define MIPS_DEBUG_DISAS - -#define GETPC() (__builtin_return_address(0)) - -/*****************************************************************************/ -/* Exceptions processing helpers */ -void cpu_loop_exit(void) -{ - longjmp(env->jmp_env, 1); -} - -void do_raise_exception_err (uint32_t exception, int error_code) -{ -#if 1 - if (logfile && exception < 0x100) - fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code); -#endif - env->exception_index = exception; - env->error_code = error_code; - T0 = 0; - cpu_loop_exit(); -} - -void do_raise_exception (uint32_t exception) -{ - do_raise_exception_err(exception, 0); -} - -void do_restore_state (void *pc_ptr) -{ - TranslationBlock *tb; - unsigned long pc = (unsigned long) pc_ptr; - - tb = tb_find_pc (pc); - cpu_restore_state (tb, env, pc, NULL); -} - -void do_raise_exception_direct (uint32_t exception) -{ - do_restore_state (GETPC ()); - do_raise_exception_err (exception, 0); -} - -#define MEMSUFFIX _raw -#include "op_helper_mem.c" -#undef MEMSUFFIX -#if !defined(CONFIG_USER_ONLY) -#define MEMSUFFIX _user -#include "op_helper_mem.c" -#undef MEMSUFFIX -#define MEMSUFFIX _kernel -#include "op_helper_mem.c" -#undef MEMSUFFIX -#endif - -/* 64 bits arithmetic for 32 bits hosts */ -#if (HOST_LONG_BITS == 32) -static inline uint64_t get_HILO (void) -{ - return ((uint64_t)env->HI << 32) | (uint64_t)env->LO; -} - -static inline void set_HILO (uint64_t HILO) -{ - env->LO = HILO & 0xFFFFFFFF; - env->HI = HILO >> 32; -} - -void do_mult (void) -{ - set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); -} - -void do_multu (void) -{ - set_HILO((uint64_t)T0 * (uint64_t)T1); -} - -void do_madd (void) -{ - int64_t tmp; - - tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); - set_HILO((int64_t)get_HILO() + tmp); -} - -void do_maddu (void) -{ - uint64_t tmp; - - tmp = ((uint64_t)T0 * (uint64_t)T1); - set_HILO(get_HILO() + tmp); -} - -void do_msub (void) -{ - int64_t tmp; - - tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); - set_HILO((int64_t)get_HILO() - tmp); -} - -void do_msubu (void) -{ - uint64_t tmp; - - tmp = ((uint64_t)T0 * (uint64_t)T1); - set_HILO(get_HILO() - tmp); -} -#endif - -#if defined(CONFIG_USER_ONLY) -void do_mfc0 (int reg, int sel) -{ - cpu_abort(env, "mfc0 reg=%d sel=%d\n", reg, sel); -} -void do_mtc0 (int reg, int sel) -{ - cpu_abort(env, "mtc0 reg=%d sel=%d\n", reg, sel); -} - -void do_tlbwi (void) -{ - cpu_abort(env, "tlbwi\n"); -} - -void do_tlbwr (void) -{ - cpu_abort(env, "tlbwr\n"); -} - -void do_tlbp (void) -{ - cpu_abort(env, "tlbp\n"); -} - -void do_tlbr (void) -{ - cpu_abort(env, "tlbr\n"); -} -#else - -/* CP0 helpers */ -void do_mfc0 (int reg, int sel) -{ - const unsigned char *rn; - - if (sel != 0 && reg != 16 && reg != 28) { - rn = "invalid"; - goto print; - } - switch (reg) { - case 0: - T0 = env->CP0_index; - rn = "Index"; - break; - case 1: - T0 = cpu_mips_get_random(env); - rn = "Random"; - break; - case 2: - T0 = env->CP0_EntryLo0; - rn = "EntryLo0"; - break; - case 3: - T0 = env->CP0_EntryLo1; - rn = "EntryLo1"; - break; - case 4: - T0 = env->CP0_Context; - rn = "Context"; - break; - case 5: - T0 = env->CP0_PageMask; - rn = "PageMask"; - break; - case 6: - T0 = env->CP0_Wired; - rn = "Wired"; - break; - case 8: - T0 = env->CP0_BadVAddr; - rn = "BadVaddr"; - break; - case 9: - T0 = cpu_mips_get_count(env); - rn = "Count"; - break; - case 10: - T0 = env->CP0_EntryHi; - rn = "EntryHi"; - break; - case 11: - T0 = env->CP0_Compare; - rn = "Compare"; - break; - case 12: - T0 = env->CP0_Status; - if (env->hflags & MIPS_HFLAG_UM) - T0 |= (1 << CP0St_UM); - rn = "Status"; - break; - case 13: - T0 = env->CP0_Cause; - rn = "Cause"; - break; - case 14: - T0 = env->CP0_EPC; - rn = "EPC"; - break; - case 15: - T0 = env->CP0_PRid; - rn = "PRid"; - break; - case 16: - switch (sel) { - case 0: - T0 = env->CP0_Config0; - rn = "Config"; - break; - case 1: - T0 = env->CP0_Config1; - rn = "Config1"; - break; - default: - rn = "Unknown config register"; - break; - } - break; - case 17: - T0 = env->CP0_LLAddr >> 4; - rn = "LLAddr"; - break; - case 18: - T0 = env->CP0_WatchLo; - rn = "WatchLo"; - break; - case 19: - T0 = env->CP0_WatchHi; - rn = "WatchHi"; - break; - case 23: - T0 = env->CP0_Debug; - if (env->hflags & MIPS_HFLAG_DM) - T0 |= 1 << CP0DB_DM; - rn = "Debug"; - break; - case 24: - T0 = env->CP0_DEPC; - rn = "DEPC"; - break; - case 28: - switch (sel) { - case 0: - T0 = env->CP0_TagLo; - rn = "TagLo"; - break; - case 1: - T0 = env->CP0_DataLo; - rn = "DataLo"; - break; - default: - rn = "unknown sel"; - break; - } - break; - case 30: - T0 = env->CP0_ErrorEPC; - rn = "ErrorEPC"; - break; - case 31: - T0 = env->CP0_DESAVE; - rn = "DESAVE"; - break; - default: - rn = "unknown"; - break; - } - print: -#if defined MIPS_DEBUG_DISAS - if (loglevel & CPU_LOG_TB_IN_ASM) { - fprintf(logfile, "%08x mfc0 %s => %08x (%d %d)\n", - env->PC, rn, T0, reg, sel); - } -#endif - return; -} - -void do_mtc0 (int reg, int sel) -{ - const unsigned char *rn; - uint32_t val, old, mask; - - if (sel != 0 && reg != 16 && reg != 28) { - val = -1; - old = -1; - rn = "invalid"; - goto print; - } - switch (reg) { - case 0: - val = (env->CP0_index & 0x80000000) | (T0 & 0x0000000F); - old = env->CP0_index; - env->CP0_index = val; - rn = "Index"; - break; - case 2: - val = T0 & 0x3FFFFFFF; - old = env->CP0_EntryLo0; - env->CP0_EntryLo0 = val; - rn = "EntryLo0"; - break; - case 3: - val = T0 & 0x3FFFFFFF; - old = env->CP0_EntryLo1; - env->CP0_EntryLo1 = val; - rn = "EntryLo1"; - break; - case 4: - val = (env->CP0_Context & 0xFF800000) | (T0 & 0x007FFFF0); - old = env->CP0_Context; - env->CP0_Context = val; - rn = "Context"; - break; - case 5: - val = T0 & 0x01FFE000; - old = env->CP0_PageMask; - env->CP0_PageMask = val; - rn = "PageMask"; - break; - case 6: - val = T0 & 0x0000000F; - old = env->CP0_Wired; - env->CP0_Wired = val; - rn = "Wired"; - break; - case 9: - val = T0; - old = cpu_mips_get_count(env); - cpu_mips_store_count(env, val); - rn = "Count"; - break; - case 10: - val = T0 & 0xFFFFE0FF; - old = env->CP0_EntryHi; - env->CP0_EntryHi = val; - /* If the ASID changes, flush qemu's TLB. */ - if ((old & 0xFF) != (val & 0xFF)) - tlb_flush (env, 1); - rn = "EntryHi"; - break; - case 11: - val = T0; - old = env->CP0_Compare; - cpu_mips_store_compare(env, val); - rn = "Compare"; - break; - case 12: - val = T0 & 0xFA78FF01; - if (T0 & (1 << CP0St_UM)) - env->hflags |= MIPS_HFLAG_UM; - else - env->hflags &= ~MIPS_HFLAG_UM; - if (T0 & (1 << CP0St_ERL)) - env->hflags |= MIPS_HFLAG_ERL; - else - env->hflags &= ~MIPS_HFLAG_ERL; - if (T0 & (1 << CP0St_EXL)) - env->hflags |= MIPS_HFLAG_EXL; - else - env->hflags &= ~MIPS_HFLAG_EXL; - old = env->CP0_Status; - env->CP0_Status = val; - /* If we unmasked an asserted IRQ, raise it */ - mask = 0x0000FF00; - if (loglevel & CPU_LOG_TB_IN_ASM) { - fprintf(logfile, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n", - old, val, env->CP0_Cause, old & mask, val & mask, - env->CP0_Cause & mask); - } - if ((val & (1 << CP0St_IE)) && !(old & (1 << CP0St_IE)) && - !(env->hflags & MIPS_HFLAG_EXL) && - !(env->hflags & MIPS_HFLAG_ERL) && - !(env->hflags & MIPS_HFLAG_DM) && - (env->CP0_Status & env->CP0_Cause & mask)) { - if (logfile) - fprintf(logfile, "Raise pending IRQs\n"); - env->interrupt_request |= CPU_INTERRUPT_HARD; - } else if (!(val & (1 << CP0St_IE)) && (old & (1 << CP0St_IE))) { - env->interrupt_request &= ~CPU_INTERRUPT_HARD; - } - rn = "Status"; - break; - case 13: - val = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x000C00300); - old = env->CP0_Cause; - env->CP0_Cause = val; -#if 0 - { - int i; - /* Check if we ever asserted a software IRQ */ - for (i = 0; i < 2; i++) { - mask = 0x100 << i; - if ((val & mask) & !(old & mask)) - mips_set_irq(i); - } - } -#endif - rn = "Cause"; - break; - case 14: - val = T0; - old = env->CP0_EPC; - env->CP0_EPC = val; - rn = "EPC"; - break; - case 16: - switch (sel) { - case 0: -#if defined(MIPS_USES_R4K_TLB) - val = (env->CP0_Config0 & 0x8017FF80) | (T0 & 0x7E000001); -#else - val = (env->CP0_Config0 & 0xFE17FF80) | (T0 & 0x00000001); -#endif - old = env->CP0_Config0; - env->CP0_Config0 = val; - rn = "Config0"; - break; - default: - val = -1; - old = -1; - rn = "bad config selector"; - break; - } - break; - case 18: - val = T0; - old = env->CP0_WatchLo; - env->CP0_WatchLo = val; - rn = "WatchLo"; - break; - case 19: - val = T0 & 0x40FF0FF8; - old = env->CP0_WatchHi; - env->CP0_WatchHi = val; - rn = "WatchHi"; - break; - case 23: - val = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120); - if (T0 & (1 << CP0DB_DM)) - env->hflags |= MIPS_HFLAG_DM; - else - env->hflags &= ~MIPS_HFLAG_DM; - old = env->CP0_Debug; - env->CP0_Debug = val; - rn = "Debug"; - break; - case 24: - val = T0; - old = env->CP0_DEPC; - env->CP0_DEPC = val; - rn = "DEPC"; - break; - case 28: - switch (sel) { - case 0: - val = T0 & 0xFFFFFCF6; - old = env->CP0_TagLo; - env->CP0_TagLo = val; - rn = "TagLo"; - break; - default: - val = -1; - old = -1; - rn = "invalid sel"; - break; - } - break; - case 30: - val = T0; - old = env->CP0_ErrorEPC; - env->CP0_ErrorEPC = val; - rn = "EPC"; - break; - case 31: - val = T0; - old = env->CP0_DESAVE; - env->CP0_DESAVE = val; - rn = "DESAVE"; - break; - default: - val = -1; - old = -1; - rn = "unknown"; - break; - } - print: -#if defined MIPS_DEBUG_DISAS - if (loglevel & CPU_LOG_TB_IN_ASM) { - fprintf(logfile, "%08x mtc0 %s %08x => %08x (%d %d %08x)\n", - env->PC, rn, T0, val, reg, sel, old); - } -#endif - return; -} - -#ifdef MIPS_USES_FPU -#include "softfloat.h" - -void fpu_handle_exception(void) -{ -#ifdef CONFIG_SOFTFLOAT - int flags = get_float_exception_flags(&env->fp_status); - unsigned int cpuflags = 0, enable, cause = 0; - - enable = GET_FP_ENABLE(env->fcr31); - - /* determine current flags */ - if (flags & float_flag_invalid) { - cpuflags |= FP_INVALID; - cause |= FP_INVALID & enable; - } - if (flags & float_flag_divbyzero) { - cpuflags |= FP_DIV0; - cause |= FP_DIV0 & enable; - } - if (flags & float_flag_overflow) { - cpuflags |= FP_OVERFLOW; - cause |= FP_OVERFLOW & enable; - } - if (flags & float_flag_underflow) { - cpuflags |= FP_UNDERFLOW; - cause |= FP_UNDERFLOW & enable; - } - if (flags & float_flag_inexact) { - cpuflags |= FP_INEXACT; - cause |= FP_INEXACT & enable; - } - SET_FP_FLAGS(env->fcr31, cpuflags); - SET_FP_CAUSE(env->fcr31, cause); -#else - SET_FP_FLAGS(env->fcr31, 0); - SET_FP_CAUSE(env->fcr31, 0); -#endif -} -#endif /* MIPS_USES_FPU */ - -/* TLB management */ -#if defined(MIPS_USES_R4K_TLB) -static void invalidate_tlb (int idx) -{ - tlb_t *tlb; - target_ulong addr; - - tlb = &env->tlb[idx]; - if (tlb->V0) { - tb_invalidate_page_range(tlb->PFN[0], tlb->end - tlb->VPN); - addr = tlb->VPN; - while (addr < tlb->end) { - tlb_flush_page (env, addr); - addr += TARGET_PAGE_SIZE; - } - } - if (tlb->V1) { - tb_invalidate_page_range(tlb->PFN[1], tlb->end2 - tlb->end); - addr = tlb->end; - while (addr < tlb->end2) { - tlb_flush_page (env, addr); - addr += TARGET_PAGE_SIZE; - } - } -} - -static void fill_tlb (int idx) -{ - tlb_t *tlb; - int size; - - /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ - tlb = &env->tlb[idx]; - tlb->VPN = env->CP0_EntryHi & 0xFFFFE000; - tlb->ASID = env->CP0_EntryHi & 0xFF; - size = env->CP0_PageMask >> 13; - size = 4 * (size + 1); - tlb->end = tlb->VPN + (1 << (8 + size)); - tlb->end2 = tlb->end + (1 << (8 + size)); - tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; - tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; - tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; - tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; - tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; - tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; - tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; - tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; - tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; -} - -void do_tlbwi (void) -{ - /* Wildly undefined effects for CP0_index containing a too high value and - MIPS_TLB_NB not being a power of two. But so does real silicon. */ - invalidate_tlb(env->CP0_index & (MIPS_TLB_NB - 1)); - fill_tlb(env->CP0_index & (MIPS_TLB_NB - 1)); -} - -void do_tlbwr (void) -{ - int r = cpu_mips_get_random(env); - - invalidate_tlb(r); - fill_tlb(r); -} - -void do_tlbp (void) -{ - tlb_t *tlb; - target_ulong tag; - uint8_t ASID; - int i; - - tag = env->CP0_EntryHi & 0xFFFFE000; - ASID = env->CP0_EntryHi & 0xFF; - for (i = 0; i < MIPS_TLB_NB; i++) { - tlb = &env->tlb[i]; - /* Check ASID, virtual page number & size */ - if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { - /* TLB match */ - env->CP0_index = i; - break; - } - } - if (i == MIPS_TLB_NB) { - env->CP0_index |= 0x80000000; - } -} - -void do_tlbr (void) -{ - tlb_t *tlb; - uint8_t ASID; - int size; - - ASID = env->CP0_EntryHi & 0xFF; - tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)]; - - /* If this will change the current ASID, flush qemu's TLB. */ - if (ASID != tlb->ASID && tlb->G != 1) - tlb_flush (env, 1); - - env->CP0_EntryHi = tlb->VPN | tlb->ASID; - size = (tlb->end - tlb->VPN) >> 12; - env->CP0_PageMask = (size - 1) << 13; - env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) - | (tlb->C0 << 3) | (tlb->PFN[0] >> 6); - env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) - | (tlb->C1 << 3) | (tlb->PFN[1] >> 6); -} -#endif - -#endif /* !CONFIG_USER_ONLY */ - -void op_dump_ldst (const unsigned char *func) -{ - if (loglevel) - fprintf(logfile, "%s => %08x %08x\n", __func__, T0, T1); -} - -void dump_sc (void) -{ - if (loglevel) { - fprintf(logfile, "%s %08x at %08x (%08x)\n", __func__, - T1, T0, env->CP0_LLAddr); - } -} - -void debug_eret (void) -{ - if (loglevel) { - fprintf(logfile, "ERET: pc %08x EPC %08x ErrorEPC %08x (%d)\n", - env->PC, env->CP0_EPC, env->CP0_ErrorEPC, - env->hflags & MIPS_HFLAG_ERL ? 1 : 0); - } -} - -void do_pmon (int function) -{ - function /= 2; - switch (function) { - case 2: /* TODO: char inbyte(int waitflag); */ - if (env->gpr[4] == 0) - env->gpr[2] = -1; - /* Fall through */ - case 11: /* TODO: char inbyte (void); */ - env->gpr[2] = -1; - break; - case 3: - case 12: - printf("%c", env->gpr[4] & 0xFF); - break; - case 17: - break; - case 158: - { - unsigned char *fmt = (void *)env->gpr[4]; - printf("%s", fmt); - } - break; - } -} - -#if !defined(CONFIG_USER_ONLY) - -static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); - -#define MMUSUFFIX _mmu -#define ALIGNED_ONLY - -#define SHIFT 0 -#include "softmmu_template.h" - -#define SHIFT 1 -#include "softmmu_template.h" - -#define SHIFT 2 -#include "softmmu_template.h" - -#define SHIFT 3 -#include "softmmu_template.h" - -static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) -{ - env->CP0_BadVAddr = addr; - do_restore_state (retaddr); - do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL); -} - -void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr) -{ - TranslationBlock *tb; - CPUState *saved_env; - unsigned long pc; - int ret; - - /* XXX: hack to restore env in all cases, even if not called from - generated code */ - saved_env = env; - env = cpu_single_env; - ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1); - if (ret) { - if (retaddr) { - /* now we have a real cpu fault */ - pc = (unsigned long)retaddr; - tb = tb_find_pc(pc); - if (tb) { - /* the PC is inside the translated code. It means that we have - a virtual CPU fault */ - cpu_restore_state(tb, env, pc, NULL); - } - } - do_raise_exception_err(env->exception_index, env->error_code); - } - env = saved_env; -} - -#endif diff --git a/target-mips/op_helper_mem.c b/target-mips/op_helper_mem.c deleted file mode 100644 index 4711f7a..0000000 --- a/target-mips/op_helper_mem.c +++ /dev/null @@ -1,141 +0,0 @@ -#ifdef TARGET_WORDS_BIGENDIAN -#define GET_LMASK(v) ((v) & 3) -#else -#define GET_LMASK(v) (((v) & 3) ^ 3) -#endif - -void glue(do_lwl, MEMSUFFIX) (uint32_t tmp) -{ -#if defined (DEBUG_OP) - target_ulong sav = T0; -#endif - - /* XXX: this is valid only in big-endian mode - * should be reverted for little-endian... - */ - switch (GET_LMASK(T0)) { - case 0: - T0 = tmp; - break; - case 1: - T0 = (tmp << 8) | (T1 & 0x000000FF); - break; - case 2: - T0 = (tmp << 16) | (T1 & 0x0000FFFF); - break; - case 3: - T0 = (tmp << 24) | (T1 & 0x00FFFFFF); - break; - } -#if defined (DEBUG_OP) - if (logfile) { - fprintf(logfile, "%s: %08x - %08x %08x => %08x\n", - __func__, sav, tmp, T1, T0); - } -#endif - RETURN(); -} - -void glue(do_lwr, MEMSUFFIX) (uint32_t tmp) -{ -#if defined (DEBUG_OP) - target_ulong sav = T0; -#endif - - /* XXX: this is valid only in big-endian mode - * should be reverted for little-endian... - */ - switch (GET_LMASK(T0)) { - case 0: - T0 = (tmp >> 24) | (T1 & 0xFFFFFF00); - break; - case 1: - T0 = (tmp >> 16) | (T1 & 0xFFFF0000); - break; - case 2: - T0 = (tmp >> 8) | (T1 & 0xFF000000); - break; - case 3: - T0 = tmp; - break; - } -#if defined (DEBUG_OP) - if (logfile) { - fprintf(logfile, "%s: %08x - %08x %08x => %08x\n", - __func__, sav, tmp, T1, T0); - } -#endif - RETURN(); -} - -uint32_t glue(do_swl, MEMSUFFIX) (uint32_t tmp) -{ -#if defined (DEBUG_OP) - target_ulong sav; -#endif - -#if defined (DEBUG_OP) - sav = tmp; -#endif - /* XXX: this is valid only in big-endian mode - * should be reverted for little-endian... - */ - switch (GET_LMASK(T0)) { - case 0: - tmp = T1; - break; - case 1: - tmp = (tmp & 0xFF000000) | (T1 >> 8); - break; - case 2: - tmp = (tmp & 0xFFFF0000) | (T1 >> 16); - break; - case 3: - tmp = (tmp & 0xFFFFFF00) | (T1 >> 24); - break; - } -#if defined (DEBUG_OP) - if (logfile) { - fprintf(logfile, "%s: %08x - %08x %08x => %08x\n", - __func__, T0, sav, T1, tmp); - } -#endif - RETURN(); - return tmp; -} - -uint32_t glue(do_swr, MEMSUFFIX) (uint32_t tmp) -{ -#if defined (DEBUG_OP) - target_ulong sav; -#endif - -#if defined (DEBUG_OP) - sav = tmp; -#endif - /* XXX: this is valid only in big-endian mode - * should be reverted for little-endian... - */ - switch (GET_LMASK(T0)) { - case 0: - tmp = (tmp & 0x00FFFFFF) | (T1 << 24); - break; - case 1: - tmp = (tmp & 0x0000FFFF) | (T1 << 16); - break; - case 2: - tmp = (tmp & 0x000000FF) | (T1 << 8); - break; - case 3: - tmp = T1; - break; - } -#if defined (DEBUG_OP) - if (logfile) { - fprintf(logfile, "%s: %08x - %08x %08x => %08x\n", - __func__, T0, sav, T1, tmp); - } -#endif - RETURN(); - return tmp; -} diff --git a/target-mips/op_mem.c b/target-mips/op_mem.c deleted file mode 100644 index 35ccd44..0000000 --- a/target-mips/op_mem.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * MIPS emulation memory micro-operations for qemu. - * - * Copyright (c) 2004-2005 Jocelyn Mayer - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -/* Standard loads and stores */ -void glue(op_lb, MEMSUFFIX) (void) -{ - T0 = glue(ldsb, MEMSUFFIX)(T0); - RETURN(); -} - -void glue(op_lbu, MEMSUFFIX) (void) -{ - T0 = glue(ldub, MEMSUFFIX)(T0); - RETURN(); -} - -void glue(op_sb, MEMSUFFIX) (void) -{ - glue(stb, MEMSUFFIX)(T0, T1); - RETURN(); -} - -void glue(op_lh, MEMSUFFIX) (void) -{ - T0 = glue(ldsw, MEMSUFFIX)(T0); - RETURN(); -} - -void glue(op_lhu, MEMSUFFIX) (void) -{ - T0 = glue(lduw, MEMSUFFIX)(T0); - RETURN(); -} - -void glue(op_sh, MEMSUFFIX) (void) -{ - glue(stw, MEMSUFFIX)(T0, T1); - RETURN(); -} - -void glue(op_lw, MEMSUFFIX) (void) -{ - T0 = glue(ldl, MEMSUFFIX)(T0); - RETURN(); -} - -void glue(op_lwu, MEMSUFFIX) (void) -{ - T0 = glue(ldl, MEMSUFFIX)(T0); - RETURN(); -} - -void glue(op_sw, MEMSUFFIX) (void) -{ - glue(stl, MEMSUFFIX)(T0, T1); - RETURN(); -} - -/* "half" load and stores. We must do the memory access inline, - or fault handling won't work. */ -void glue(op_lwl, MEMSUFFIX) (void) -{ - uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3); - CALL_FROM_TB1(glue(do_lwl, MEMSUFFIX), tmp); - RETURN(); -} - -void glue(op_lwr, MEMSUFFIX) (void) -{ - uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3); - CALL_FROM_TB1(glue(do_lwr, MEMSUFFIX), tmp); - RETURN(); -} - -void glue(op_swl, MEMSUFFIX) (void) -{ - uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3); - tmp = CALL_FROM_TB1(glue(do_swl, MEMSUFFIX), tmp); - glue(stl, MEMSUFFIX)(T0 & ~3, tmp); - RETURN(); -} - -void glue(op_swr, MEMSUFFIX) (void) -{ - uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3); - tmp = CALL_FROM_TB1(glue(do_swr, MEMSUFFIX), tmp); - glue(stl, MEMSUFFIX)(T0 & ~3, tmp); - RETURN(); -} - -void glue(op_ll, MEMSUFFIX) (void) -{ - T1 = T0; - T0 = glue(ldl, MEMSUFFIX)(T0); - env->CP0_LLAddr = T1; - RETURN(); -} - -void glue(op_sc, MEMSUFFIX) (void) -{ - CALL_FROM_TB0(dump_sc); - if (T0 == env->CP0_LLAddr) { - glue(stl, MEMSUFFIX)(T0, T1); - T0 = 1; - } else { - T0 = 0; - } - RETURN(); -} - -#ifdef MIPS_USES_FPU -void glue(op_lwc1, MEMSUFFIX) (void) -{ - WT0 = glue(ldl, MEMSUFFIX)(T0); - RETURN(); -} -void glue(op_swc1, MEMSUFFIX) (void) -{ - glue(stl, MEMSUFFIX)(T0, WT0); - RETURN(); -} -void glue(op_ldc1, MEMSUFFIX) (void) -{ - DT0 = glue(ldq, MEMSUFFIX)(T0); - RETURN(); -} -void glue(op_sdc1, MEMSUFFIX) (void) -{ - glue(stq, MEMSUFFIX)(T0, DT0); - RETURN(); -} -#endif diff --git a/target-mips/op_template.c b/target-mips/op_template.c deleted file mode 100644 index 9314c95..0000000 --- a/target-mips/op_template.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * MIPS emulation micro-operations templates for reg load & store for qemu. - * - * Copyright (c) 2004-2005 Jocelyn Mayer - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#if defined(REG) -void glue(op_load_gpr_T0_gpr, REG) (void) -{ - T0 = env->gpr[REG]; - RETURN(); -} - -void glue(op_store_T0_gpr_gpr, REG) (void) -{ - env->gpr[REG] = T0; - RETURN(); -} - -void glue(op_load_gpr_T1_gpr, REG) (void) -{ - T1 = env->gpr[REG]; - RETURN(); -} - -void glue(op_store_T1_gpr_gpr, REG) (void) -{ - env->gpr[REG] = T1; - RETURN(); -} - -void glue(op_load_gpr_T2_gpr, REG) (void) -{ - T2 = env->gpr[REG]; - RETURN(); -} -#endif - -#if defined (TN) -void glue(op_set_, TN) (void) -{ - TN = PARAM1; - RETURN(); -} - -void glue (op_reset_, TN) (void) -{ - TN = 0; - RETURN(); -} -#endif diff --git a/target-mips/translate.c b/target-mips/translate.c deleted file mode 100644 index 7ad8ebd..0000000 --- a/target-mips/translate.c +++ /dev/null @@ -1,2443 +0,0 @@ -/* - * MIPS32 emulation for qemu: main translation routines. - * - * Copyright (c) 2004-2005 Jocelyn Mayer - * Copyright (c) 2006 Marius Groeger (FPU operations) - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include <stdarg.h> -#include <stdlib.h> -#include <stdio.h> -#include <string.h> -#include <inttypes.h> - -#include "cpu.h" -#include "exec-all.h" -#include "disas.h" - -//#define MIPS_DEBUG_DISAS -//#define MIPS_SINGLE_STEP - -#ifdef USE_DIRECT_JUMP -#define TBPARAM(x) -#else -#define TBPARAM(x) (long)(x) -#endif - -enum { -#define DEF(s, n, copy_size) INDEX_op_ ## s, -#include "opc.h" -#undef DEF - NB_OPS, -}; - -static uint16_t *gen_opc_ptr; -static uint32_t *gen_opparam_ptr; - -#include "gen-op.h" - -/* MIPS opcodes */ -#define EXT_SPECIAL 0x100 -#define EXT_SPECIAL2 0x200 -#define EXT_REGIMM 0x300 -#define EXT_CP0 0x400 -#define EXT_CP1 0x500 -#define EXT_CP2 0x600 -#define EXT_CP3 0x700 - -enum { - /* indirect opcode tables */ - OPC_SPECIAL = 0x00, - OPC_BREGIMM = 0x01, - OPC_CP0 = 0x10, - OPC_CP1 = 0x11, - OPC_CP2 = 0x12, - OPC_CP3 = 0x13, - OPC_SPECIAL2 = 0x1C, - /* arithmetic with immediate */ - OPC_ADDI = 0x08, - OPC_ADDIU = 0x09, - OPC_SLTI = 0x0A, - OPC_SLTIU = 0x0B, - OPC_ANDI = 0x0C, - OPC_ORI = 0x0D, - OPC_XORI = 0x0E, - OPC_LUI = 0x0F, - /* Jump and branches */ - OPC_J = 0x02, - OPC_JAL = 0x03, - OPC_BEQ = 0x04, /* Unconditional if rs = rt = 0 (B) */ - OPC_BEQL = 0x14, - OPC_BNE = 0x05, - OPC_BNEL = 0x15, - OPC_BLEZ = 0x06, - OPC_BLEZL = 0x16, - OPC_BGTZ = 0x07, - OPC_BGTZL = 0x17, - OPC_JALX = 0x1D, /* MIPS 16 only */ - /* Load and stores */ - OPC_LB = 0x20, - OPC_LH = 0x21, - OPC_LWL = 0x22, - OPC_LW = 0x23, - OPC_LBU = 0x24, - OPC_LHU = 0x25, - OPC_LWR = 0x26, - OPC_LWU = 0x27, - OPC_SB = 0x28, - OPC_SH = 0x29, - OPC_SWL = 0x2A, - OPC_SW = 0x2B, - OPC_SWR = 0x2E, - OPC_LL = 0x30, - OPC_SC = 0x38, - /* Floating point load/store */ - OPC_LWC1 = 0x31, - OPC_LWC2 = 0x32, - OPC_LDC1 = 0x35, - OPC_LDC2 = 0x36, - OPC_SWC1 = 0x39, - OPC_SWC2 = 0x3A, - OPC_SDC1 = 0x3D, - OPC_SDC2 = 0x3E, - /* Cache and prefetch */ - OPC_CACHE = 0x2F, - OPC_PREF = 0x33, -}; - -/* MIPS special opcodes */ -enum { - /* Shifts */ - OPC_SLL = 0x00 | EXT_SPECIAL, - /* NOP is SLL r0, r0, 0 */ - /* SSNOP is SLL r0, r0, 1 */ - OPC_SRL = 0x02 | EXT_SPECIAL, - OPC_SRA = 0x03 | EXT_SPECIAL, - OPC_SLLV = 0x04 | EXT_SPECIAL, - OPC_SRLV = 0x06 | EXT_SPECIAL, - OPC_SRAV = 0x07 | EXT_SPECIAL, - /* Multiplication / division */ - OPC_MULT = 0x18 | EXT_SPECIAL, - OPC_MULTU = 0x19 | EXT_SPECIAL, - OPC_DIV = 0x1A | EXT_SPECIAL, - OPC_DIVU = 0x1B | EXT_SPECIAL, - /* 2 registers arithmetic / logic */ - OPC_ADD = 0x20 | EXT_SPECIAL, - OPC_ADDU = 0x21 | EXT_SPECIAL, - OPC_SUB = 0x22 | EXT_SPECIAL, - OPC_SUBU = 0x23 | EXT_SPECIAL, - OPC_AND = 0x24 | EXT_SPECIAL, - OPC_OR = 0x25 | EXT_SPECIAL, - OPC_XOR = 0x26 | EXT_SPECIAL, - OPC_NOR = 0x27 | EXT_SPECIAL, - OPC_SLT = 0x2A | EXT_SPECIAL, - OPC_SLTU = 0x2B | EXT_SPECIAL, - /* Jumps */ - OPC_JR = 0x08 | EXT_SPECIAL, - OPC_JALR = 0x09 | EXT_SPECIAL, - /* Traps */ - OPC_TGE = 0x30 | EXT_SPECIAL, - OPC_TGEU = 0x31 | EXT_SPECIAL, - OPC_TLT = 0x32 | EXT_SPECIAL, - OPC_TLTU = 0x33 | EXT_SPECIAL, - OPC_TEQ = 0x34 | EXT_SPECIAL, - OPC_TNE = 0x36 | EXT_SPECIAL, - /* HI / LO registers load & stores */ - OPC_MFHI = 0x10 | EXT_SPECIAL, - OPC_MTHI = 0x11 | EXT_SPECIAL, - OPC_MFLO = 0x12 | EXT_SPECIAL, - OPC_MTLO = 0x13 | EXT_SPECIAL, - /* Conditional moves */ - OPC_MOVZ = 0x0A | EXT_SPECIAL, - OPC_MOVN = 0x0B | EXT_SPECIAL, - - OPC_MOVCI = 0x01 | EXT_SPECIAL, - - /* Special */ - OPC_PMON = 0x05 | EXT_SPECIAL, - OPC_SYSCALL = 0x0C | EXT_SPECIAL, - OPC_BREAK = 0x0D | EXT_SPECIAL, - OPC_SYNC = 0x0F | EXT_SPECIAL, -}; - -enum { - /* Mutiply & xxx operations */ - OPC_MADD = 0x00 | EXT_SPECIAL2, - OPC_MADDU = 0x01 | EXT_SPECIAL2, - OPC_MUL = 0x02 | EXT_SPECIAL2, - OPC_MSUB = 0x04 | EXT_SPECIAL2, - OPC_MSUBU = 0x05 | EXT_SPECIAL2, - /* Misc */ - OPC_CLZ = 0x20 | EXT_SPECIAL2, - OPC_CLO = 0x21 | EXT_SPECIAL2, - /* Special */ - OPC_SDBBP = 0x3F | EXT_SPECIAL2, -}; - -/* Branch REGIMM */ -enum { - OPC_BLTZ = 0x00 | EXT_REGIMM, - OPC_BLTZL = 0x02 | EXT_REGIMM, - OPC_BGEZ = 0x01 | EXT_REGIMM, - OPC_BGEZL = 0x03 | EXT_REGIMM, - OPC_BLTZAL = 0x10 | EXT_REGIMM, - OPC_BLTZALL = 0x12 | EXT_REGIMM, - OPC_BGEZAL = 0x11 | EXT_REGIMM, - OPC_BGEZALL = 0x13 | EXT_REGIMM, - OPC_TGEI = 0x08 | EXT_REGIMM, - OPC_TGEIU = 0x09 | EXT_REGIMM, - OPC_TLTI = 0x0A | EXT_REGIMM, - OPC_TLTIU = 0x0B | EXT_REGIMM, - OPC_TEQI = 0x0C | EXT_REGIMM, - OPC_TNEI = 0x0E | EXT_REGIMM, -}; - -enum { - /* Coprocessor 0 (MMU) */ - OPC_MFC0 = 0x00 | EXT_CP0, - OPC_MTC0 = 0x04 | EXT_CP0, - OPC_TLBR = 0x01 | EXT_CP0, - OPC_TLBWI = 0x02 | EXT_CP0, - OPC_TLBWR = 0x06 | EXT_CP0, - OPC_TLBP = 0x08 | EXT_CP0, - OPC_ERET = 0x18 | EXT_CP0, - OPC_DERET = 0x1F | EXT_CP0, - OPC_WAIT = 0x20 | EXT_CP0, -}; - -#ifdef MIPS_USES_FPU -enum { - /* Coprocessor 1 (FPU) */ - OPC_MFC1 = 0x00 | EXT_CP1, - OPC_MTC1 = 0x04 | EXT_CP1, - OPC_CFC1 = 0x02 | EXT_CP1, - OPC_CTC1 = 0x06 | EXT_CP1, -}; -#endif - -const unsigned char *regnames[] = - { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", - "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", }; - -/* Warning: no function for r0 register (hard wired to zero) */ -#define GEN32(func, NAME) \ -static GenOpFunc *NAME ## _table [32] = { \ -NULL, NAME ## 1, NAME ## 2, NAME ## 3, \ -NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ -NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ -NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ -NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ -NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ -NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ -NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ -}; \ -static inline void func(int n) \ -{ \ - NAME ## _table[n](); \ -} - -/* General purpose registers moves */ -GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr); -GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr); -GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr); - -GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr); -GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr); - -#ifdef MIPS_USES_FPU -const unsigned char *fregnames[] = - { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", - "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", }; - -# define SFGEN32(func, NAME) \ -static GenOpFunc *NAME ## _table [32] = { \ -NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ -NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ -NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ -NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ -NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ -NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ -NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ -NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ -}; \ -static inline void func(int n) \ -{ \ - NAME ## _table[n](); \ -} - -# define DFGEN32(func, NAME) \ -static GenOpFunc *NAME ## _table [32] = { \ -NAME ## 0, 0, NAME ## 2, 0, \ -NAME ## 4, 0, NAME ## 6, 0, \ -NAME ## 8, 0, NAME ## 10, 0, \ -NAME ## 12, 0, NAME ## 14, 0, \ -NAME ## 16, 0, NAME ## 18, 0, \ -NAME ## 20, 0, NAME ## 22, 0, \ -NAME ## 24, 0, NAME ## 26, 0, \ -NAME ## 28, 0, NAME ## 30, 0, \ -}; \ -static inline void func(int n) \ -{ \ - NAME ## _table[n](); \ -} - -SFGEN32(gen_op_load_fpr_WT0, gen_op_load_fpr_WT0_fpr); -SFGEN32(gen_op_store_fpr_WT0, gen_op_store_fpr_WT0_fpr); - -SFGEN32(gen_op_load_fpr_WT1, gen_op_load_fpr_WT1_fpr); -SFGEN32(gen_op_store_fpr_WT1, gen_op_store_fpr_WT1_fpr); - -SFGEN32(gen_op_load_fpr_WT2, gen_op_load_fpr_WT2_fpr); -SFGEN32(gen_op_store_fpr_WT2, gen_op_store_fpr_WT2_fpr); - -DFGEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fpr); -DFGEN32(gen_op_store_fpr_DT0, gen_op_store_fpr_DT0_fpr); - -DFGEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fpr); -DFGEN32(gen_op_store_fpr_DT1, gen_op_store_fpr_DT1_fpr); - -DFGEN32(gen_op_load_fpr_DT2, gen_op_load_fpr_DT2_fpr); -DFGEN32(gen_op_store_fpr_DT2, gen_op_store_fpr_DT2_fpr); - -#define FOP_CONDS(fmt) \ -static GenOpFunc * cond_ ## fmt ## _table[16] = { \ - gen_op_cmp_ ## fmt ## _f, \ - gen_op_cmp_ ## fmt ## _un, \ - gen_op_cmp_ ## fmt ## _eq, \ - gen_op_cmp_ ## fmt ## _ueq, \ - gen_op_cmp_ ## fmt ## _olt, \ - gen_op_cmp_ ## fmt ## _ult, \ - gen_op_cmp_ ## fmt ## _ole, \ - gen_op_cmp_ ## fmt ## _ule, \ - gen_op_cmp_ ## fmt ## _sf, \ - gen_op_cmp_ ## fmt ## _ngle, \ - gen_op_cmp_ ## fmt ## _seq, \ - gen_op_cmp_ ## fmt ## _ngl, \ - gen_op_cmp_ ## fmt ## _lt, \ - gen_op_cmp_ ## fmt ## _nge, \ - gen_op_cmp_ ## fmt ## _le, \ - gen_op_cmp_ ## fmt ## _ngt, \ -}; \ -static inline void gen_cmp_ ## fmt(int n) \ -{ \ - cond_ ## fmt ## _table[n](); \ -} - -FOP_CONDS(d) -FOP_CONDS(s) - -#endif - -typedef struct DisasContext { - struct TranslationBlock *tb; - target_ulong pc, saved_pc; - uint32_t opcode; - /* Routine used to access memory */ - int mem_idx; - uint32_t hflags, saved_hflags; - uint32_t CP0_Status; - int bstate; - target_ulong btarget; -} DisasContext; - -enum { - BS_NONE = 0, /* We go out of the TB without reaching a branch or an - * exception condition - */ - BS_STOP = 1, /* We want to stop translation for any reason */ - BS_BRANCH = 2, /* We reached a branch condition */ - BS_EXCP = 3, /* We reached an exception condition */ -}; - -#if defined MIPS_DEBUG_DISAS -#define MIPS_DEBUG(fmt, args...) \ -do { \ - if (loglevel & CPU_LOG_TB_IN_ASM) { \ - fprintf(logfile, "%08x: %08x " fmt "\n", \ - ctx->pc, ctx->opcode , ##args); \ - } \ -} while (0) -#else -#define MIPS_DEBUG(fmt, args...) do { } while(0) -#endif - -#define MIPS_INVAL(op) \ -do { \ - MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \ - ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \ -} while (0) - -#define GEN_LOAD_REG_TN(Tn, Rn) \ -do { \ - if (Rn == 0) { \ - glue(gen_op_reset_, Tn)(); \ - } else { \ - glue(gen_op_load_gpr_, Tn)(Rn); \ - } \ -} while (0) - -#define GEN_LOAD_IMM_TN(Tn, Imm) \ -do { \ - if (Imm == 0) { \ - glue(gen_op_reset_, Tn)(); \ - } else { \ - glue(gen_op_set_, Tn)(Imm); \ - } \ -} while (0) - -#define GEN_STORE_TN_REG(Rn, Tn) \ -do { \ - if (Rn != 0) { \ - glue(glue(gen_op_store_, Tn),_gpr)(Rn); \ - } \ -} while (0) - -#ifdef MIPS_USES_FPU - -# define GEN_LOAD_FREG_FTN(FTn, Fn) \ -do { \ - glue(gen_op_load_fpr_, FTn)(Fn); \ -} while (0) - -#define GEN_STORE_FTN_FREG(Fn, FTn) \ -do { \ - glue(gen_op_store_fpr_, FTn)(Fn); \ -} while (0) - -#endif - -static inline void save_cpu_state (DisasContext *ctx, int do_save_pc) -{ -#if defined MIPS_DEBUG_DISAS - if (loglevel & CPU_LOG_TB_IN_ASM) { - fprintf(logfile, "hflags %08x saved %08x\n", - ctx->hflags, ctx->saved_hflags); - } -#endif - if (do_save_pc && ctx->pc != ctx->saved_pc) { - gen_op_save_pc(ctx->pc); - ctx->saved_pc = ctx->pc; - } - if (ctx->hflags != ctx->saved_hflags) { - gen_op_save_state(ctx->hflags); - ctx->saved_hflags = ctx->hflags; - if (ctx->hflags & MIPS_HFLAG_BR) { - gen_op_save_breg_target(); - } else if (ctx->hflags & MIPS_HFLAG_B) { - gen_op_save_btarget(ctx->btarget); - } else if (ctx->hflags & MIPS_HFLAG_BMASK) { - gen_op_save_bcond(); - gen_op_save_btarget(ctx->btarget); - } - } -} - -static inline void generate_exception_err (DisasContext *ctx, int excp, int err) -{ -#if defined MIPS_DEBUG_DISAS - if (loglevel & CPU_LOG_TB_IN_ASM) - fprintf(logfile, "%s: raise exception %d\n", __func__, excp); -#endif - save_cpu_state(ctx, 1); - if (err == 0) - gen_op_raise_exception(excp); - else - gen_op_raise_exception_err(excp, err); - ctx->bstate = BS_EXCP; -} - -static inline void generate_exception (DisasContext *ctx, int excp) -{ - generate_exception_err (ctx, excp, 0); -} - -#if defined(CONFIG_USER_ONLY) -#define op_ldst(name) gen_op_##name##_raw() -#define OP_LD_TABLE(width) -#define OP_ST_TABLE(width) -#else -#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])() -#define OP_LD_TABLE(width) \ -static GenOpFunc *gen_op_l##width[] = { \ - &gen_op_l##width##_user, \ - &gen_op_l##width##_kernel, \ -} -#define OP_ST_TABLE(width) \ -static GenOpFunc *gen_op_s##width[] = { \ - &gen_op_s##width##_user, \ - &gen_op_s##width##_kernel, \ -} -#endif - -#ifdef TARGET_MIPS64 -OP_LD_TABLE(d); -OP_LD_TABLE(dl); -OP_LD_TABLE(dr); -OP_ST_TABLE(d); -OP_ST_TABLE(dl); -OP_ST_TABLE(dr); -#endif -OP_LD_TABLE(w); -OP_LD_TABLE(wu); -OP_LD_TABLE(wl); -OP_LD_TABLE(wr); -OP_ST_TABLE(w); -OP_ST_TABLE(wl); -OP_ST_TABLE(wr); -OP_LD_TABLE(h); -OP_LD_TABLE(hu); -OP_ST_TABLE(h); -OP_LD_TABLE(b); -OP_LD_TABLE(bu); -OP_ST_TABLE(b); -OP_LD_TABLE(l); -OP_ST_TABLE(c); -#ifdef MIPS_USES_FPU -OP_LD_TABLE(wc1); -OP_ST_TABLE(wc1); -OP_LD_TABLE(dc1); -OP_ST_TABLE(dc1); -#endif - -/* Load and store */ -static void gen_ldst (DisasContext *ctx, uint16_t opc, int rt, - int base, int16_t offset) -{ - const unsigned char *opn = "unk"; - - if (base == 0) { - GEN_LOAD_IMM_TN(T0, offset); - } else if (offset == 0) { - gen_op_load_gpr_T0(base); - } else { - gen_op_load_gpr_T0(base); - gen_op_set_T1(offset); - gen_op_add(); - } - /* Don't do NOP if destination is zero: we must perform the actual - * memory access - */ - switch (opc) { -#if defined(TARGET_MIPS64) - case OPC_LD: -#if defined (MIPS_HAS_UNALIGNED_LS) - case OPC_ULD: -#endif - op_ldst(ld); - GEN_STORE_TN_REG(rt, T0); - opn = "ld"; - break; - case OPC_SD: -#if defined (MIPS_HAS_UNALIGNED_LS) - case OPC_USD: -#endif - GEN_LOAD_REG_TN(T1, rt); - op_ldst(sd); - opn = "sd"; - break; - case OPC_LDL: - op_ldst(ldl); - GEN_STORE_TN_REG(rt, T0); - opn = "ldl"; - break; - case OPC_SDL: - GEN_LOAD_REG_TN(T1, rt); - op_ldst(sdl); - opn = "sdl"; - break; - case OPC_LDR: - op_ldst(ldr); - GEN_STORE_TN_REG(rt, T0); - opn = "ldr"; - break; - case OPC_SDR: - GEN_LOAD_REG_TN(T1, rt); - op_ldst(sdr); - opn = "sdr"; - break; -#endif - case OPC_LW: -#if defined (MIPS_HAS_UNALIGNED_LS) - case OPC_ULW: -#endif - op_ldst(lw); - GEN_STORE_TN_REG(rt, T0); - opn = "lw"; - break; - case OPC_LWU: - op_ldst(lwu); - GEN_STORE_TN_REG(rt, T0); - opn = "lwu"; - break; - case OPC_SW: -#if defined (MIPS_HAS_UNALIGNED_LS) - case OPC_USW: -#endif - GEN_LOAD_REG_TN(T1, rt); - op_ldst(sw); - opn = "sw"; - break; - case OPC_LH: -#if defined (MIPS_HAS_UNALIGNED_LS) - case OPC_ULH: -#endif - op_ldst(lh); - GEN_STORE_TN_REG(rt, T0); - opn = "lh"; - break; - case OPC_SH: -#if defined (MIPS_HAS_UNALIGNED_LS) - case OPC_USH: -#endif - GEN_LOAD_REG_TN(T1, rt); - op_ldst(sh); - opn = "sh"; - break; - case OPC_LHU: -#if defined (MIPS_HAS_UNALIGNED_LS) - case OPC_ULHU: -#endif - op_ldst(lhu); - GEN_STORE_TN_REG(rt, T0); - opn = "lhu"; - break; - case OPC_LB: - op_ldst(lb); - GEN_STORE_TN_REG(rt, T0); - opn = "lb"; - break; - case OPC_SB: - GEN_LOAD_REG_TN(T1, rt); - op_ldst(sb); - opn = "sb"; - break; - case OPC_LBU: - op_ldst(lbu); - GEN_STORE_TN_REG(rt, T0); - opn = "lbu"; - break; - case OPC_LWL: - GEN_LOAD_REG_TN(T1, rt); - op_ldst(lwl); - GEN_STORE_TN_REG(rt, T0); - opn = "lwl"; - break; - case OPC_SWL: - GEN_LOAD_REG_TN(T1, rt); - op_ldst(swl); - opn = "swr"; - break; - case OPC_LWR: - GEN_LOAD_REG_TN(T1, rt); - op_ldst(lwr); - GEN_STORE_TN_REG(rt, T0); - opn = "lwr"; - break; - case OPC_SWR: - GEN_LOAD_REG_TN(T1, rt); - op_ldst(swr); - opn = "swr"; - break; - case OPC_LL: - op_ldst(ll); - GEN_STORE_TN_REG(rt, T0); - opn = "ll"; - break; - case OPC_SC: - GEN_LOAD_REG_TN(T1, rt); - op_ldst(sc); - GEN_STORE_TN_REG(rt, T0); - opn = "sc"; - break; - default: - MIPS_INVAL("load/store"); - generate_exception(ctx, EXCP_RI); - return; - } - MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]); -} - -#ifdef MIPS_USES_FPU - -/* Load and store */ -static void gen_flt_ldst (DisasContext *ctx, uint16_t opc, int ft, - int base, int16_t offset) -{ - const unsigned char *opn = "unk"; - - if (base == 0) { - GEN_LOAD_IMM_TN(T0, offset); - } else if (offset == 0) { - gen_op_load_gpr_T0(base); - } else { - gen_op_load_gpr_T0(base); - gen_op_set_T1(offset); - gen_op_add(); - } - /* Don't do NOP if destination is zero: we must perform the actual - * memory access - */ - switch (opc) { - case OPC_LWC1: - op_ldst(lwc1); - GEN_STORE_FTN_FREG(ft, WT0); - opn = "lwc1"; - break; - case OPC_SWC1: - GEN_LOAD_FREG_FTN(WT0, ft); - op_ldst(swc1); - opn = "swc1"; - break; - case OPC_LDC1: - op_ldst(ldc1); - GEN_STORE_FTN_FREG(ft, DT0); - opn = "ldc1"; - break; - case OPC_SDC1: - GEN_LOAD_FREG_FTN(DT0, ft); - op_ldst(sdc1); - opn = "sdc1"; - break; - default: - MIPS_INVAL("float load/store"); - generate_exception(ctx, EXCP_CpU); - return; - } - MIPS_DEBUG("%s %s, %d(%s)", opn, fregnames[ft], offset, regnames[base]); -} -#endif - -/* Arithmetic with immediate operand */ -static void gen_arith_imm (DisasContext *ctx, uint16_t opc, int rt, - int rs, int16_t imm) -{ - uint32_t uimm; - const unsigned char *opn = "unk"; - - if (rt == 0 && opc != OPC_ADDI) { - /* if no destination, treat it as a NOP - * For addi, we must generate the overflow exception when needed. - */ - MIPS_DEBUG("NOP"); - return; - } - if (opc == OPC_ADDI || opc == OPC_ADDIU || - opc == OPC_SLTI || opc == OPC_SLTIU) - uimm = (int32_t)imm; /* Sign extent to 32 bits */ - else - uimm = (uint16_t)imm; - if (opc != OPC_LUI) { - GEN_LOAD_REG_TN(T0, rs); - GEN_LOAD_IMM_TN(T1, uimm); - } else { - uimm = uimm << 16; - GEN_LOAD_IMM_TN(T0, uimm); - } - switch (opc) { - case OPC_ADDI: - save_cpu_state(ctx, 1); - gen_op_addo(); - opn = "addi"; - break; - case OPC_ADDIU: - gen_op_add(); - opn = "addiu"; - break; - case OPC_SLTI: - gen_op_lt(); - opn = "slti"; - break; - case OPC_SLTIU: - gen_op_ltu(); - opn = "sltiu"; - break; - case OPC_ANDI: - gen_op_and(); - opn = "andi"; - break; - case OPC_ORI: - gen_op_or(); - opn = "ori"; - break; - case OPC_XORI: - gen_op_xor(); - opn = "xori"; - break; - case OPC_LUI: - opn = "lui"; - break; - case OPC_SLL: - gen_op_sll(); - opn = "sll"; - break; - case OPC_SRA: - gen_op_sra(); - opn = "sra"; - break; - case OPC_SRL: - gen_op_srl(); - opn = "srl"; - break; - default: - MIPS_INVAL("imm arith"); - generate_exception(ctx, EXCP_RI); - return; - } - GEN_STORE_TN_REG(rt, T0); - MIPS_DEBUG("%s %s, %s, %x", opn, regnames[rt], regnames[rs], uimm); -} - -/* Arithmetic */ -static void gen_arith (DisasContext *ctx, uint16_t opc, - int rd, int rs, int rt) -{ - const unsigned char *opn = "unk"; - - if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB) { - /* if no destination, treat it as a NOP - * For add & sub, we must generate the overflow exception when needed. - */ - MIPS_DEBUG("NOP"); - return; - } - GEN_LOAD_REG_TN(T0, rs); - GEN_LOAD_REG_TN(T1, rt); - switch (opc) { - case OPC_ADD: - save_cpu_state(ctx, 1); - gen_op_addo(); - opn = "add"; - break; - case OPC_ADDU: - gen_op_add(); - opn = "addu"; - break; - case OPC_SUB: - save_cpu_state(ctx, 1); - gen_op_subo(); - opn = "sub"; - break; - case OPC_SUBU: - gen_op_sub(); - opn = "subu"; - break; - case OPC_SLT: - gen_op_lt(); - opn = "slt"; - break; - case OPC_SLTU: - gen_op_ltu(); - opn = "sltu"; - break; - case OPC_AND: - gen_op_and(); - opn = "and"; - break; - case OPC_NOR: - gen_op_nor(); - opn = "nor"; - break; - case OPC_OR: - gen_op_or(); - opn = "or"; - break; - case OPC_XOR: - gen_op_xor(); - opn = "xor"; - break; - case OPC_MUL: - gen_op_mul(); - opn = "mul"; - break; - case OPC_MOVN: - gen_op_movn(rd); - opn = "movn"; - goto print; - case OPC_MOVZ: - gen_op_movz(rd); - opn = "movz"; - goto print; - case OPC_SLLV: - gen_op_sllv(); - opn = "sllv"; - break; - case OPC_SRAV: - gen_op_srav(); - opn = "srav"; - break; - case OPC_SRLV: - gen_op_srlv(); - opn = "srlv"; - break; - default: - MIPS_INVAL("arith"); - generate_exception(ctx, EXCP_RI); - return; - } - GEN_STORE_TN_REG(rd, T0); - print: - MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); -} - -/* Arithmetic on HI/LO registers */ -static void gen_HILO (DisasContext *ctx, uint16_t opc, int reg) -{ - const unsigned char *opn = "unk"; - - if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) { - /* Treat as a NOP */ - MIPS_DEBUG("NOP"); - return; - } - switch (opc) { - case OPC_MFHI: - gen_op_load_HI(); - GEN_STORE_TN_REG(reg, T0); - opn = "mfhi"; - break; - case OPC_MFLO: - gen_op_load_LO(); - GEN_STORE_TN_REG(reg, T0); - opn = "mflo"; - break; - case OPC_MTHI: - GEN_LOAD_REG_TN(T0, reg); - gen_op_store_HI(); - opn = "mthi"; - break; - case OPC_MTLO: - GEN_LOAD_REG_TN(T0, reg); - gen_op_store_LO(); - opn = "mtlo"; - break; - default: - MIPS_INVAL("HILO"); - generate_exception(ctx, EXCP_RI); - return; - } - MIPS_DEBUG("%s %s", opn, regnames[reg]); -} - -static void gen_muldiv (DisasContext *ctx, uint16_t opc, - int rs, int rt) -{ - const unsigned char *opn = "unk"; - - GEN_LOAD_REG_TN(T0, rs); - GEN_LOAD_REG_TN(T1, rt); - switch (opc) { - case OPC_DIV: - gen_op_div(); - opn = "div"; - break; - case OPC_DIVU: - gen_op_divu(); - opn = "divu"; - break; - case OPC_MULT: - gen_op_mult(); - opn = "mult"; - break; - case OPC_MULTU: - gen_op_multu(); - opn = "multu"; - break; - case OPC_MADD: - gen_op_madd(); - opn = "madd"; - break; - case OPC_MADDU: - gen_op_maddu(); - opn = "maddu"; - break; - case OPC_MSUB: - gen_op_msub(); - opn = "msub"; - break; - case OPC_MSUBU: - gen_op_msubu(); - opn = "msubu"; - break; - default: - MIPS_INVAL("mul/div"); - generate_exception(ctx, EXCP_RI); - return; - } - MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]); -} - -static void gen_cl (DisasContext *ctx, uint16_t opc, - int rd, int rs) -{ - const unsigned char *opn = "unk"; - if (rd == 0) { - /* Treat as a NOP */ - MIPS_DEBUG("NOP"); - return; - } - GEN_LOAD_REG_TN(T0, rs); - switch (opc) { - case OPC_CLO: - /* CLO */ - gen_op_clo(); - opn = "clo"; - break; - case OPC_CLZ: - /* CLZ */ - gen_op_clz(); - opn = "clz"; - break; - default: - MIPS_INVAL("CLx"); - generate_exception(ctx, EXCP_RI); - return; - } - gen_op_store_T0_gpr(rd); - MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]); -} - -/* Traps */ -static void gen_trap (DisasContext *ctx, uint16_t opc, - int rs, int rt, int16_t imm) -{ - int cond; - - cond = 0; - /* Load needed operands */ - switch (opc) { - case OPC_TEQ: - case OPC_TGE: - case OPC_TGEU: - case OPC_TLT: - case OPC_TLTU: - case OPC_TNE: - /* Compare two registers */ - if (rs != rt) { - GEN_LOAD_REG_TN(T0, rs); - GEN_LOAD_REG_TN(T1, rt); - cond = 1; - } - case OPC_TEQI: - case OPC_TGEI: - case OPC_TGEIU: - case OPC_TLTI: - case OPC_TLTIU: - case OPC_TNEI: - /* Compare register to immediate */ - if (rs != 0 || imm != 0) { - GEN_LOAD_REG_TN(T0, rs); - GEN_LOAD_IMM_TN(T1, (int32_t)imm); - cond = 1; - } - break; - } - if (cond == 0) { - switch (opc) { - case OPC_TEQ: /* rs == rs */ - case OPC_TEQI: /* r0 == 0 */ - case OPC_TGE: /* rs >= rs */ - case OPC_TGEI: /* r0 >= 0 */ - case OPC_TGEU: /* rs >= rs unsigned */ - case OPC_TGEIU: /* r0 >= 0 unsigned */ - /* Always trap */ - gen_op_set_T0(1); - break; - case OPC_TLT: /* rs < rs */ - case OPC_TLTI: /* r0 < 0 */ - case OPC_TLTU: /* rs < rs unsigned */ - case OPC_TLTIU: /* r0 < 0 unsigned */ - case OPC_TNE: /* rs != rs */ - case OPC_TNEI: /* r0 != 0 */ - /* Never trap: treat as NOP */ - return; - default: - MIPS_INVAL("TRAP"); - generate_exception(ctx, EXCP_RI); - return; - } - } else { - switch (opc) { - case OPC_TEQ: - case OPC_TEQI: - gen_op_eq(); - break; - case OPC_TGE: - case OPC_TGEI: - gen_op_ge(); - break; - case OPC_TGEU: - case OPC_TGEIU: - gen_op_geu(); - break; - case OPC_TLT: - case OPC_TLTI: - gen_op_lt(); - break; - case OPC_TLTU: - case OPC_TLTIU: - gen_op_ltu(); - break; - case OPC_TNE: - case OPC_TNEI: - gen_op_ne(); - break; - default: - MIPS_INVAL("TRAP"); - generate_exception(ctx, EXCP_RI); - return; - } - } - save_cpu_state(ctx, 1); - gen_op_trap(); - ctx->bstate = BS_STOP; -} - -static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) -{ - TranslationBlock *tb; - tb = ctx->tb; - if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) { - if (n == 0) - gen_op_goto_tb0(TBPARAM(tb)); - else - gen_op_goto_tb1(TBPARAM(tb)); - gen_op_save_pc(dest); - gen_op_set_T0((long)tb + n); - gen_op_exit_tb(); - } else { - gen_op_save_pc(dest); - gen_op_set_T0(0); - gen_op_exit_tb(); - } -} - -/* Branches (before delay slot) */ -static void gen_compute_branch (DisasContext *ctx, uint16_t opc, - int rs, int rt, int32_t offset) -{ - target_ulong btarget; - int blink, bcond; - - btarget = -1; - blink = 0; - bcond = 0; - /* Load needed operands */ - switch (opc) { - case OPC_BEQ: - case OPC_BEQL: - case OPC_BNE: - case OPC_BNEL: - /* Compare two registers */ - if (rs != rt) { - GEN_LOAD_REG_TN(T0, rs); - GEN_LOAD_REG_TN(T1, rt); - bcond = 1; - } - btarget = ctx->pc + 4 + offset; - break; - case OPC_BGEZ: - case OPC_BGEZAL: - case OPC_BGEZALL: - case OPC_BGEZL: - case OPC_BGTZ: - case OPC_BGTZL: - case OPC_BLEZ: - case OPC_BLEZL: - case OPC_BLTZ: - case OPC_BLTZAL: - case OPC_BLTZALL: - case OPC_BLTZL: - /* Compare to zero */ - if (rs != 0) { - gen_op_load_gpr_T0(rs); - bcond = 1; - } - btarget = ctx->pc + 4 + offset; - break; - case OPC_J: - case OPC_JAL: - /* Jump to immediate */ - btarget = ((ctx->pc + 4) & 0xF0000000) | offset; - break; - case OPC_JR: - case OPC_JALR: - /* Jump to register */ - if (offset != 0) { - /* Only hint = 0 is valid */ - generate_exception(ctx, EXCP_RI); - return; - } - GEN_LOAD_REG_TN(T2, rs); - break; - default: - MIPS_INVAL("branch/jump"); - generate_exception(ctx, EXCP_RI); - return; - } - if (bcond == 0) { - /* No condition to be computed */ - switch (opc) { - case OPC_BEQ: /* rx == rx */ - case OPC_BEQL: /* rx == rx likely */ - case OPC_BGEZ: /* 0 >= 0 */ - case OPC_BGEZL: /* 0 >= 0 likely */ - case OPC_BLEZ: /* 0 <= 0 */ - case OPC_BLEZL: /* 0 <= 0 likely */ - /* Always take */ - ctx->hflags |= MIPS_HFLAG_B; - MIPS_DEBUG("balways"); - break; - case OPC_BGEZAL: /* 0 >= 0 */ - case OPC_BGEZALL: /* 0 >= 0 likely */ - /* Always take and link */ - blink = 31; - ctx->hflags |= MIPS_HFLAG_B; - MIPS_DEBUG("balways and link"); - break; - case OPC_BNE: /* rx != rx */ - case OPC_BGTZ: /* 0 > 0 */ - case OPC_BLTZ: /* 0 < 0 */ - /* Treated as NOP */ - MIPS_DEBUG("bnever (NOP)"); - return; - case OPC_BLTZAL: /* 0 < 0 */ - gen_op_set_T0(ctx->pc + 8); - gen_op_store_T0_gpr(31); - return; - case OPC_BLTZALL: /* 0 < 0 likely */ - gen_op_set_T0(ctx->pc + 8); - gen_op_store_T0_gpr(31); - gen_goto_tb(ctx, 0, ctx->pc + 4); - return; - case OPC_BNEL: /* rx != rx likely */ - case OPC_BGTZL: /* 0 > 0 likely */ - case OPC_BLTZL: /* 0 < 0 likely */ - /* Skip the instruction in the delay slot */ - MIPS_DEBUG("bnever and skip"); - gen_goto_tb(ctx, 0, ctx->pc + 4); - return; - case OPC_J: - ctx->hflags |= MIPS_HFLAG_B; - MIPS_DEBUG("j %08x", btarget); - break; - case OPC_JAL: - blink = 31; - ctx->hflags |= MIPS_HFLAG_B; - MIPS_DEBUG("jal %08x", btarget); - break; - case OPC_JR: - ctx->hflags |= MIPS_HFLAG_BR; - MIPS_DEBUG("jr %s", regnames[rs]); - break; - case OPC_JALR: - blink = rt; - ctx->hflags |= MIPS_HFLAG_BR; - MIPS_DEBUG("jalr %s, %s", regnames[rt], regnames[rs]); - break; - default: - MIPS_INVAL("branch/jump"); - generate_exception(ctx, EXCP_RI); - return; - } - } else { - switch (opc) { - case OPC_BEQ: - gen_op_eq(); - MIPS_DEBUG("beq %s, %s, %08x", - regnames[rs], regnames[rt], btarget); - goto not_likely; - case OPC_BEQL: - gen_op_eq(); - MIPS_DEBUG("beql %s, %s, %08x", - regnames[rs], regnames[rt], btarget); - goto likely; - case OPC_BNE: - gen_op_ne(); - MIPS_DEBUG("bne %s, %s, %08x", - regnames[rs], regnames[rt], btarget); - goto not_likely; - case OPC_BNEL: - gen_op_ne(); - MIPS_DEBUG("bnel %s, %s, %08x", - regnames[rs], regnames[rt], btarget); - goto likely; - case OPC_BGEZ: - gen_op_gez(); - MIPS_DEBUG("bgez %s, %08x", regnames[rs], btarget); - goto not_likely; - case OPC_BGEZL: - gen_op_gez(); - MIPS_DEBUG("bgezl %s, %08x", regnames[rs], btarget); - goto likely; - case OPC_BGEZAL: - gen_op_gez(); - MIPS_DEBUG("bgezal %s, %08x", regnames[rs], btarget); - blink = 31; - goto not_likely; - case OPC_BGEZALL: - gen_op_gez(); - blink = 31; - MIPS_DEBUG("bgezall %s, %08x", regnames[rs], btarget); - goto likely; - case OPC_BGTZ: - gen_op_gtz(); - MIPS_DEBUG("bgtz %s, %08x", regnames[rs], btarget); - goto not_likely; - case OPC_BGTZL: - gen_op_gtz(); - MIPS_DEBUG("bgtzl %s, %08x", regnames[rs], btarget); - goto likely; - case OPC_BLEZ: - gen_op_lez(); - MIPS_DEBUG("blez %s, %08x", regnames[rs], btarget); - goto not_likely; - case OPC_BLEZL: - gen_op_lez(); - MIPS_DEBUG("blezl %s, %08x", regnames[rs], btarget); - goto likely; - case OPC_BLTZ: - gen_op_ltz(); - MIPS_DEBUG("bltz %s, %08x", regnames[rs], btarget); - goto not_likely; - case OPC_BLTZL: - gen_op_ltz(); - MIPS_DEBUG("bltzl %s, %08x", regnames[rs], btarget); - goto likely; - case OPC_BLTZAL: - gen_op_ltz(); - blink = 31; - MIPS_DEBUG("bltzal %s, %08x", regnames[rs], btarget); - not_likely: - ctx->hflags |= MIPS_HFLAG_BC; - break; - case OPC_BLTZALL: - gen_op_ltz(); - blink = 31; - MIPS_DEBUG("bltzall %s, %08x", regnames[rs], btarget); - likely: - ctx->hflags |= MIPS_HFLAG_BL; - break; - } - gen_op_set_bcond(); - } - MIPS_DEBUG("enter ds: link %d cond %02x target %08x", - blink, ctx->hflags, btarget); - ctx->btarget = btarget; - if (blink > 0) { - gen_op_set_T0(ctx->pc + 8); - gen_op_store_T0_gpr(blink); - } - return; -} - -/* CP0 (MMU and control) */ -static void gen_cp0 (DisasContext *ctx, uint16_t opc, int rt, int rd) -{ - const unsigned char *opn = "unk"; - - if (!(ctx->CP0_Status & (1 << CP0St_CU0)) && - (ctx->hflags & MIPS_HFLAG_UM) && - !(ctx->hflags & MIPS_HFLAG_ERL) && - !(ctx->hflags & MIPS_HFLAG_EXL)) { - if (loglevel & CPU_LOG_TB_IN_ASM) { - fprintf(logfile, "CP0 is not usable\n"); - } - generate_exception_err (ctx, EXCP_CpU, 0); - return; - } - - switch (opc) { - case OPC_MFC0: - if (rt == 0) { - /* Treat as NOP */ - return; - } - gen_op_mfc0(rd, ctx->opcode & 0x7); - gen_op_store_T0_gpr(rt); - opn = "mfc0"; - break; - case OPC_MTC0: - /* If we get an exception, we want to restart at next instruction */ - ctx->pc += 4; - save_cpu_state(ctx, 1); - ctx->pc -= 4; - GEN_LOAD_REG_TN(T0, rt); - gen_op_mtc0(rd, ctx->opcode & 0x7); - /* Stop translation as we may have switched the execution mode */ - ctx->bstate = BS_STOP; - opn = "mtc0"; - break; -#if defined(MIPS_USES_R4K_TLB) - case OPC_TLBWI: - gen_op_tlbwi(); - opn = "tlbwi"; - break; - case OPC_TLBWR: - gen_op_tlbwr(); - opn = "tlbwr"; - break; - case OPC_TLBP: - gen_op_tlbp(); - opn = "tlbp"; - break; - case OPC_TLBR: - gen_op_tlbr(); - opn = "tlbr"; - break; -#endif - case OPC_ERET: - opn = "eret"; - save_cpu_state(ctx, 0); - gen_op_eret(); - ctx->bstate = BS_EXCP; - break; - case OPC_DERET: - opn = "deret"; - if (!(ctx->hflags & MIPS_HFLAG_DM)) { - generate_exception(ctx, EXCP_RI); - } else { - save_cpu_state(ctx, 0); - gen_op_deret(); - ctx->bstate = BS_EXCP; - } - break; - case OPC_WAIT: - opn = "wait"; - /* If we get an exception, we want to restart at next instruction */ - ctx->pc += 4; - save_cpu_state(ctx, 1); - ctx->pc -= 4; - gen_op_wait(); - ctx->bstate = BS_EXCP; - break; - default: - if (loglevel & CPU_LOG_TB_IN_ASM) { - fprintf(logfile, "Invalid CP0 opcode: %08x %03x %03x %03x\n", - ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F, - ((ctx->opcode >> 16) & 0x1F)); - } - generate_exception(ctx, EXCP_RI); - return; - } - MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd); -} - -#ifdef MIPS_USES_FPU -/* CP1 Branches (before delay slot) */ -static void gen_compute_branch1 (DisasContext *ctx, uint16_t cond, - int32_t offset) -{ - target_ulong btarget; - - btarget = ctx->pc + 4 + offset; - - switch (cond) { - case 0x0000: /* bc1f */ - gen_op_bc1f(); - MIPS_DEBUG("bc1f %08x", btarget); - goto not_likely; - case 0x0002: /* bc1fl */ - gen_op_bc1f(); - MIPS_DEBUG("bc1fl %08x", btarget); - goto likely; - case 0x0001: /* bc1t */ - gen_op_bc1t(); - MIPS_DEBUG("bc1t %08x", btarget); - not_likely: - ctx->hflags |= MIPS_HFLAG_BC; - break; - case 0x0003: /* bc1tl */ - gen_op_bc1t(); - MIPS_DEBUG("bc1tl %08x", btarget); - likely: - ctx->hflags |= MIPS_HFLAG_BL; - break; - default: - MIPS_INVAL("cp1 branch/jump"); - generate_exception(ctx, EXCP_RI); - return; - } - gen_op_set_bcond(); - - MIPS_DEBUG("enter ds: cond %02x target %08x", - ctx->hflags, btarget); - ctx->btarget = btarget; - - return; -} - -/* Coprocessor 1 (FPU) */ -static void gen_cp1 (DisasContext *ctx, uint16_t opc, int rt, int fs) -{ - const unsigned char *opn = "unk"; - - switch (opc) { - case OPC_MFC1: - GEN_LOAD_FREG_FTN(WT0, fs); - gen_op_mfc1(); - GEN_STORE_TN_REG(rt, T0); - opn = "mfc1"; - break; - case OPC_MTC1: - GEN_LOAD_REG_TN(T0, rt); - gen_op_mtc1(); - GEN_STORE_FTN_FREG(fs, WT0); - opn = "mtc1"; - break; - case OPC_CFC1: - if (fs != 0 && fs != 31) { - MIPS_INVAL("cfc1 freg"); - generate_exception(ctx, EXCP_RI); - return; - } - GEN_LOAD_IMM_TN(T1, fs); - gen_op_cfc1(); - GEN_STORE_TN_REG(rt, T0); - opn = "cfc1"; - break; - case OPC_CTC1: - if (fs != 0 && fs != 31) { - MIPS_INVAL("ctc1 freg"); - generate_exception(ctx, EXCP_RI); - return; - } - GEN_LOAD_IMM_TN(T1, fs); - GEN_LOAD_REG_TN(T0, rt); - gen_op_ctc1(); - opn = "ctc1"; - break; - default: - if (loglevel & CPU_LOG_TB_IN_ASM) { - fprintf(logfile, "Invalid CP1 opcode: %08x %03x %03x %03x\n", - ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F, - ((ctx->opcode >> 16) & 0x1F)); - } - generate_exception(ctx, EXCP_RI); - return; - } - MIPS_DEBUG("%s %s %s", opn, regnames[rt], fregnames[fs]); -} - -/* verify if floating point register is valid; an operation is not defined - * if bit 0 of any register specification is set and the FR bit in the - * Status register equals zero, since the register numbers specify an - * even-odd pair of adjacent coprocessor general registers. When the FR bit - * in the Status register equals one, both even and odd register numbers - * are valid. - * - * Multiple float registers can be checked by calling - * CHECK_FR(ctx, freg1 | freg2 | ... | fregN); - */ -#define CHECK_FR(ctx, freg) do { \ - if (!((ctx)->CP0_Status & (1<<CP0St_FR)) && ((freg) & 1)) { \ - generate_exception(ctx, EXCP_RI); \ - return; \ - } \ - } while(0) - -#define FOP(func, fmt) (((fmt) << 21) | (func)) - -static void gen_farith (DisasContext *ctx, int fmt, int ft, int fs, int fd, int func) -{ - const unsigned char *opn = "unk"; - const char *condnames[] = { - "c.f", - "c.un", - "c.eq", - "c.ueq", - "c.olt", - "c.ult", - "c.ole", - "c.ule", - "c.sf", - "c.ngle", - "c.seq", - "c.ngl", - "c.lt", - "c.nge", - "c.le", - "c.ngt", - }; - int binary = 0; - - switch (ctx->opcode & FOP(0x3f, 0x1f)) { - case FOP(0, 17): - CHECK_FR(ctx, fs | ft | fd); - GEN_LOAD_FREG_FTN(DT0, fs); - GEN_LOAD_FREG_FTN(DT1, ft); - gen_op_float_add_d(); - GEN_STORE_FTN_FREG(fd, DT2); - opn = "add.d"; - binary = 1; - break; - case FOP(1, 17): - CHECK_FR(ctx, fs | ft | fd); - GEN_LOAD_FREG_FTN(DT0, fs); - GEN_LOAD_FREG_FTN(DT1, ft); - gen_op_float_sub_d(); - GEN_STORE_FTN_FREG(fd, DT2); - opn = "sub.d"; - binary = 1; - break; - case FOP(2, 17): - CHECK_FR(ctx, fs | ft | fd); - GEN_LOAD_FREG_FTN(DT0, fs); - GEN_LOAD_FREG_FTN(DT1, ft); - gen_op_float_mul_d(); - GEN_STORE_FTN_FREG(fd, DT2); - opn = "mul.d"; - binary = 1; - break; - case FOP(3, 17): - CHECK_FR(ctx, fs | ft | fd); - GEN_LOAD_FREG_FTN(DT0, fs); - GEN_LOAD_FREG_FTN(DT1, ft); - gen_op_float_div_d(); - GEN_STORE_FTN_FREG(fd, DT2); - opn = "div.d"; - binary = 1; - break; - case FOP(4, 17): - CHECK_FR(ctx, fs | fd); - GEN_LOAD_FREG_FTN(DT0, fs); - gen_op_float_sqrt_d(); - GEN_STORE_FTN_FREG(fd, DT2); - opn = "sqrt.d"; - break; - case FOP(5, 17): - CHECK_FR(ctx, fs | fd); - GEN_LOAD_FREG_FTN(DT0, fs); - gen_op_float_abs_d(); - GEN_STORE_FTN_FREG(fd, DT2); - opn = "abs.d"; - break; - case FOP(6, 17): - CHECK_FR(ctx, fs | fd); - GEN_LOAD_FREG_FTN(DT0, fs); - gen_op_float_mov_d(); - GEN_STORE_FTN_FREG(fd, DT2); - opn = "mov.d"; - break; - case FOP(7, 17): - CHECK_FR(ctx, fs | fd); - GEN_LOAD_FREG_FTN(DT0, fs); - gen_op_float_chs_d(); - GEN_STORE_FTN_FREG(fd, DT2); - opn = "neg.d"; - break; - /* 8 - round.l */ - /* 9 - trunc.l */ - /* 10 - ceil.l */ - /* 11 - floor.l */ - case FOP(12, 17): - CHECK_FR(ctx, fs | fd); - GEN_LOAD_FREG_FTN(DT0, fs); - gen_op_float_roundw_d(); - GEN_STORE_FTN_FREG(fd, WT2); - opn = "round.w.d"; - break; - case FOP(13, 17): - CHECK_FR(ctx, fs | fd); - GEN_LOAD_FREG_FTN(DT0, fs); - gen_op_float_truncw_d(); - GEN_STORE_FTN_FREG(fd, WT2); - opn = "trunc.w.d"; - break; - case FOP(14, 17): - CHECK_FR(ctx, fs | fd); - GEN_LOAD_FREG_FTN(DT0, fs); - gen_op_float_ceilw_d(); - GEN_STORE_FTN_FREG(fd, WT2); - opn = "ceil.w.d"; - break; - case FOP(15, 17): - CHECK_FR(ctx, fs | fd); - GEN_LOAD_FREG_FTN(DT0, fs); - gen_op_float_floorw_d(); - GEN_STORE_FTN_FREG(fd, WT2); - opn = "ceil.w.d"; - break; - case FOP(33, 20): /* cvt.d.w */ - CHECK_FR(ctx, fs | fd); - GEN_LOAD_FREG_FTN(WT0, fs); - gen_op_float_cvtd_w(); - GEN_STORE_FTN_FREG(fd, DT2); - opn = "cvt.d.w"; - break; - case FOP(48, 17): - case FOP(49, 17): - case FOP(50, 17): - case FOP(51, 17): - case FOP(52, 17): - case FOP(53, 17): - case FOP(54, 17): - case FOP(55, 17): - case FOP(56, 17): - case FOP(57, 17): - case FOP(58, 17): - case FOP(59, 17): - case FOP(60, 17): - case FOP(61, 17): - case FOP(62, 17): - case FOP(63, 17): - CHECK_FR(ctx, fs | ft); - GEN_LOAD_FREG_FTN(DT0, fs); - GEN_LOAD_FREG_FTN(DT1, ft); - gen_cmp_d(func-48); - opn = condnames[func-48]; - break; - case FOP(0, 16): - CHECK_FR(ctx, fs | ft | fd); - GEN_LOAD_FREG_FTN(WT0, fs); - GEN_LOAD_FREG_FTN(WT1, ft); - gen_op_float_add_s(); - GEN_STORE_FTN_FREG(fd, WT2); - opn = "add.s"; - binary = 1; - break; - case FOP(1, 16): - CHECK_FR(ctx, fs | ft | fd); - GEN_LOAD_FREG_FTN(WT0, fs); - GEN_LOAD_FREG_FTN(WT1, ft); - gen_op_float_sub_s(); - GEN_STORE_FTN_FREG(fd, WT2); - opn = "sub.s"; - binary = 1; - break; - case FOP(2, 16): - CHECK_FR(ctx, fs | ft | fd); - GEN_LOAD_FREG_FTN(WT0, fs); - GEN_LOAD_FREG_FTN(WT1, ft); - gen_op_float_mul_s(); - GEN_STORE_FTN_FREG(fd, WT2); - opn = "mul.s"; - binary = 1; - break; - case FOP(3, 16): - CHECK_FR(ctx, fs | ft | fd); - GEN_LOAD_FREG_FTN(WT0, fs); - GEN_LOAD_FREG_FTN(WT1, ft); - gen_op_float_div_s(); - GEN_STORE_FTN_FREG(fd, WT2); - opn = "div.s"; - binary = 1; - break; - case FOP(4, 16): - CHECK_FR(ctx, fs | fd); - GEN_LOAD_FREG_FTN(WT0, fs); - gen_op_float_sqrt_s(); - GEN_STORE_FTN_FREG(fd, WT2); - opn = "sqrt.s"; - break; - case FOP(5, 16): - CHECK_FR(ctx, fs | fd); - GEN_LOAD_FREG_FTN(WT0, fs); - gen_op_float_abs_s(); - GEN_STORE_FTN_FREG(fd, WT2); - opn = "abs.s"; - break; - case FOP(6, 16): - CHECK_FR(ctx, fs | fd); - GEN_LOAD_FREG_FTN(WT0, fs); - gen_op_float_mov_s(); - GEN_STORE_FTN_FREG(fd, WT2); - opn = "mov.s"; - break; - case FOP(7, 16): - CHECK_FR(ctx, fs | fd); - GEN_LOAD_FREG_FTN(WT0, fs); - gen_op_float_chs_s(); - GEN_STORE_FTN_FREG(fd, WT2); - opn = "neg.s"; - break; - case FOP(12, 16): - CHECK_FR(ctx, fs | fd); - GEN_LOAD_FREG_FTN(WT0, fs); - gen_op_float_roundw_s(); - GEN_STORE_FTN_FREG(fd, WT2); - opn = "round.w.s"; - break; - case FOP(13, 16): - CHECK_FR(ctx, fs | fd); - GEN_LOAD_FREG_FTN(WT0, fs); - gen_op_float_truncw_s(); - GEN_STORE_FTN_FREG(fd, WT2); - opn = "trunc.w.s"; - break; - case FOP(32, 20): /* cvt.s.w */ - CHECK_FR(ctx, fs | fd); - GEN_LOAD_FREG_FTN(WT0, fs); - gen_op_float_cvts_w(); - GEN_STORE_FTN_FREG(fd, WT2); - opn = "cvt.s.w"; - break; - case FOP(36, 16): /* cvt.w.s */ - CHECK_FR(ctx, fs | fd); - GEN_LOAD_FREG_FTN(WT0, fs); - gen_op_float_cvtw_s(); - GEN_STORE_FTN_FREG(fd, WT2); - opn = "cvt.w.s"; - break; - case FOP(36, 17): /* cvt.w.d */ - CHECK_FR(ctx, fs | fd); - GEN_LOAD_FREG_FTN(WT0, fs); - gen_op_float_cvtw_d(); - GEN_STORE_FTN_FREG(fd, WT2); - opn = "cvt.w.d"; - break; - case FOP(48, 16): - case FOP(49, 16): - case FOP(50, 16): - case FOP(51, 16): - case FOP(52, 16): - case FOP(53, 16): - case FOP(54, 16): - case FOP(55, 16): - case FOP(56, 16): - case FOP(57, 16): - case FOP(58, 16): - case FOP(59, 16): - case FOP(60, 16): - case FOP(61, 16): - case FOP(62, 16): - case FOP(63, 16): - CHECK_FR(ctx, fs | ft); - GEN_LOAD_FREG_FTN(WT0, fs); - GEN_LOAD_FREG_FTN(WT1, ft); - gen_cmp_s(func-48); - opn = condnames[func-48]; - break; - default: - if (loglevel & CPU_LOG_TB_IN_ASM) { - fprintf(logfile, "Invalid arith function: %08x %03x %03x %03x\n", - ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F, - ((ctx->opcode >> 16) & 0x1F)); - } - generate_exception(ctx, EXCP_RI); - return; - } - if (binary) - MIPS_DEBUG("%s %s, %s, %s", opn, fregnames[fd], fregnames[fs], fregnames[ft]); - else - MIPS_DEBUG("%s %s,%s", opn, fregnames[fd], fregnames[fs]); -} -#endif - -/* ISA extensions */ -/* MIPS16 extension to MIPS32 */ -/* SmartMIPS extension to MIPS32 */ - -#ifdef TARGET_MIPS64 -static void gen_arith64 (DisasContext *ctx, uint16_t opc) -{ - if (func == 0x02 && rd == 0) { - /* NOP */ - return; - } - if (rs == 0 || rt == 0) { - gen_op_reset_T0(); - gen_op_save64(); - } else { - gen_op_load_gpr_T0(rs); - gen_op_load_gpr_T1(rt); - gen_op_save64(); - if (func & 0x01) - gen_op_mul64u(); - else - gen_op_mul64s(); - } - if (func & 0x02) - gen_op_add64(); - else - gen_op_sub64(); -} - -/* Coprocessor 3 (FPU) */ - -/* MDMX extension to MIPS64 */ -/* MIPS-3D extension to MIPS64 */ - -#endif - -static void gen_blikely(DisasContext *ctx) -{ - int l1; - l1 = gen_new_label(); - gen_op_jnz_T2(l1); - gen_op_save_state(ctx->hflags & ~MIPS_HFLAG_BMASK); - gen_goto_tb(ctx, 1, ctx->pc + 4); - gen_set_label(l1); -} - -static void decode_opc (DisasContext *ctx) -{ - int32_t offset; - int rs, rt, rd, sa; - uint16_t op, op1; - int16_t imm; - - /* make sure instructions are on a word boundary */ - if (ctx->pc & 0x3) { - generate_exception(ctx, EXCP_AdEL); - return; - } - - if ((ctx->hflags & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) { - /* Handle blikely not taken case */ - MIPS_DEBUG("blikely condition (%08x)", ctx->pc + 4); - gen_blikely(ctx); - } - op = ctx->opcode >> 26; - rs = ((ctx->opcode >> 21) & 0x1F); - rt = ((ctx->opcode >> 16) & 0x1F); - rd = ((ctx->opcode >> 11) & 0x1F); - sa = ((ctx->opcode >> 6) & 0x1F); - imm = (int16_t)ctx->opcode; - switch (op) { - case 0x00: /* Special opcode */ - op1 = ctx->opcode & 0x3F; - switch (op1) { - case 0x00: /* Arithmetic with immediate */ - case 0x02 ... 0x03: - gen_arith_imm(ctx, op1 | EXT_SPECIAL, rd, rt, sa); - break; - case 0x04: /* Arithmetic */ - case 0x06 ... 0x07: - case 0x0A ... 0x0B: - case 0x20 ... 0x27: - case 0x2A ... 0x2B: - gen_arith(ctx, op1 | EXT_SPECIAL, rd, rs, rt); - break; - case 0x18 ... 0x1B: /* MULT / DIV */ - gen_muldiv(ctx, op1 | EXT_SPECIAL, rs, rt); - break; - case 0x08 ... 0x09: /* Jumps */ - gen_compute_branch(ctx, op1 | EXT_SPECIAL, rs, rd, sa); - return; - case 0x30 ... 0x34: /* Traps */ - case 0x36: - gen_trap(ctx, op1 | EXT_SPECIAL, rs, rt, -1); - break; - case 0x10: /* Move from HI/LO */ - case 0x12: - gen_HILO(ctx, op1 | EXT_SPECIAL, rd); - break; - case 0x11: - case 0x13: /* Move to HI/LO */ - gen_HILO(ctx, op1 | EXT_SPECIAL, rs); - break; - case 0x0C: /* SYSCALL */ - generate_exception(ctx, EXCP_SYSCALL); - break; - case 0x0D: /* BREAK */ - generate_exception(ctx, EXCP_BREAK); - break; - case 0x0F: /* SYNC */ - /* Treat as a noop */ - break; - case 0x05: /* Pmon entry point */ - gen_op_pmon((ctx->opcode >> 6) & 0x1F); - break; - - case 0x01: /* MOVCI */ -#if defined (MIPS_HAS_MOVCI) - /* XXX */ -#else - /* Not implemented */ - generate_exception_err (ctx, EXCP_CpU, 1); -#endif - break; - -#if defined (TARGET_MIPS64) - case 0x14: /* MIPS64 specific opcodes */ - case 0x16: - case 0x17: - case 0x1C ... 0x1F: - case 0x2C ... 0x2F: - case 0x37: - case 0x39 ... 0x3B: - case 0x3E ... 0x3F: -#endif - default: /* Invalid */ - MIPS_INVAL("special"); - generate_exception(ctx, EXCP_RI); - break; - } - break; - case 0x1C: /* Special2 opcode */ - op1 = ctx->opcode & 0x3F; - switch (op1) { -#if defined (MIPS_USES_R4K_EXT) - /* Those instructions are not part of MIPS32 core */ - case 0x00 ... 0x01: /* Multiply and add/sub */ - case 0x04 ... 0x05: - gen_muldiv(ctx, op1 | EXT_SPECIAL2, rs, rt); - break; - case 0x02: /* MUL */ - gen_arith(ctx, op1 | EXT_SPECIAL2, rd, rs, rt); - break; - case 0x20 ... 0x21: /* CLO / CLZ */ - gen_cl(ctx, op1 | EXT_SPECIAL2, rd, rs); - break; -#endif - case 0x3F: /* SDBBP */ - /* XXX: not clear which exception should be raised - * when in debug mode... - */ - if (!(ctx->hflags & MIPS_HFLAG_DM)) { - generate_exception(ctx, EXCP_DBp); - } else { - generate_exception(ctx, EXCP_DBp); - } - /* Treat as a noop */ - break; - default: /* Invalid */ - MIPS_INVAL("special2"); - generate_exception(ctx, EXCP_RI); - break; - } - break; - case 0x01: /* B REGIMM opcode */ - op1 = ((ctx->opcode >> 16) & 0x1F); - switch (op1) { - case 0x00 ... 0x03: /* REGIMM branches */ - case 0x10 ... 0x13: - gen_compute_branch(ctx, op1 | EXT_REGIMM, rs, -1, imm << 2); - return; - case 0x08 ... 0x0C: /* Traps */ - case 0x0E: - gen_trap(ctx, op1 | EXT_REGIMM, rs, -1, imm); - break; - default: /* Invalid */ - MIPS_INVAL("REGIMM"); - generate_exception(ctx, EXCP_RI); - break; - } - break; - case 0x10: /* CP0 opcode */ - op1 = ((ctx->opcode >> 21) & 0x1F); - switch (op1) { - case 0x00: - case 0x04: - gen_cp0(ctx, op1 | EXT_CP0, rt, rd); - break; - default: - gen_cp0(ctx, (ctx->opcode & 0x3F) | EXT_CP0, rt, rd); - break; - } - break; - case 0x08 ... 0x0F: /* Arithmetic with immediate opcode */ - gen_arith_imm(ctx, op, rt, rs, imm); - break; - case 0x02 ... 0x03: /* Jump */ - offset = (int32_t)(ctx->opcode & 0x03FFFFFF) << 2; - gen_compute_branch(ctx, op, rs, rt, offset); - return; - case 0x04 ... 0x07: /* Branch */ - case 0x14 ... 0x17: - gen_compute_branch(ctx, op, rs, rt, imm << 2); - return; - case 0x20 ... 0x2E: /* Load and stores */ - case 0x30: - case 0x38: - gen_ldst(ctx, op, rt, rs, imm); - break; - case 0x2F: /* Cache operation */ - /* Treat as a noop */ - break; - case 0x33: /* Prefetch */ - /* Treat as a noop */ - break; - case 0x3F: /* HACK */ - break; - - /* Floating point. */ - case 0x31: /* LWC1 */ - case 0x35: /* LDC1 */ - case 0x39: /* SWC1 */ - case 0x3D: /* SDC1 */ -#if defined(MIPS_USES_FPU) - gen_op_cp1_enabled(); - gen_flt_ldst(ctx, op, rt, rs, imm); -#else - generate_exception_err(ctx, EXCP_CpU, 1); -#endif - break; - - case 0x11: /* CP1 opcode */ -#if defined(MIPS_USES_FPU) - gen_op_cp1_enabled(); - op1 = ((ctx->opcode >> 21) & 0x1F); - switch (op1) { - case 0x00: /* mfc1 */ - case 0x02: /* cfc1 */ - case 0x04: /* mtc1 */ - case 0x06: /* ctc1 */ - gen_cp1(ctx, op1 | EXT_CP1, rt, rd); - break; - case 0x08: /* bc */ - gen_compute_branch1(ctx, rt, imm << 2); - return; - case 0x10: /* 16: fmt=single fp */ - case 0x11: /* 17: fmt=double fp */ - case 0x14: /* 20: fmt=32bit fixed */ - case 0x15: /* 21: fmt=64bit fixed */ - gen_farith(ctx, op1, rt, rd, sa, ctx->opcode & 0x3f); - break; - default: - generate_exception_err(ctx, EXCP_RI, 1); - break; - } - break; -#else - generate_exception_err(ctx, EXCP_CpU, 1); -#endif - break; - - /* COP2. */ - case 0x32: /* LWC2 */ - case 0x36: /* LDC2 */ - case 0x3A: /* SWC2 */ - case 0x3E: /* SDC2 */ - case 0x12: /* CP2 opcode */ - /* Not implemented */ - generate_exception_err(ctx, EXCP_CpU, 2); - break; - - case 0x13: /* CP3 opcode */ - /* Not implemented */ - generate_exception_err(ctx, EXCP_CpU, 3); - break; - -#if defined (TARGET_MIPS64) - case 0x18 ... 0x1B: - case 0x27: - case 0x34: - case 0x37: - /* MIPS64 opcodes */ -#endif -#if defined (MIPS_HAS_JALX) - case 0x1D: - /* JALX: not implemented */ -#endif - case 0x1E: - /* ASE specific */ - default: /* Invalid */ - MIPS_INVAL(""); - generate_exception(ctx, EXCP_RI); - break; - } - if (ctx->hflags & MIPS_HFLAG_BMASK) { - int hflags = ctx->hflags; - /* Branches completion */ - ctx->hflags &= ~MIPS_HFLAG_BMASK; - ctx->bstate = BS_BRANCH; - save_cpu_state(ctx, 0); - switch (hflags & MIPS_HFLAG_BMASK) { - case MIPS_HFLAG_B: - /* unconditional branch */ - MIPS_DEBUG("unconditional branch"); - gen_goto_tb(ctx, 0, ctx->btarget); - break; - case MIPS_HFLAG_BL: - /* blikely taken case */ - MIPS_DEBUG("blikely branch taken"); - gen_goto_tb(ctx, 0, ctx->btarget); - break; - case MIPS_HFLAG_BC: - /* Conditional branch */ - MIPS_DEBUG("conditional branch"); - { - int l1; - l1 = gen_new_label(); - gen_op_jnz_T2(l1); - gen_goto_tb(ctx, 1, ctx->pc + 4); - gen_set_label(l1); - gen_goto_tb(ctx, 0, ctx->btarget); - } - break; - case MIPS_HFLAG_BR: - /* unconditional branch to register */ - MIPS_DEBUG("branch to register"); - gen_op_breg(); - break; - default: - MIPS_DEBUG("unknown branch"); - break; - } - } -} - -int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, - int search_pc) -{ - DisasContext ctx, *ctxp = &ctx; - target_ulong pc_start; - uint16_t *gen_opc_end; - int j, lj = -1; - - if (search_pc && loglevel) - fprintf (logfile, "search pc %d\n", search_pc); - - pc_start = tb->pc; - gen_opc_ptr = gen_opc_buf; - gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; - gen_opparam_ptr = gen_opparam_buf; - nb_gen_labels = 0; - ctx.pc = pc_start; - ctx.saved_pc = -1; - ctx.tb = tb; - ctx.bstate = BS_NONE; - /* Restore delay slot state from the tb context. */ - ctx.hflags = tb->flags; - ctx.saved_hflags = ctx.hflags; - if (ctx.hflags & MIPS_HFLAG_BR) { - gen_op_restore_breg_target(); - } else if (ctx.hflags & MIPS_HFLAG_B) { - ctx.btarget = env->btarget; - } else if (ctx.hflags & MIPS_HFLAG_BMASK) { - /* If we are in the delay slot of a conditional branch, - * restore the branch condition from env->bcond to T2 - */ - ctx.btarget = env->btarget; - gen_op_restore_bcond(); - } -#if defined(CONFIG_USER_ONLY) - ctx.mem_idx = 0; -#else - ctx.mem_idx = !((ctx.hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM); -#endif - ctx.CP0_Status = env->CP0_Status; -#ifdef DEBUG_DISAS - if (loglevel & CPU_LOG_TB_CPU) { - fprintf(logfile, "------------------------------------------------\n"); - /* FIXME: This may print out stale hflags from env... */ - cpu_dump_state(env, logfile, fprintf, 0); - } -#endif -#if defined MIPS_DEBUG_DISAS - if (loglevel & CPU_LOG_TB_IN_ASM) - fprintf(logfile, "\ntb %p super %d cond %04x\n", - tb, ctx.mem_idx, ctx.hflags); -#endif - while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) { - if (env->nb_breakpoints > 0) { - for(j = 0; j < env->nb_breakpoints; j++) { - if (env->breakpoints[j] == ctx.pc) { - save_cpu_state(ctxp, 1); - ctx.bstate = BS_BRANCH; - gen_op_debug(); - goto done_generating; - } - } - } - - if (search_pc) { - j = gen_opc_ptr - gen_opc_buf; - if (lj < j) { - lj++; - while (lj < j) - gen_opc_instr_start[lj++] = 0; - } - gen_opc_pc[lj] = ctx.pc; - gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK; - gen_opc_instr_start[lj] = 1; - } - ctx.opcode = ldl_code(ctx.pc); - decode_opc(&ctx); - ctx.pc += 4; - - if (env->singlestep_enabled) - break; - - if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) - break; - -#if defined (MIPS_SINGLE_STEP) - break; -#endif - } - if (env->singlestep_enabled) { - save_cpu_state(ctxp, ctx.bstate == BS_NONE); - gen_op_debug(); - goto done_generating; - } - else if (ctx.bstate != BS_BRANCH && ctx.bstate != BS_EXCP) { - save_cpu_state(ctxp, 0); - gen_goto_tb(&ctx, 0, ctx.pc); - } - gen_op_reset_T0(); - /* Generate the return instruction */ - gen_op_exit_tb(); -done_generating: - *gen_opc_ptr = INDEX_op_end; - if (search_pc) { - j = gen_opc_ptr - gen_opc_buf; - lj++; - while (lj <= j) - gen_opc_instr_start[lj++] = 0; - tb->size = 0; - } else { - tb->size = ctx.pc - pc_start; - } -#ifdef DEBUG_DISAS -#if defined MIPS_DEBUG_DISAS - if (loglevel & CPU_LOG_TB_IN_ASM) - fprintf(logfile, "\n"); -#endif - if (loglevel & CPU_LOG_TB_IN_ASM) { - fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); - target_disas(logfile, pc_start, ctx.pc - pc_start, 0); - fprintf(logfile, "\n"); - } - if (loglevel & CPU_LOG_TB_OP) { - fprintf(logfile, "OP:\n"); - dump_ops(gen_opc_buf, gen_opparam_buf); - fprintf(logfile, "\n"); - } - if (loglevel & CPU_LOG_TB_CPU) { - fprintf(logfile, "---------------- %d %08x\n", ctx.bstate, ctx.hflags); - } -#endif - - return 0; -} - -int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) -{ - return gen_intermediate_code_internal(env, tb, 0); -} - -int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) -{ - return gen_intermediate_code_internal(env, tb, 1); -} - -#ifdef MIPS_USES_FPU -void fpu_dump_state(CPUState *env, FILE *f, - int (*fpu_fprintf)(FILE *f, const char *fmt, ...), - int flags) -{ - int i; - -# define printfpr(fp) do { \ - fpu_fprintf(f, "w:%08x d:%08lx%08lx fd:%g fs:%g\n", \ - (fp)->w[FP_ENDIAN_IDX], (fp)->w[0], (fp)->w[1], (fp)->fd, (fp)->fs[FP_ENDIAN_IDX]); \ - } while(0) - - fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d\n", - env->fcr0, env->fcr31, - (env->CP0_Status & (1<<CP0St_FR)) != 0); - fpu_fprintf(f, "FT0: "); printfpr(&env->ft0); - fpu_fprintf(f, "FT1: "); printfpr(&env->ft1); - fpu_fprintf(f, "FT2: "); printfpr(&env->ft2); - for(i=0; i < 32; i+=2) { - fpu_fprintf(f, "f%02d: ", i); - printfpr(FPR(env, i)); - } - -#undef printfpr -} - -void dump_fpu(CPUState *env) -{ - if (loglevel) { - fprintf(logfile, "pc=0x%08x HI=0x%08x LO=0x%08x ds %04x %08x %d\n", - env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond); - fpu_dump_state(env, logfile, fprintf, 0); - } -} -#endif /* MIPS_USES_FPU */ - -void cpu_dump_state (CPUState *env, FILE *f, - int (*cpu_fprintf)(FILE *f, const char *fmt, ...), - int flags) -{ - uint32_t c0_status; - int i; - - cpu_fprintf(f, "pc=0x%08x HI=0x%08x LO=0x%08x ds %04x %08x %d\n", - env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond); - for (i = 0; i < 32; i++) { - if ((i & 3) == 0) - cpu_fprintf(f, "GPR%02d:", i); - cpu_fprintf(f, " %s %08x", regnames[i], env->gpr[i]); - if ((i & 3) == 3) - cpu_fprintf(f, "\n"); - } - - c0_status = env->CP0_Status; - if (env->hflags & MIPS_HFLAG_UM) - c0_status |= (1 << CP0St_UM); - if (env->hflags & MIPS_HFLAG_ERL) - c0_status |= (1 << CP0St_ERL); - if (env->hflags & MIPS_HFLAG_EXL) - c0_status |= (1 << CP0St_EXL); - - cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x%08x\n", - c0_status, env->CP0_Cause, env->CP0_EPC); - cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%08x\n", - env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); -#ifdef MIPS_USES_FPU - fpu_dump_state(env, f, cpu_fprintf, flags); -#endif -} - -CPUMIPSState *cpu_mips_init (void) -{ - CPUMIPSState *env; - - env = qemu_mallocz(sizeof(CPUMIPSState)); - if (!env) - return NULL; - cpu_exec_init(env); - tlb_flush(env, 1); - /* Minimal init */ - env->PC = 0xBFC00000; -#if defined (MIPS_USES_R4K_TLB) - env->CP0_random = MIPS_TLB_NB - 1; -#endif - env->CP0_Wired = 0; - env->CP0_Config0 = MIPS_CONFIG0; -#if defined (MIPS_CONFIG1) - env->CP0_Config1 = MIPS_CONFIG1; -#endif -#if defined (MIPS_CONFIG2) - env->CP0_Config2 = MIPS_CONFIG2; -#endif -#if defined (MIPS_CONFIG3) - env->CP0_Config3 = MIPS_CONFIG3; -#endif - env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV); - env->CP0_WatchLo = 0; - env->hflags = MIPS_HFLAG_ERL; - /* Count register increments in debug mode, EJTAG version 1 */ - env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); - env->CP0_PRid = MIPS_CPU; - env->exception_index = EXCP_NONE; -#if defined(CONFIG_USER_ONLY) - env->hflags |= MIPS_HFLAG_UM; -#endif -#ifdef MIPS_USES_FPU - env->fcr0 = MIPS_FCR0; -#endif - return env; -} |