diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/android_arm.c | 2 | ||||
| -rw-r--r-- | hw/apic.c | 8 | ||||
| -rw-r--r-- | hw/armv7m.c | 14 | ||||
| -rw-r--r-- | hw/armv7m_nvic.c | 4 | ||||
| -rw-r--r-- | hw/bt-hci-csr.c | 4 | ||||
| -rw-r--r-- | hw/bt-hci.c | 12 | ||||
| -rw-r--r-- | hw/goldfish_pipe.c | 2 | ||||
| -rw-r--r-- | hw/goldfish_timer.c | 30 | ||||
| -rw-r--r-- | hw/goldfish_trace.c | 2 | ||||
| -rw-r--r-- | hw/hw.h | 15 | ||||
| -rw-r--r-- | hw/i8254.c | 12 | ||||
| -rw-r--r-- | hw/mc146818rtc.c | 28 | ||||
| -rw-r--r-- | hw/msmouse.c | 2 | ||||
| -rw-r--r-- | hw/msmouse.h | 2 | ||||
| -rw-r--r-- | hw/pc.c | 26 | ||||
| -rw-r--r-- | hw/usb-ohci.c | 22 |
16 files changed, 90 insertions, 95 deletions
diff --git a/hw/android_arm.c b/hw/android_arm.c index 3b9dc6d..188051b 100644 --- a/hw/android_arm.c +++ b/hw/android_arm.c @@ -79,7 +79,7 @@ static void android_arm_init_(ram_addr_t ram_size, env = cpu_init(cpu_model); register_savevm( "cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load, env ); - ram_offset = qemu_ram_alloc(ram_size); + ram_offset = qemu_ram_alloc(NULL,"android_arm",ram_size); cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); cpu_pic = arm_pic_init_cpu(env); @@ -599,7 +599,7 @@ static uint32_t apic_get_current_count(APICState *s) { int64_t d; uint32_t val; - d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >> + d = (qemu_get_clock_ns(vm_clock) - s->initial_count_load_time) >> s->count_shift; if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { /* periodic */ @@ -806,12 +806,12 @@ static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) int n = index - 0x32; s->lvt[n] = val; if (n == APIC_LVT_TIMER) - apic_timer_update(s, qemu_get_clock(vm_clock)); + apic_timer_update(s, qemu_get_clock_ns(vm_clock)); } break; case 0x38: s->initial_count = val; - s->initial_count_load_time = qemu_get_clock(vm_clock); + s->initial_count_load_time = qemu_get_clock_ns(vm_clock); apic_timer_update(s, s->initial_count_load_time); break; case 0x39: @@ -956,7 +956,7 @@ int apic_init(CPUState *env) cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000, apic_io_memory); } - s->timer = qemu_new_timer(vm_clock, apic_timer, s); + s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s); register_savevm("apic", s->idx, 2, apic_save, apic_load, s); qemu_register_reset(apic_reset, 0, s); diff --git a/hw/armv7m.c b/hw/armv7m.c index 297a3e1..f7636db 100644 --- a/hw/armv7m.c +++ b/hw/armv7m.c @@ -105,13 +105,13 @@ static void bitband_writel(void *opaque, target_phys_addr_t offset, cpu_physical_memory_write(addr, (uint8_t *)&v, 4); } -static CPUReadMemoryFunc *bitband_readfn[] = { +static CPUReadMemoryFunc * const bitband_readfn[] = { bitband_readb, bitband_readw, bitband_readl }; -static CPUWriteMemoryFunc *bitband_writefn[] = { +static CPUWriteMemoryFunc * const bitband_writefn[] = { bitband_writeb, bitband_writew, bitband_writel @@ -192,9 +192,11 @@ qemu_irq *armv7m_init(int flash_size, int sram_size, /* Flash programming is done via the SCU, so pretend it is ROM. */ cpu_register_physical_memory(0, flash_size, - qemu_ram_alloc(flash_size) | IO_MEM_ROM); + qemu_ram_alloc(NULL, "armv7m.flash", + flash_size) | IO_MEM_ROM); cpu_register_physical_memory(0x20000000, sram_size, - qemu_ram_alloc(sram_size) | IO_MEM_RAM); + qemu_ram_alloc(NULL, "armv7m.sram", + sram_size) | IO_MEM_RAM); armv7m_bitband_init(); nvic = qdev_create(NULL, "armv7m_nvic"); @@ -233,8 +235,8 @@ qemu_irq *armv7m_init(int flash_size, int sram_size, space. This stops qemu complaining about executing code outside RAM when returning from an exception. */ cpu_register_physical_memory(0xfffff000, 0x1000, - qemu_ram_alloc(0x1000) | IO_MEM_RAM); - + qemu_ram_alloc(NULL, "armv7m.hack", + 0x1000) | IO_MEM_RAM); return pic; } diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c index f789c78..f732011 100644 --- a/hw/armv7m_nvic.c +++ b/hw/armv7m_nvic.c @@ -64,7 +64,7 @@ static inline int64_t systick_scale(nvic_state *s) static void systick_reload(nvic_state *s, int reset) { if (reset) - s->systick.tick = qemu_get_clock(vm_clock); + s->systick.tick = qemu_get_clock_ns(vm_clock); s->systick.tick += (s->systick.reload + 1) * systick_scale(s); qemu_mod_timer(s->systick.timer, s->systick.tick); } @@ -396,7 +396,7 @@ static void armv7m_nvic_init(SysBusDevice *dev) gic_init(&s->gic); cpu_register_physical_memory(0xe000e000, 0x1000, s->gic.iomemtype); - s->systick.timer = qemu_new_timer(vm_clock, systick_timer_tick, s); + s->systick.timer = qemu_new_timer_ns(vm_clock, systick_timer_tick, s); register_savevm("armv7m_nvic", -1, 1, nvic_save, nvic_load, s); } diff --git a/hw/bt-hci-csr.c b/hw/bt-hci-csr.c index 982577d..65ffa37 100644 --- a/hw/bt-hci-csr.c +++ b/hw/bt-hci-csr.c @@ -88,7 +88,7 @@ static inline void csrhci_fifo_wake(struct csrhci_s *s) } if (s->out_len) - qemu_mod_timer(s->out_tm, qemu_get_clock(vm_clock) + s->baud_delay); + qemu_mod_timer(s->out_tm, qemu_get_clock_ns(vm_clock) + s->baud_delay); } #define csrhci_out_packetz(s, len) memset(csrhci_out_packet(s, len), 0, len) @@ -446,7 +446,7 @@ CharDriverState *uart_hci_init(qemu_irq wakeup) s->hci->evt_recv = csrhci_out_hci_packet_event; s->hci->acl_recv = csrhci_out_hci_packet_acl; - s->out_tm = qemu_new_timer(vm_clock, csrhci_out_tick, s); + s->out_tm = qemu_new_timer_ns(vm_clock, csrhci_out_tick, s); s->pins = qemu_allocate_irqs(csrhci_pins, s, __csrhci_pins); csrhci_reset(s); diff --git a/hw/bt-hci.c b/hw/bt-hci.c index f1ee92c..41df24c 100644 --- a/hw/bt-hci.c +++ b/hw/bt-hci.c @@ -576,7 +576,7 @@ static void bt_hci_inquiry_result(struct bt_hci_s *hci, static void bt_hci_mod_timer_1280ms(QEMUTimer *timer, int period) { - qemu_mod_timer(timer, qemu_get_clock(vm_clock) + + qemu_mod_timer(timer, qemu_get_clock_ns(vm_clock) + muldiv64(period << 7, get_ticks_per_sec(), 100)); } @@ -657,7 +657,7 @@ static void bt_hci_lmp_link_establish(struct bt_hci_s *hci, if (master) { link->acl_mode = acl_active; hci->lm.handle[hci->lm.last_handle].acl_mode_timer = - qemu_new_timer(vm_clock, bt_hci_mode_tick, link); + qemu_new_timer_ns(vm_clock, bt_hci_mode_tick, link); } } @@ -1084,7 +1084,7 @@ static int bt_hci_mode_change(struct bt_hci_s *hci, uint16_t handle, bt_hci_event_status(hci, HCI_SUCCESS); - qemu_mod_timer(link->acl_mode_timer, qemu_get_clock(vm_clock) + + qemu_mod_timer(link->acl_mode_timer, qemu_get_clock_ns(vm_clock) + muldiv64(interval * 625, get_ticks_per_sec(), 1000000)); bt_hci_lmp_mode_change_master(hci, link->link, mode, interval); @@ -2145,10 +2145,10 @@ struct HCIInfo *bt_new_hci(struct bt_scatternet_s *net) { struct bt_hci_s *s = qemu_mallocz(sizeof(struct bt_hci_s)); - s->lm.inquiry_done = qemu_new_timer(vm_clock, bt_hci_inquiry_done, s); - s->lm.inquiry_next = qemu_new_timer(vm_clock, bt_hci_inquiry_next, s); + s->lm.inquiry_done = qemu_new_timer_ns(vm_clock, bt_hci_inquiry_done, s); + s->lm.inquiry_next = qemu_new_timer_ns(vm_clock, bt_hci_inquiry_next, s); s->conn_accept_timer = - qemu_new_timer(vm_clock, bt_hci_conn_accept_timeout, s); + qemu_new_timer_ns(vm_clock, bt_hci_conn_accept_timeout, s); s->evt_packet = bt_hci_evt_packet; s->evt_submit = bt_hci_evt_submit; diff --git a/hw/goldfish_pipe.c b/hw/goldfish_pipe.c index 998ba49..fd31a2b 100644 --- a/hw/goldfish_pipe.c +++ b/hw/goldfish_pipe.c @@ -655,7 +655,7 @@ throttlePipe_init( void* hwpipe, void* svcOpaque, const char* args ) ANEW0(pipe); pingPongPipe_init0(&pipe->pingpong, hwpipe, svcOpaque); - pipe->timer = qemu_new_timer(vm_clock, throttlePipe_timerFunc, pipe); + pipe->timer = qemu_new_timer_ns(vm_clock, throttlePipe_timerFunc, pipe); /* For now, limit to 500 KB/s in both directions */ pipe->sendRate = 1e9 / (500*1024*8); pipe->recvRate = pipe->sendRate; diff --git a/hw/goldfish_timer.c b/hw/goldfish_timer.c index a714b22..567ce2e 100644 --- a/hw/goldfish_timer.c +++ b/hw/goldfish_timer.c @@ -34,16 +34,6 @@ struct timer_state { QEMUTimer *timer; }; -/* Converts nanoseconds into ticks */ -static int64_t ns2tks(int64_t ns) { - return muldiv64(ns, get_ticks_per_sec(), 1000000000); -} - -/* Converts ticks into nanoseconds */ -static int64_t tks2ns(int64_t tks) { - return muldiv64(tks, 1000000000, get_ticks_per_sec()); -} - #define GOLDFISH_TIMER_SAVE_VERSION 1 static void goldfish_timer_save(QEMUFile* f, void* opaque) @@ -53,9 +43,9 @@ static void goldfish_timer_save(QEMUFile* f, void* opaque) qemu_put_be64(f, s->now_ns); /* in case the kernel is in the middle of a timer read */ qemu_put_byte(f, s->armed); if (s->armed) { - int64_t now_tks = qemu_get_clock(vm_clock); - int64_t alarm_tks = ns2tks(s->alarm_low_ns | (int64_t)s->alarm_high_ns << 32); - qemu_put_be64(f, alarm_tks - now_tks); + int64_t now_ns = qemu_get_clock_ns(vm_clock); + int64_t alarm_ns = (s->alarm_low_ns | (int64_t)s->alarm_high_ns << 32); + qemu_put_be64(f, alarm_ns - now_ns); } } @@ -88,7 +78,7 @@ static uint32_t goldfish_timer_read(void *opaque, target_phys_addr_t offset) struct timer_state *s = (struct timer_state *)opaque; switch(offset) { case TIMER_TIME_LOW: - s->now_ns = tks2ns(qemu_get_clock(vm_clock)); + s->now_ns = qemu_get_clock_ns(vm_clock); return s->now_ns; case TIMER_TIME_HIGH: return s->now_ns >> 32; @@ -101,16 +91,16 @@ static uint32_t goldfish_timer_read(void *opaque, target_phys_addr_t offset) static void goldfish_timer_write(void *opaque, target_phys_addr_t offset, uint32_t value_ns) { struct timer_state *s = (struct timer_state *)opaque; - int64_t alarm_tks, now_tks; + int64_t alarm_ns, now_ns; switch(offset) { case TIMER_ALARM_LOW: s->alarm_low_ns = value_ns; - alarm_tks = ns2tks(s->alarm_low_ns | (int64_t)s->alarm_high_ns << 32); - now_tks = qemu_get_clock(vm_clock); - if (alarm_tks <= now_tks) { + alarm_ns = (s->alarm_low_ns | (int64_t)s->alarm_high_ns << 32); + now_ns = qemu_get_clock_ns(vm_clock); + if (alarm_ns <= now_ns) { goldfish_device_set_irq(&s->dev, 0, 1); } else { - qemu_mod_timer(s->timer, alarm_tks); + qemu_mod_timer(s->timer, alarm_ns); s->armed = 1; } break; @@ -251,7 +241,7 @@ void goldfish_timer_and_rtc_init(uint32_t timerbase, int timerirq) { timer_state.dev.base = timerbase; timer_state.dev.irq = timerirq; - timer_state.timer = qemu_new_timer(vm_clock, goldfish_timer_tick, &timer_state); + timer_state.timer = qemu_new_timer_ns(vm_clock, goldfish_timer_tick, &timer_state); goldfish_device_add(&timer_state.dev, goldfish_timer_readfn, goldfish_timer_writefn, &timer_state); register_savevm( "goldfish_timer", 0, GOLDFISH_TIMER_SAVE_VERSION, goldfish_timer_save, goldfish_timer_load, &timer_state); diff --git a/hw/goldfish_trace.c b/hw/goldfish_trace.c index 02f9b8d..9eeb2a4 100644 --- a/hw/goldfish_trace.c +++ b/hw/goldfish_trace.c @@ -16,7 +16,7 @@ #include "qemu_file.h" #include "goldfish_trace.h" #include "sysemu.h" -#include "trace.h" +#include "android-trace.h" #ifdef CONFIG_MEMCHECK #include "memcheck/memcheck.h" #include "memcheck/memcheck_util.h" @@ -37,8 +37,8 @@ typedef int (QEMUFileRateLimit)(void *opaque); * the new actual bandwidth. It should be new_rate if everything goes ok, and * the old rate otherwise */ -typedef size_t (QEMUFileSetRateLimit)(void *opaque, size_t new_rate); -typedef size_t (QEMUFileGetRateLimit)(void *opaque); +typedef int64_t (QEMUFileSetRateLimit)(void *opaque, int64_t new_rate); +typedef int64_t (QEMUFileGetRateLimit)(void *opaque); QEMUFile *qemu_fopen_ops(void *opaque, QEMUFilePutBufferFunc *put_buffer, QEMUFileGetBufferFunc *get_buffer, @@ -47,10 +47,11 @@ QEMUFile *qemu_fopen_ops(void *opaque, QEMUFilePutBufferFunc *put_buffer, QEMUFileSetRateLimit *set_rate_limit, QEMUFileGetRateLimit *get_rate_limit); QEMUFile *qemu_fopen(const char *filename, const char *mode); +QEMUFile *qemu_fdopen(int fd, const char *mode); QEMUFile *qemu_fopen_socket(int fd); QEMUFile *qemu_popen(FILE *popen_file, const char *mode); QEMUFile *qemu_popen_cmd(const char *command, const char *mode); -int qemu_popen_fd(QEMUFile *f); +int qemu_stdio_fd(QEMUFile *f); void qemu_fflush(QEMUFile *f); int qemu_fclose(QEMUFile *f); void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size); @@ -66,7 +67,9 @@ static inline void qemu_put_ubyte(QEMUFile *f, unsigned int v) void qemu_put_be16(QEMUFile *f, unsigned int v); void qemu_put_be32(QEMUFile *f, unsigned int v); void qemu_put_be64(QEMUFile *f, uint64_t v); +#ifdef CONFIG_ANDROID void qemu_put_float(QEMUFile *f, float v); +#endif int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size); int qemu_get_byte(QEMUFile *f); @@ -80,10 +83,12 @@ static inline unsigned int qemu_get_ubyte(QEMUFile *f) unsigned int qemu_get_be16(QEMUFile *f); unsigned int qemu_get_be32(QEMUFile *f); uint64_t qemu_get_be64(QEMUFile *f); +#ifdef CONFIG_ANDROID float qemu_get_float(QEMUFile *f); +#endif int qemu_file_rate_limit(QEMUFile *f); -size_t qemu_file_set_rate_limit(QEMUFile *f, size_t new_rate); -size_t qemu_file_get_rate_limit(QEMUFile *f); +int64_t qemu_file_set_rate_limit(QEMUFile *f, int64_t new_rate); +int64_t qemu_file_get_rate_limit(QEMUFile *f); int qemu_file_has_error(QEMUFile *f); void qemu_file_set_error(QEMUFile *f); @@ -66,7 +66,7 @@ static int pit_get_count(PITChannelState *s) uint64_t d; int counter; - d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ, get_ticks_per_sec()); + d = muldiv64(qemu_get_clock_ns(vm_clock) - s->count_load_time, PIT_FREQ, get_ticks_per_sec()); switch(s->mode) { case 0: case 1: @@ -189,7 +189,7 @@ void pit_set_gate(PITState *pit, int channel, int val) case 5: if (s->gate < val) { /* restart counting on rising edge */ - s->count_load_time = qemu_get_clock(vm_clock); + s->count_load_time = qemu_get_clock_ns(vm_clock); pit_irq_timer_update(s, s->count_load_time); } break; @@ -197,7 +197,7 @@ void pit_set_gate(PITState *pit, int channel, int val) case 3: if (s->gate < val) { /* restart counting on rising edge */ - s->count_load_time = qemu_get_clock(vm_clock); + s->count_load_time = qemu_get_clock_ns(vm_clock); pit_irq_timer_update(s, s->count_load_time); } /* XXX: disable/enable counting */ @@ -228,7 +228,7 @@ static inline void pit_load_count(PITChannelState *s, int val) { if (val == 0) val = 0x10000; - s->count_load_time = qemu_get_clock(vm_clock); + s->count_load_time = qemu_get_clock_ns(vm_clock); s->count = val; pit_irq_timer_update(s, s->count_load_time); } @@ -262,7 +262,7 @@ static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val) if (!(val & 0x10) && !s->status_latched) { /* status latch */ /* XXX: add BCD and null count */ - s->status = (pit_get_out1(s, qemu_get_clock(vm_clock)) << 7) | + s->status = (pit_get_out1(s, qemu_get_clock_ns(vm_clock)) << 7) | (s->rw_mode << 4) | (s->mode << 1) | s->bcd; @@ -492,7 +492,7 @@ PITState *pit_init(int base, qemu_irq irq) s = &pit->channels[0]; /* the timer 0 is connected to an IRQ */ - s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s); + s->irq_timer = qemu_new_timer_ns(vm_clock, pit_irq_timer, s); s->irq = irq; register_savevm("i8254", base, 1, pit_save, pit_load, pit); diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c index f93a3cb..9cf880d 100644 --- a/hw/mc146818rtc.c +++ b/hw/mc146818rtc.c @@ -108,8 +108,8 @@ static void rtc_coalesced_timer_update(RTCState *s) qemu_del_timer(s->coalesced_timer); } else { /* divide each RTC interval to 2 - 8 smaller intervals */ - int c = MIN(s->irq_coalesced, 7) + 1; - int64_t next_clock = qemu_get_clock(vm_clock) + + int c = MIN(s->irq_coalesced, 7) + 1; + int64_t next_clock = qemu_get_clock_ns(vm_clock) + muldiv64(s->period / c, get_ticks_per_sec(), 32768); qemu_mod_timer(s->coalesced_timer, next_clock); } @@ -150,7 +150,7 @@ static void rtc_timer_update(RTCState *s, int64_t current_time) #endif #endif enable_pie = 1; - + if (period_code != 0 && (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie) || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) { @@ -237,7 +237,7 @@ static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) /* UIP bit is read only */ s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | (s->cmos_data[RTC_REG_A] & REG_A_UIP); - rtc_timer_update(s, qemu_get_clock(vm_clock)); + rtc_timer_update(s, qemu_get_clock_ns(vm_clock)); break; case RTC_REG_B: if (data & REG_B_SET) { @@ -251,7 +251,7 @@ static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) } } s->cmos_data[RTC_REG_B] = data; - rtc_timer_update(s, qemu_get_clock(vm_clock)); + rtc_timer_update(s, qemu_get_clock_ns(vm_clock)); break; case RTC_REG_C: case RTC_REG_D: @@ -610,18 +610,18 @@ RTCState *rtc_init_sqw(int base, qemu_irq irq, qemu_irq sqw_irq, int base_year) s->base_year = base_year; rtc_set_date_from_host(s); - s->periodic_timer = qemu_new_timer(vm_clock, + s->periodic_timer = qemu_new_timer_ns(vm_clock, rtc_periodic_timer, s); #ifdef TARGET_I386 if (rtc_td_hack) - s->coalesced_timer = qemu_new_timer(vm_clock, rtc_coalesced_timer, s); + s->coalesced_timer = qemu_new_timer_ns(vm_clock, rtc_coalesced_timer, s); #endif - s->second_timer = qemu_new_timer(vm_clock, + s->second_timer = qemu_new_timer_ns(vm_clock, rtc_update_second, s); - s->second_timer2 = qemu_new_timer(vm_clock, + s->second_timer2 = qemu_new_timer_ns(vm_clock, rtc_update_second2, s); - s->next_second_time = qemu_get_clock(vm_clock) + (get_ticks_per_sec() * 99) / 100; + s->next_second_time = qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() * 99) / 100; qemu_mod_timer(s->second_timer2, s->next_second_time); register_ioport_write(base, 2, 1, cmos_ioport_write, s); @@ -731,14 +731,14 @@ RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, s->base_year = base_year; rtc_set_date_from_host(s); - s->periodic_timer = qemu_new_timer(vm_clock, + s->periodic_timer = qemu_new_timer_ns(vm_clock, rtc_periodic_timer, s); - s->second_timer = qemu_new_timer(vm_clock, + s->second_timer = qemu_new_timer_ns(vm_clock, rtc_update_second, s); - s->second_timer2 = qemu_new_timer(vm_clock, + s->second_timer2 = qemu_new_timer_ns(vm_clock, rtc_update_second2, s); - s->next_second_time = qemu_get_clock(vm_clock) + (get_ticks_per_sec() * 99) / 100; + s->next_second_time = qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() * 99) / 100; qemu_mod_timer(s->second_timer2, s->next_second_time); io_memory = cpu_register_io_memory(rtc_mm_read, rtc_mm_write, s); diff --git a/hw/msmouse.c b/hw/msmouse.c index 69356a5..05f893c 100644 --- a/hw/msmouse.c +++ b/hw/msmouse.c @@ -64,7 +64,7 @@ static void msmouse_chr_close (struct CharDriverState *chr) qemu_free (chr); } -CharDriverState *qemu_chr_open_msmouse(void) +CharDriverState *qemu_chr_open_msmouse(QemuOpts *opts) { CharDriverState *chr; diff --git a/hw/msmouse.h b/hw/msmouse.h index 947afd9..456cb21 100644 --- a/hw/msmouse.h +++ b/hw/msmouse.h @@ -1,2 +1,2 @@ /* msmouse.c */ -CharDriverState *qemu_chr_open_msmouse(void); +CharDriverState *qemu_chr_open_msmouse(QemuOpts *opts); @@ -550,7 +550,7 @@ static void generate_bootsect(target_phys_addr_t option_rom, *p++ = 0x1f; /* pop ds */ *p++ = 0x58; /* pop ax */ *p++ = 0xcb; /* lret */ - + /* Actual code */ *reloc = (p - rom); @@ -910,7 +910,7 @@ static void pc_init1(ram_addr_t ram_size, cpu_model = "qemu32"; #endif } - + for(i = 0; i < smp_cpus; i++) { env = cpu_init(cpu_model); if (!env) { @@ -927,25 +927,23 @@ static void pc_init1(ram_addr_t ram_size, vmport_init(); /* allocate RAM */ - ram_addr = qemu_ram_alloc(0xa0000); + ram_addr = qemu_ram_alloc(NULL, "pc.ram", + below_4g_mem_size + above_4g_mem_size); cpu_register_physical_memory(0, 0xa0000, ram_addr); - - /* Allocate, even though we won't register, so we don't break the - * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000), - * and some bios areas, which will be registered later - */ - ram_addr = qemu_ram_alloc(0x100000 - 0xa0000); - ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000); cpu_register_physical_memory(0x100000, below_4g_mem_size - 0x100000, - ram_addr); + ram_addr + 0x100000); + if (above_4g_mem_size > 0) { + cpu_register_physical_memory(0x100000000ULL, above_4g_mem_size, + ram_addr + below_4g_mem_size); + } #else /* * Allocate a single contiguous RAM so that the goldfish * framebuffer can work well especially when the frame buffer is * large. */ - ram_addr = qemu_ram_alloc(below_4g_mem_size); + ram_addr = qemu_ram_alloc(NULL, "pc.ram", below_4g_mem_size); cpu_register_physical_memory(0, below_4g_mem_size, ram_addr); #endif @@ -975,7 +973,7 @@ static void pc_init1(ram_addr_t ram_size, (bios_size % 65536) != 0) { goto bios_error; } - bios_offset = qemu_ram_alloc(bios_size); + bios_offset = qemu_ram_alloc(NULL, "bios.bin", bios_size); ret = load_image(filename, qemu_get_ram_ptr(bios_offset)); if (ret != bios_size) { bios_error: @@ -995,7 +993,7 @@ static void pc_init1(ram_addr_t ram_size, - option_rom_offset = qemu_ram_alloc(0x20000); + option_rom_offset = qemu_ram_alloc(NULL, "pc.rom", 0x20000); oprom_area_size = 0; cpu_register_physical_memory(0xc0000, 0x20000, option_rom_offset); diff --git a/hw/usb-ohci.c b/hw/usb-ohci.c index 7dd8ed3..d34b85d 100644 --- a/hw/usb-ohci.c +++ b/hw/usb-ohci.c @@ -626,7 +626,7 @@ static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed, starting_frame = OHCI_BM(iso_td.flags, TD_SF); frame_count = OHCI_BM(iso_td.flags, TD_FC); - relative_frame_number = USUB(ohci->frame_number, starting_frame); + relative_frame_number = USUB(ohci->frame_number, starting_frame); #ifdef DEBUG_ISOCH printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n" @@ -640,8 +640,8 @@ static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed, iso_td.flags, iso_td.bp, iso_td.next, iso_td.be, iso_td.offset[0], iso_td.offset[1], iso_td.offset[2], iso_td.offset[3], iso_td.offset[4], iso_td.offset[5], iso_td.offset[6], iso_td.offset[7], - ohci->frame_number, starting_frame, - frame_count, relative_frame_number, + ohci->frame_number, starting_frame, + frame_count, relative_frame_number, OHCI_BM(iso_td.flags, TD_DI), OHCI_BM(iso_td.flags, TD_CC)); #endif @@ -651,7 +651,7 @@ static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed, } else if (relative_frame_number > frame_count) { /* ISO TD expired - retire the TD to the Done Queue and continue with the next ISO TD of the same ED */ - dprintf("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number, + dprintf("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number, frame_count); OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN); ed->head &= ~OHCI_DPTR_MASK; @@ -692,8 +692,8 @@ static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed, start_offset = iso_td.offset[relative_frame_number]; next_offset = iso_td.offset[relative_frame_number + 1]; - if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) || - ((relative_frame_number < frame_count) && + if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) || + ((relative_frame_number < frame_count) && !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) { printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n", start_offset, next_offset); @@ -758,7 +758,7 @@ static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed, if (ret != USB_RET_NODEV) break; } - + if (ret == USB_RET_ASYNC) { return 1; } @@ -1095,7 +1095,7 @@ static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion) /* Generate a SOF event, and set a timer for EOF */ static void ohci_sof(OHCIState *ohci) { - ohci->sof_time = qemu_get_clock(vm_clock); + ohci->sof_time = qemu_get_clock_ns(vm_clock); qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time); ohci_set_interrupt(ohci, OHCI_INTR_SF); } @@ -1179,12 +1179,12 @@ static void ohci_frame_boundary(void *opaque) */ static int ohci_bus_start(OHCIState *ohci) { - ohci->eof_timer = qemu_new_timer(vm_clock, + ohci->eof_timer = qemu_new_timer_ns(vm_clock, ohci_frame_boundary, ohci); if (ohci->eof_timer == NULL) { - fprintf(stderr, "usb-ohci: %s: qemu_new_timer failed\n", ohci->name); + fprintf(stderr, "usb-ohci: %s: qemu_new_timer_ns failed\n", ohci->name); /* TODO: Signal unrecoverable error */ return 0; } @@ -1304,7 +1304,7 @@ static uint32_t ohci_get_frame_remaining(OHCIState *ohci) /* Being in USB operational state guarnatees sof_time was * set already. */ - tks = qemu_get_clock(vm_clock) - ohci->sof_time; + tks = qemu_get_clock_ns(vm_clock) - ohci->sof_time; /* avoid muldiv if possible */ if (tks >= usb_frame_time) |