1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
|
/*
* Software MMU support
*
* Copyright (c) 2003 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
*/
#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
#define DATA_TYPE uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define USUFFIX l
#define DATA_TYPE uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define USUFFIX uw
#define DATA_TYPE uint16_t
#define DATA_STYPE int16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define USUFFIX ub
#define DATA_TYPE uint8_t
#define DATA_STYPE int8_t
#else
#error unsupported data size
#endif
#if ACCESS_TYPE < (NB_MMU_MODES)
#if defined(OUTSIDE_JIT)
/* Dispatch calls to __ldx_outside_jit / __stx_outside_jit, which don't
* expect CPU environment. to be cached in ebp register, but rather uses
* cpu_single_env variable for that purpose.
*/
#define MMUSUFFIX _outside_jit
#else // OUTSIDE_JIT
#define MMUSUFFIX _mmu
#endif // OUTSIDE_JIT
#define CPU_MMU_INDEX ACCESS_TYPE
#elif ACCESS_TYPE == (NB_MMU_MODES)
#define CPU_MMU_INDEX (cpu_mmu_index(env))
#define MMUSUFFIX _mmu
#elif ACCESS_TYPE == (NB_MMU_MODES + 1)
#define CPU_MMU_INDEX (cpu_mmu_index(env))
#define MMUSUFFIX _cmmu
#else
#error invalid ACCESS_TYPE
#endif
#if DATA_SIZE == 8
#define RES_TYPE uint64_t
#else
#define RES_TYPE int
#endif
#if ACCESS_TYPE == (NB_MMU_MODES + 1)
#define ADDR_READ addr_code
#else
#define ADDR_READ addr_read
#endif
#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
(ACCESS_TYPE < NB_MMU_MODES) && defined(ASM_SOFTMMU)
static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
{
int res;
asm volatile ("movl %1, %%edx\n"
"movl %1, %%eax\n"
"shrl %3, %%edx\n"
"andl %4, %%eax\n"
"andl %2, %%edx\n"
"leal %5(%%edx, %%ebp), %%edx\n"
"cmpl (%%edx), %%eax\n"
"movl %1, %%eax\n"
"je 1f\n"
"movl %6, %%edx\n"
"call %7\n"
"movl %%eax, %0\n"
"jmp 2f\n"
"1:\n"
"addl 12(%%edx), %%eax\n"
#if DATA_SIZE == 1
"movzbl (%%eax), %0\n"
#elif DATA_SIZE == 2
"movzwl (%%eax), %0\n"
#elif DATA_SIZE == 4
"movl (%%eax), %0\n"
#else
#error unsupported size
#endif
"2:\n"
: "=r" (res)
: "r" (ptr),
"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
"i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
"m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
"i" (CPU_MMU_INDEX),
"m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
: "%eax", "%ecx", "%edx", "memory", "cc");
return res;
}
#if DATA_SIZE <= 2
static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
{
int res;
asm volatile ("movl %1, %%edx\n"
"movl %1, %%eax\n"
"shrl %3, %%edx\n"
"andl %4, %%eax\n"
"andl %2, %%edx\n"
"leal %5(%%edx, %%ebp), %%edx\n"
"cmpl (%%edx), %%eax\n"
"movl %1, %%eax\n"
"je 1f\n"
"movl %6, %%edx\n"
"call %7\n"
#if DATA_SIZE == 1
"movsbl %%al, %0\n"
#elif DATA_SIZE == 2
"movswl %%ax, %0\n"
#else
#error unsupported size
#endif
"jmp 2f\n"
"1:\n"
"addl 12(%%edx), %%eax\n"
#if DATA_SIZE == 1
"movsbl (%%eax), %0\n"
#elif DATA_SIZE == 2
"movswl (%%eax), %0\n"
#else
#error unsupported size
#endif
"2:\n"
: "=r" (res)
: "r" (ptr),
"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
"i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
"m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
"i" (CPU_MMU_INDEX),
"m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
: "%eax", "%ecx", "%edx", "memory", "cc");
return res;
}
#endif
static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
{
asm volatile ("movl %0, %%edx\n"
"movl %0, %%eax\n"
"shrl %3, %%edx\n"
"andl %4, %%eax\n"
"andl %2, %%edx\n"
"leal %5(%%edx, %%ebp), %%edx\n"
"cmpl (%%edx), %%eax\n"
"movl %0, %%eax\n"
"je 1f\n"
#if DATA_SIZE == 1
"movzbl %b1, %%edx\n"
#elif DATA_SIZE == 2
"movzwl %w1, %%edx\n"
#elif DATA_SIZE == 4
"movl %1, %%edx\n"
#else
#error unsupported size
#endif
"movl %6, %%ecx\n"
"call %7\n"
"jmp 2f\n"
"1:\n"
"addl 8(%%edx), %%eax\n"
#if DATA_SIZE == 1
"movb %b1, (%%eax)\n"
#elif DATA_SIZE == 2
"movw %w1, (%%eax)\n"
#elif DATA_SIZE == 4
"movl %1, (%%eax)\n"
#else
#error unsupported size
#endif
"2:\n"
:
: "r" (ptr),
#if DATA_SIZE == 1
"q" (v),
#else
"r" (v),
#endif
"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
"i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
"m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_write)),
"i" (CPU_MMU_INDEX),
"m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
: "%eax", "%ecx", "%edx", "memory", "cc");
}
#else
/* generic load/store macros */
static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
{
int page_index;
RES_TYPE res;
target_ulong addr;
unsigned long physaddr;
int mmu_idx;
addr = ptr;
page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
mmu_idx = CPU_MMU_INDEX;
if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
(addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
} else {
physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
}
return res;
}
#if DATA_SIZE <= 2
static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
{
int res, page_index;
target_ulong addr;
unsigned long physaddr;
int mmu_idx;
addr = ptr;
page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
mmu_idx = CPU_MMU_INDEX;
if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
(addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
} else {
physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
}
return res;
}
#endif
#if ACCESS_TYPE != (NB_MMU_MODES + 1)
/* generic store macro */
static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
{
int page_index;
target_ulong addr;
unsigned long physaddr;
int mmu_idx;
addr = ptr;
page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
mmu_idx = CPU_MMU_INDEX;
if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write !=
(addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, mmu_idx);
} else {
physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
}
}
#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
#endif /* !asm */
#if ACCESS_TYPE != (NB_MMU_MODES + 1)
#if DATA_SIZE == 8
static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
{
union {
float64 d;
uint64_t i;
} u;
u.i = glue(ldq, MEMSUFFIX)(ptr);
return u.d;
}
static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
{
union {
float64 d;
uint64_t i;
} u;
u.d = v;
glue(stq, MEMSUFFIX)(ptr, u.i);
}
#endif /* DATA_SIZE == 8 */
#if DATA_SIZE == 4
static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
{
union {
float32 f;
uint32_t i;
} u;
u.i = glue(ldl, MEMSUFFIX)(ptr);
return u.f;
}
static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
{
union {
float32 f;
uint32_t i;
} u;
u.f = v;
glue(stl, MEMSUFFIX)(ptr, u.i);
}
#endif /* DATA_SIZE == 4 */
#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
#undef RES_TYPE
#undef DATA_TYPE
#undef DATA_STYPE
#undef SUFFIX
#undef USUFFIX
#undef DATA_SIZE
#undef CPU_MMU_INDEX
#undef MMUSUFFIX
#undef ADDR_READ
|
