summaryrefslogtreecommitdiffstats
path: root/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/Filt_6k_7k_neon.s
diff options
context:
space:
mode:
authorMans Rullgard <mans@mansr.com>2011-04-05 17:40:06 +0300
committerMartin Storsjo <martin@martin.st>2012-01-12 11:14:04 +0200
commitb676a05348e4c516fa8b57e33b10548e6142c3f8 (patch)
tree79cbd20823076300dffa09f7afdb3cfa8d5d4231 /media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/Filt_6k_7k_neon.s
parenta9798d3c1f1c9787975dc0f16e2191da95f2f0da (diff)
downloadframeworks_av-b676a05348e4c516fa8b57e33b10548e6142c3f8.zip
frameworks_av-b676a05348e4c516fa8b57e33b10548e6142c3f8.tar.gz
frameworks_av-b676a05348e4c516fa8b57e33b10548e6142c3f8.tar.bz2
stagefright aacenc/amrwbenc: Remove trailing whitespace
This was applied in AOSP master earlier, in commit b21611e5b0f1797e39e781d91ade023bac87637f, but when merged into the Google internal tree in 88c2d4d26d79384f32a25bd775cf873cb678b12a, none of these changes have been brought in. (The diff of this merge commit and its first parent, d94b71d, is empty.) Therefore, reapply the rest of these changes on the files that still are present in the current version. Change-Id: I645a9b9134769958a11808a06163123d28d83e46
Diffstat (limited to 'media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/Filt_6k_7k_neon.s')
-rw-r--r--media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/Filt_6k_7k_neon.s70
1 files changed, 35 insertions, 35 deletions
diff --git a/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/Filt_6k_7k_neon.s b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/Filt_6k_7k_neon.s
index 5389a1c..14ba828 100644
--- a/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/Filt_6k_7k_neon.s
+++ b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/Filt_6k_7k_neon.s
@@ -13,7 +13,7 @@
@ ** See the License for the specific language governing permissions and
@ ** limitations under the License.
@ */
-@
+@
@**********************************************************************/
@void Filt_6k_7k(
@ Word16 signal[], /* input: signal */
@@ -23,7 +23,7 @@
@***********************************************************************
@ r0 --- signal[]
@ r1 --- lg
-@ r2 --- mem[]
+@ r2 --- mem[]
.section .text
.global Filt_6k_7k_asm
@@ -31,7 +31,7 @@
Filt_6k_7k_asm:
- STMFD r13!, {r0 - r12, r14}
+ STMFD r13!, {r0 - r12, r14}
SUB r13, r13, #240 @ x[L_SUBFR16k + (L_FIR - 1)]
MOV r8, r0 @ copy signal[] address
MOV r5, r2 @ copy mem[] address
@@ -49,7 +49,7 @@ Filt_6k_7k_asm:
- LDR r10, Lable1 @ get fir_7k address
+ LDR r10, Lable1 @ get fir_7k address
MOV r3, r8 @ change myMemCopy to Copy, due to Copy will change r3 content
ADD r6, r13, #60 @ get x[L_FIR - 1] address
MOV r7, r3 @ get signal[i]
@@ -81,9 +81,9 @@ Filt_6k_7k_asm:
MOV r12, r5
@STR r5, [sp, #-4] @ PUSH r5 to stack
@ not use registers: r4, r10, r12, r14, r5
- MOV r4, r13
- MOV r5, #0 @ i = 0
-
+ MOV r4, r13
+ MOV r5, #0 @ i = 0
+
@ r4 --- x[i], r10 ---- fir_6k_7k
VLD1.S16 {Q0, Q1}, [r10]! @fir_6k_7k[0] ~ fir_6k_7k[15]
VLD1.S16 {Q2, Q3}, [r10]! @fir_6k_7k[16] ~ fir_6k_7k[31]
@@ -91,20 +91,20 @@ Filt_6k_7k_asm:
VLD1.S16 {Q4, Q5}, [r4]! @x[0] ~ x[15]
VLD1.S16 {Q6, Q7}, [r4]! @x[16] ~ X[31]
- VLD1.S16 {Q8}, [r4]!
- VMOV.S16 Q15, #0
-
+ VLD1.S16 {Q8}, [r4]!
+ VMOV.S16 Q15, #0
+
LOOP_6K7K:
- VMULL.S16 Q9,D8,D0[0]
- VMULL.S16 Q10,D9,D1[0]
- VMULL.S16 Q11,D9,D0[0]
+ VMULL.S16 Q9,D8,D0[0]
+ VMULL.S16 Q10,D9,D1[0]
+ VMULL.S16 Q11,D9,D0[0]
VMULL.S16 Q12,D10,D1[0]
VEXT.8 Q4,Q4,Q5,#2
VMLAL.S16 Q9,D10,D2[0]
VMLAL.S16 Q10,D11,D3[0]
VMLAL.S16 Q11,D11,D2[0]
- VMLAL.S16 Q12,D12,D3[0]
+ VMLAL.S16 Q12,D12,D3[0]
VEXT.8 Q5,Q5,Q6,#2
VMLAL.S16 Q9,D12,D4[0]
VMLAL.S16 Q10,D13,D5[0]
@@ -115,18 +115,18 @@ LOOP_6K7K:
VMLAL.S16 Q10,D15,D7[0]
VMLAL.S16 Q11,D15,D6[0]
VMLAL.S16 Q12,D16,D7[0]
- VEXT.8 Q7,Q7,Q8,#2
+ VEXT.8 Q7,Q7,Q8,#2
- VMLAL.S16 Q9,D8,D0[1]
+ VMLAL.S16 Q9,D8,D0[1]
VMLAL.S16 Q10,D9,D1[1]
- VEXT.8 Q8,Q8,Q15,#2
- VMLAL.S16 Q11,D9,D0[1]
+ VEXT.8 Q8,Q8,Q15,#2
+ VMLAL.S16 Q11,D9,D0[1]
VMLAL.S16 Q12,D10,D1[1]
VEXT.8 Q4,Q4,Q5,#2
VMLAL.S16 Q9,D10,D2[1]
VMLAL.S16 Q10,D11,D3[1]
VMLAL.S16 Q11,D11,D2[1]
- VMLAL.S16 Q12,D12,D3[1]
+ VMLAL.S16 Q12,D12,D3[1]
VEXT.8 Q5,Q5,Q6,#2
VMLAL.S16 Q9,D12,D4[1]
VMLAL.S16 Q10,D13,D5[1]
@@ -137,18 +137,18 @@ LOOP_6K7K:
VMLAL.S16 Q10,D15,D7[1]
VMLAL.S16 Q11,D15,D6[1]
VMLAL.S16 Q12,D16,D7[1]
- VEXT.8 Q7,Q7,Q8,#2
+ VEXT.8 Q7,Q7,Q8,#2
- VMLAL.S16 Q9,D8,D0[2]
+ VMLAL.S16 Q9,D8,D0[2]
VMLAL.S16 Q10,D9,D1[2]
- VEXT.8 Q8,Q8,Q15,#2
- VMLAL.S16 Q11,D9,D0[2]
+ VEXT.8 Q8,Q8,Q15,#2
+ VMLAL.S16 Q11,D9,D0[2]
VMLAL.S16 Q12,D10,D1[2]
VEXT.8 Q4,Q4,Q5,#2
VMLAL.S16 Q9,D10,D2[2]
VMLAL.S16 Q10,D11,D3[2]
VMLAL.S16 Q11,D11,D2[2]
- VMLAL.S16 Q12,D12,D3[2]
+ VMLAL.S16 Q12,D12,D3[2]
VEXT.8 Q5,Q5,Q6,#2
VMLAL.S16 Q9,D12,D4[2]
VMLAL.S16 Q10,D13,D5[2]
@@ -159,18 +159,18 @@ LOOP_6K7K:
VMLAL.S16 Q10,D15,D7[2]
VMLAL.S16 Q11,D15,D6[2]
VMLAL.S16 Q12,D16,D7[2]
- VEXT.8 Q7,Q7,Q8,#2
+ VEXT.8 Q7,Q7,Q8,#2
- VMLAL.S16 Q9,D8,D0[3]
+ VMLAL.S16 Q9,D8,D0[3]
VMLAL.S16 Q10,D9,D1[3]
- VEXT.8 Q8,Q8,Q15,#2
- VMLAL.S16 Q11,D9,D0[3]
+ VEXT.8 Q8,Q8,Q15,#2
+ VMLAL.S16 Q11,D9,D0[3]
VMLAL.S16 Q12,D10,D1[3]
VEXT.8 Q4,Q4,Q5,#2
VMLAL.S16 Q9,D10,D2[3]
VMLAL.S16 Q10,D11,D3[3]
VMLAL.S16 Q11,D11,D2[3]
- VMLAL.S16 Q12,D12,D3[3]
+ VMLAL.S16 Q12,D12,D3[3]
VEXT.8 Q5,Q5,Q6,#2
VMLAL.S16 Q9,D12,D4[3]
VMLAL.S16 Q10,D13,D5[3]
@@ -181,10 +181,10 @@ LOOP_6K7K:
VMLAL.S16 Q10,D15,D7[3]
VMLAL.S16 Q11,D15,D6[3]
VMLAL.S16 Q12,D16,D7[3]
- VEXT.8 Q7,Q7,Q8,#2
+ VEXT.8 Q7,Q7,Q8,#2
VMOV.S16 D8,D9
- VEXT.8 Q8,Q8,Q15,#2
+ VEXT.8 Q8,Q8,Q15,#2
VMOV.S16 D9,D10
VADD.S32 Q9,Q9,Q10
VMOV.S16 D10,D11
@@ -214,12 +214,12 @@ LOOP_6K7K:
VST1.S16 {D4, D5, D6}, [r1]!
VST1.S16 D7[0], [r1]!
VST1.S16 D7[1], [r1]!
-
+
Filt_6k_7k_end:
- ADD r13, r13, #240
- LDMFD r13!, {r0 - r12, r15}
-
+ ADD r13, r13, #240
+ LDMFD r13!, {r0 - r12, r15}
+
Lable1:
.word fir_6k_7k
@ENDFUNC
generated by cgit v1.1 at 2024-06-11 13:58:14 +0000