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author | Chih-Hung Hsieh <chh@google.com> | 2015-08-19 11:44:57 -0700 |
---|---|---|
committer | Steve Kondik <steve@cyngn.com> | 2016-01-08 21:46:45 -0800 |
commit | 687730892c7bed143df27df76cfb673516a5b6a4 (patch) | |
tree | 4895ca2f379b8e6f2af57f0b45673963724b5f24 /media/libstagefright/codecs/on2/h264dec/source/arm_neon_asm_gcc/h264bsdFillRow7.S | |
parent | 94f3841a5218c0e8d5dd19c3f92e38419f808725 (diff) | |
download | frameworks_av-687730892c7bed143df27df76cfb673516a5b6a4.zip frameworks_av-687730892c7bed143df27df76cfb673516a5b6a4.tar.gz frameworks_av-687730892c7bed143df27df76cfb673516a5b6a4.tar.bz2 |
Use unified syntax to compile with both llvm and gas.
* Remove useless stab debug info directives .func and .endfunc,
which are not recognized by clang/llvm integrated assembler.
* Replace require8 with REQUIRE8, preserve8 with PRESERVE8.
* Replace LDRNESB with LDRSBNE, LDREQSB with LDRSBEQ, etc.
* Replace VST1 {*.U8} with VST1.8 ..., VLD1 {*.U8} with VLD1.8,
and VMOV with VMOV.I8.
* New assembler output code is identical or equivalent to old gas output.
For example, the 3 references of
LDR r7, =0x80808080
in omxdl/arm_neon/vc/m4p10/src_gcc/armVCM4P10_Average_4x_Align_unsafe_s.S
produced 3 instances of
.word 0x80808080
by llvm integrated assembler but only one by gas.
Change-Id: Ifdcd5bee915a7534198d7f219bceab72045f6a22
Diffstat (limited to 'media/libstagefright/codecs/on2/h264dec/source/arm_neon_asm_gcc/h264bsdFillRow7.S')
-rw-r--r-- | media/libstagefright/codecs/on2/h264dec/source/arm_neon_asm_gcc/h264bsdFillRow7.S | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/media/libstagefright/codecs/on2/h264dec/source/arm_neon_asm_gcc/h264bsdFillRow7.S b/media/libstagefright/codecs/on2/h264dec/source/arm_neon_asm_gcc/h264bsdFillRow7.S index 6955b9a..6ed6227 100644 --- a/media/libstagefright/codecs/on2/h264dec/source/arm_neon_asm_gcc/h264bsdFillRow7.S +++ b/media/libstagefright/codecs/on2/h264dec/source/arm_neon_asm_gcc/h264bsdFillRow7.S @@ -16,7 +16,7 @@ #include "asm_common.S" - preserve8 + PRESERVE8 .fpu neon .text @@ -33,12 +33,12 @@ /* -- NEON registers -- */ -#define qTmp0 Q0.U8 -#define qTmp1 Q1.U8 -#define dTmp0 D0.U8 -#define dTmp1 D1.U8 -#define dTmp2 D2.U8 -#define dTmp3 D3.U8 +#define qTmp0 Q0 +#define qTmp1 Q1 +#define dTmp0 D0 +#define dTmp1 D1 +#define dTmp2 D2 +#define dTmp3 D3 /* void h264bsdFillRow7(const u8 * ref, u8 * fill, i32 left, i32 center, @@ -74,40 +74,40 @@ switch_center: B case_8 case_8: - VLD1 {qTmp0, qTmp1}, [ref]! + VLD1.8 {qTmp0, qTmp1}, [ref]! SUB center, center, #32 - VST1 {qTmp0}, [fill]! - VST1 {qTmp1}, [fill]! + VST1.8 {qTmp0}, [fill]! + VST1.8 {qTmp1}, [fill]! B loop_center case_7: - VLD1 {dTmp0,dTmp1,dTmp2}, [ref]! + VLD1.8 {dTmp0,dTmp1,dTmp2}, [ref]! SUB center, center, #28 LDR tmp2, [ref], #4 - VST1 {dTmp0,dTmp1,dTmp2}, [fill]! + VST1.8 {dTmp0,dTmp1,dTmp2}, [fill]! STR tmp2, [fill],#4 B loop_center case_6: - VLD1 {dTmp0,dTmp1,dTmp2}, [ref]! + VLD1.8 {dTmp0,dTmp1,dTmp2}, [ref]! SUB center, center, #24 - VST1 {dTmp0,dTmp1,dTmp2}, [fill]! + VST1.8 {dTmp0,dTmp1,dTmp2}, [fill]! B loop_center case_5: - VLD1 {qTmp0}, [ref]! + VLD1.8 {qTmp0}, [ref]! SUB center, center, #20 LDR tmp2, [ref], #4 - VST1 {qTmp0}, [fill]! + VST1.8 {qTmp0}, [fill]! STR tmp2, [fill],#4 B loop_center case_4: - VLD1 {qTmp0}, [ref]! + VLD1.8 {qTmp0}, [ref]! SUB center, center, #16 - VST1 {qTmp0}, [fill]! + VST1.8 {qTmp0}, [fill]! B loop_center case_3: - VLD1 {dTmp0}, [ref]! + VLD1.8 {dTmp0}, [ref]! SUB center, center, #12 LDR tmp2, [ref], #4 - VST1 dTmp0, [fill]! + VST1.8 dTmp0, [fill]! STR tmp2, [fill],#4 B loop_center case_2: |