diff options
Diffstat (limited to 'media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E')
11 files changed, 2164 insertions, 0 deletions
diff --git a/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/Deemph_32_opt.s b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/Deemph_32_opt.s new file mode 100644 index 0000000..0eb5e9f --- /dev/null +++ b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/Deemph_32_opt.s @@ -0,0 +1,104 @@ +@/*
+@ ** Copyright 2003-2010, VisualOn, Inc.
+@ **
+@ ** Licensed under the Apache License, Version 2.0 (the "License");
+@ ** you may not use this file except in compliance with the License.
+@ ** You may obtain a copy of the License at
+@ **
+@ ** http://www.apache.org/licenses/LICENSE-2.0
+@ **
+@ ** Unless required by applicable law or agreed to in writing, software
+@ ** distributed under the License is distributed on an "AS IS" BASIS,
+@ ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+@ ** See the License for the specific language governing permissions and
+@ ** limitations under the License.
+@ */
+
+@void Deemph_32(
+@ Word16 x_hi[], /* (i) : input signal (bit31..16) */
+@ Word16 x_lo[], /* (i) : input signal (bit15..4) */
+@ Word16 y[], /* (o) : output signal (x16) */
+@ Word16 mu, /* (i) Q15 : deemphasis factor */
+@ Word16 L, /* (i) : vector size */
+@ Word16 * mem /* (i/o) : memory (y[-1]) */
+@ )
+
+@x_hi RN R0
+@x_lo RN R1
+@y[] RN R2
+@*mem RN R3
+
+ .section .text
+ .global Deemph_32_asm
+
+Deemph_32_asm:
+
+ STMFD r13!, {r4 - r12, r14}
+ MOV r4, #2 @i=0
+ LDRSH r6, [r0], #2 @load x_hi[0]
+ LDRSH r7, [r1], #2 @load x_lo[0]
+ LDR r5, =22282 @r5---mu
+ MOV r11, #0x8000
+
+ @y[0]
+ MOV r10, r6, LSL #16 @L_tmp = x_hi[0]<<16
+ MOV r8, r5, ASR #1 @fac = mu >> 1
+ LDR r5, [r3]
+ ADD r12, r10, r7, LSL #4 @L_tmp += x_lo[0] << 4
+ MOV r10, r12, LSL #3 @L_tmp <<= 3
+ MUL r9, r5, r8
+ LDRSH r6, [r0], #2 @load x_hi[1]
+ QDADD r10, r10, r9
+ LDRSH r7, [r1], #2 @load x_lo[1]
+ MOV r12, r10, LSL #1 @L_tmp = L_mac(L_tmp, *mem, fac)
+ QADD r10, r12, r11
+ MOV r14, r10, ASR #16 @y[0] = round(L_tmp)
+
+
+ MOV r10, r6, LSL #16
+ ADD r12, r10, r7, LSL #4
+ STRH r14, [r2], #2 @update y[0]
+ MOV r10, r12, LSL #3
+ MUL r9, r14, r8
+ QDADD r10, r10, r9
+ MOV r12, r10, LSL #1
+ QADD r10, r12, r11
+ MOV r14, r10, ASR #16 @y[1] = round(L_tmp)
+
+LOOP:
+ LDRSH r6, [r0], #2 @load x_hi[]
+ LDRSH r7, [r1], #2
+ STRH r14, [r2], #2
+ MOV r10, r6, LSL #16
+ ADD r12, r10, r7, LSL #4
+ MUL r9, r14, r8
+ MOV r10, r12, LSL #3
+ QDADD r10, r10, r9
+ LDRSH r6, [r0], #2 @load x_hi[]
+ MOV r12, r10, LSL #1
+ QADD r10, r12, r11
+ LDRSH r7, [r1], #2
+ MOV r14, r10, ASR #16
+
+ MOV r10, r6, LSL #16
+ ADD r12, r10, r7, LSL #4
+ STRH r14, [r2], #2
+ MUL r9, r14, r8
+ MOV r10, r12, LSL #3
+ QDADD r10, r10, r9
+ ADD r4, r4, #2
+ MOV r12, r10, LSL #1
+ QADD r10, r12, r11
+ CMP r4, #64
+ MOV r14, r10, ASR #16
+
+ BLT LOOP
+ STR r14, [r3]
+ STRH r14, [r2]
+
+ LDMFD r13!, {r4 - r12, r15}
+
+ @ENDP
+ .END
+
+
diff --git a/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/Dot_p_opt.s b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/Dot_p_opt.s new file mode 100644 index 0000000..0383269 --- /dev/null +++ b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/Dot_p_opt.s @@ -0,0 +1,80 @@ +@/*
+@ ** Copyright 2003-2010, VisualOn, Inc.
+@ **
+@ ** Licensed under the Apache License, Version 2.0 (the "License");
+@ ** you may not use this file except in compliance with the License.
+@ ** You may obtain a copy of the License at
+@ **
+@ ** http://www.apache.org/licenses/LICENSE-2.0
+@ **
+@ ** Unless required by applicable law or agreed to in writing, software
+@ ** distributed under the License is distributed on an "AS IS" BASIS,
+@ ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+@ ** See the License for the specific language governing permissions and
+@ ** limitations under the License.
+@ */
+@
+@Word32 Dot_product12( /* (o) Q31: normalized result (1 < val <= -1) */
+@ Word16 x[], /* (i) 12bits: x vector */
+@ Word16 y[], /* (i) 12bits: y vector */
+@ Word16 lg, /* (i) : vector length */
+@ Word16 * exp /* (o) : exponent of result (0..+30) */
+@)
+@****************************************************************
+@ x[] --- r0
+@ y[] --- r1
+@ lg --- r2
+@ *exp --- r3
+
+ .section .text
+ .global Dot_product12_asm
+
+Dot_product12_asm:
+
+ STMFD r13!, {r4 - r12, r14}
+ MOV r4, #0 @ L_sum = 0
+ MOV r5, #0 @ i = 0
+
+LOOP:
+ LDR r6, [r0], #4
+ LDR r7, [r1], #4
+ LDR r8, [r0], #4
+ SMLABB r4, r6, r7, r4
+ LDR r9, [r1], #4
+ SMLATT r4, r6, r7, r4
+
+ LDR r6, [r0], #4
+ SMLABB r4, r8, r9, r4
+
+ LDR r7, [r1], #4
+ SMLATT r4, r8, r9, r4
+ LDR r8, [r0], #4
+
+ SMLABB r4, r6, r7, r4
+ LDR r9, [r1], #4
+ SMLATT r4, r6, r7, r4
+ ADD r5, r5, #8
+ SMLABB r4, r8, r9, r4
+ CMP r5, r2
+ SMLATT r4, r8, r9, r4
+ BLT LOOP
+
+ MOV r12, r4, LSL #1
+ ADD r12, r12, #1 @ L_sum = (L_sum << 1) + 1
+ MOV r4, r12
+
+ CMP r12, #0
+ RSBLT r4, r12, #0
+ CLZ r10, r4
+ SUB r10, r10, #1 @ sft = norm_l(L_sum)
+ MOV r0, r12, LSL r10 @ L_sum = L_sum << sft
+ RSB r11, r10, #30 @ *exp = 30 - sft
+ STRH r11, [r3]
+
+Dot_product12_end:
+
+ LDMFD r13!, {r4 - r12, r15}
+ @ENDFUNC
+ .END
+
+
diff --git a/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/Filt_6k_7k_opt.s b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/Filt_6k_7k_opt.s new file mode 100644 index 0000000..e6ebd73 --- /dev/null +++ b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/Filt_6k_7k_opt.s @@ -0,0 +1,185 @@ +@/*
+@ ** Copyright 2003-2010, VisualOn, Inc.
+@ **
+@ ** Licensed under the Apache License, Version 2.0 (the "License");
+@ ** you may not use this file except in compliance with the License.
+@ ** You may obtain a copy of the License at
+@ **
+@ ** http://www.apache.org/licenses/LICENSE-2.0
+@ **
+@ ** Unless required by applicable law or agreed to in writing, software
+@ ** distributed under the License is distributed on an "AS IS" BASIS,
+@ ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+@ ** See the License for the specific language governing permissions and
+@ ** limitations under the License.
+@ */
+
+@**********************************************************************/
+@void Filt_6k_7k(
+@ Word16 signal[], /* input: signal */
+@ Word16 lg, /* input: length of input */
+@ Word16 mem[] /* in/out: memory (size=30) */
+@)
+@******************************************************************
+@ r0 --- signal[]
+@ r1 --- lg
+@ r2 --- mem[]
+
+ .section .text
+ .global Filt_6k_7k_asm
+ .extern voAWB_Copy
+ .extern fir_6k_7k
+
+Filt_6k_7k_asm:
+
+ STMFD r13!, {r4 - r12, r14}
+ SUB r13, r13, #240 @ x[L_SUBFR16k + (L_FIR - 1)]
+ MOV r8, r0 @ copy signal[] address
+ MOV r4, r1 @ copy lg address
+ MOV r5, r2 @ copy mem[] address
+
+ MOV r1, r13
+ MOV r0, r2
+ MOV r2, #30 @ L_FIR - 1
+ BL voAWB_Copy @ memcpy(x, mem, (L_FIR - 1)<<1)
+
+ LDR r10, Lable1 @ get fir_7k address
+
+ MOV r14, #0
+ MOV r3, r8 @ change myMemCopy to Copy, due to Copy will change r3 content
+ ADD r6, r13, #60 @ get x[L_FIR - 1] address
+ MOV r7, r3 @ get signal[i]
+LOOP1:
+ LDRSH r8, [r7], #2
+ LDRSH r9, [r7], #2
+ MOV r8, r8, ASR #2
+ MOV r9, r9, ASR #2
+ LDRSH r11, [r7], #2
+ LDRSH r12, [r7], #2
+ MOV r11, r11, ASR #2
+ MOV r12, r12, ASR #2
+ STRH r8, [r6], #2
+ STRH r9, [r6], #2
+ STRH r11, [r6], #2
+ STRH r12, [r6], #2
+ LDRSH r8, [r7], #2
+ LDRSH r9, [r7], #2
+ MOV r8, r8, ASR #2
+ MOV r9, r9, ASR #2
+ LDRSH r11, [r7], #2
+ LDRSH r12, [r7], #2
+ MOV r11, r11, ASR #2
+ MOV r12, r12, ASR #2
+ STRH r8, [r6], #2
+ STRH r9, [r6], #2
+ STRH r11, [r6], #2
+ STRH r12, [r6], #2
+ ADD r14, r14, #8
+ CMP r14, #80
+ BLT LOOP1
+
+
+ STR r5, [sp, #-4] @ PUSH r5 to stack
+
+ @ not use registers: r4, r10, r12, r14, r5
+ MOV r4, r13
+ MOV r5, #0 @ i = 0
+LOOP2:
+ LDR r0, [r10]
+
+ LDRSH r1, [r4] @ load x[i]
+ LDRSH r2, [r4, #60] @ load x[i + 30]
+ LDRSH r6, [r4, #2] @ load x[i + 1]
+ LDRSH r7, [r4, #58] @ load x[i + 29]
+ ADD r1, r1, r2 @ x[i] + x[i + 30]
+ ADD r6, r6, r7 @ x[i + 1] + x[i + 29]
+ LDRSH r8, [r4, #4] @ load x[i + 2]
+ LDRSH r9, [r4, #56] @ load x[i + 28]
+
+ SMULBB r14, r1, r0 @ (x[i] + x[i + 30]) * fir_7k[0]
+ ADD r8, r8, r9 @ x[i + 2] + x[i + 28]
+ SMLABT r14, r6, r0, r14 @ (x[i + 1] + x[i + 29]) * fir_7k[1]
+
+ LDR r0, [r10, #4]
+ LDRSH r1, [r4, #6] @ load x[i+3]
+ LDRSH r2, [r4, #54] @ load x[i+27]
+ LDRSH r6, [r4, #8] @ load x[i+4]
+ LDRSH r7, [r4, #52] @ load x[i+26]
+ ADD r1, r1, r2 @ x[i+3] + x[i+27]
+ ADD r6, r6, r7 @ x[i+4] + x[i+26]
+ SMLABB r14, r8, r0, r14 @ (x[i + 2] + x[i + 28]) * fir_7k[2]
+ LDRSH r8, [r4, #10] @ load x[i+5]
+ LDRSH r9, [r4, #50] @ load x[i+25]
+ SMLABT r14, r1, r0, r14 @ (x[i+3] + x[i+27]) * fir_7k[3]
+ ADD r8, r8, r9 @ x[i+5] + x[i+25]
+
+ LDR r0, [r10, #8]
+ LDRSH r1, [r4, #12] @ x[i+6]
+ LDRSH r2, [r4, #48] @ x[i+24]
+ SMLABB r14, r6, r0, r14 @ (x[i+4] + x[i+26]) * fir_7k[4]
+ LDRSH r6, [r4, #14] @ x[i+7]
+ LDRSH r7, [r4, #46] @ x[i+23]
+ SMLABT r14, r8, r0, r14 @ (x[i+5] + x[i+25]) * fir_7k[5]
+ LDR r0, [r10, #12]
+ ADD r1, r1, r2 @ (x[i+6] + x[i+24])
+ ADD r6, r6, r7 @ (x[i+7] + x[i+23])
+ SMLABB r14, r1, r0, r14 @ (x[i+6] + x[i+24]) * fir_7k[6]
+ LDRSH r8, [r4, #16] @ x[i+8]
+ LDRSH r9, [r4, #44] @ x[i+22]
+ SMLABT r14, r6, r0, r14 @ (x[i+7] + x[i+23]) * fir_7k[7]
+ LDR r0, [r10, #16]
+ LDRSH r1, [r4, #18] @ x[i+9]
+ LDRSH r2, [r4, #42] @ x[i+21]
+ LDRSH r6, [r4, #20] @ x[i+10]
+ LDRSH r7, [r4, #40] @ x[i+20]
+ ADD r8, r8, r9 @ (x[i+8] + x[i+22])
+ ADD r1, r1, r2 @ (x[i+9] + x[i+21])
+ ADD r6, r6, r7 @ (x[i+10] + x[i+20])
+ SMLABB r14, r8, r0, r14 @ (x[i+8] + x[i+22]) * fir_7k[8]
+ LDRSH r8, [r4, #22] @ x[i+11]
+ LDRSH r9, [r4, #38] @ x[i+19]
+ SMLABT r14, r1, r0, r14 @ (x[i+9] + x[i+21]) * fir_7k[9]
+ LDR r0, [r10, #20]
+ LDRSH r1, [r4, #24] @ x[i+12]
+ LDRSH r2, [r4, #36] @ x[i+18]
+ SMLABB r14, r6, r0, r14 @ (x[i+10] + x[i+20]) * fir_7k[10]
+ LDRSH r6, [r4, #26] @ x[i+13]
+ ADD r8, r8, r9 @ (x[i+11] + x[i+19])
+ LDRSH r7, [r4, #34] @ x[i+17]
+ SMLABT r14, r8, r0, r14 @ (x[i+11] + x[i+19]) * fir_7k[11]
+ LDR r0, [r10, #24]
+ ADD r1, r1, r2 @ x[i+12] + x[i+18]
+ LDRSH r8, [r4, #28] @ x[i+14]
+ SMLABB r14, r1, r0, r14 @ (x[i+12] + x[i+18]) * fir_7k[12]
+ ADD r6, r6, r7 @ (x[i+13] + x[i+17])
+ LDRSH r9, [r4, #32] @ x[i+16]
+ SMLABT r14, r6, r0, r14 @ (x[i+13] + x[i+17]) * fir_7k[13]
+ LDR r0, [r10, #28]
+ ADD r8, r8, r9 @ (x[i+14] + x[i+16])
+ LDRSH r1, [r4, #30] @ x[i+15]
+ SMLABB r14, r8, r0, r14 @ (x[i+14] + x[i+16]) * fir_7k[14]
+ SMLABT r14, r1, r0, r14 @ x[i+15] * fir_7k[15]
+
+ ADD r5, r5, #1
+ ADD r14, r14, #0x4000
+ ADD r4, r4, #2
+ MOV r1, r14, ASR #15
+ CMP r5, #80
+ STRH r1, [r3], #2 @signal[i] = (L_tmp + 0x4000) >> 15
+ BLT LOOP2
+
+ LDR r1, [sp, #-4] @mem address
+ ADD r0, r13, #160 @x + lg
+ MOV r2, #30
+ BL voAWB_Copy
+
+Filt_6k_7k_end:
+ ADD r13, r13, #240
+ LDMFD r13!, {r4 - r12, r15}
+
+Lable1:
+ .word fir_6k_7k
+ @ENDFUNC
+ .END
+
+
diff --git a/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/Norm_Corr_opt.s b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/Norm_Corr_opt.s new file mode 100644 index 0000000..b440a31 --- /dev/null +++ b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/Norm_Corr_opt.s @@ -0,0 +1,231 @@ +@/* +@ ** Copyright 2003-2010, VisualOn, Inc. +@ ** +@ ** Licensed under the Apache License, Version 2.0 (the "License"); +@ ** you may not use this file except in compliance with the License. +@ ** You may obtain a copy of the License at +@ ** +@ ** http://www.apache.org/licenses/LICENSE-2.0 +@ ** +@ ** Unless required by applicable law or agreed to in writing, software +@ ** distributed under the License is distributed on an "AS IS" BASIS, +@ ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +@ ** See the License for the specific language governing permissions and +@ ** limitations under the License. +@ */ + +@static void Norm_Corr (Word16 exc[], /* (i) : excitation buffer */ +@ Word16 xn[], /* (i) : target vector */ +@ Word16 h[], /* (i) Q15 : impulse response of synth/wgt filters */ +@ Word16 L_subfr, /* (i) : sub-frame length */ +@ Word16 t_min, /* (i) : minimum value of pitch lag. */ +@ Word16 t_max, /* (i) : maximum value of pitch lag. */ +@ Word16 corr_norm[]) /* (o) Q15 : normalized correlation */ +@ + +@ r0 --- exc[] +@ r1 --- xn[] +@ r2 --- h[] +@ r3 --- L_subfr +@ r4 --- t_min +@ r5 --- t_max +@ r6 --- corr_norm[] + + + .section .text + .global Norm_corr_asm + .extern Convolve_asm + .extern Isqrt_n +@****************************** +@ constant +@****************************** +.equ EXC , 0 +.equ XN , 4 +.equ H , 8 +.equ L_SUBFR , 12 +.equ voSTACK , 172 +.equ T_MIN , 212 +.equ T_MAX , 216 +.equ CORR_NORM , 220 + +Norm_corr_asm: + + STMFD r13!, {r4 - r12, r14} + SUB r13, r13, #voSTACK + + ADD r8, r13, #20 @get the excf[L_SUBFR] + LDR r4, [r13, #T_MIN] @get t_min + RSB r11, r4, #0 @k = -t_min + ADD r5, r0, r11, LSL #1 @get the &exc[k] + + @transfer Convolve function + STMFD sp!, {r0 - r3} + MOV r0, r5 + MOV r1, r2 + MOV r2, r8 @r2 --- excf[] + BL Convolve_asm + LDMFD sp!, {r0 - r3} + + @ r8 --- excf[] + + MOV r14, r1 @copy xn[] address + MOV r5, #64 + MOV r6, #0 @L_tmp = 0 + MOV r7, #1 + +LOOP1: + LDR r9, [r14], #4 + LDR r10, [r14], #4 + LDR r11, [r14], #4 + LDR r12, [r14], #4 + SMLABB r6, r9, r9, r6 @L_tmp += (xn[i] * xn[i]) + SMLATT r6, r9, r9, r6 @L_tmp += (xn[i+1] * xn[i+1]) + SMLABB r6, r10, r10, r6 + SMLATT r6, r10, r10, r6 + SMLABB r6, r11, r11, r6 + SMLATT r6, r11, r11, r6 + SMLABB r6, r12, r12, r6 + SMLATT r6, r12, r12, r6 + SUBS r5, r5, #8 + BNE LOOP1 + + ADD r9, r7, r6, LSL #1 @L_tmp = (L_tmp << 1) + 1 + CLZ r7, r9 + SUB r6, r7, #1 @exp = norm_l(L_tmp) + RSB r7, r6, #32 @exp = 32 - exp + MOV r6, r7, ASR #1 + RSB r7, r6, #0 @scale = -(exp >> 1) + + @loop for every possible period + @for(t = t_min@ t <= t_max@ t++) + @r7 --- scale r4 --- t_min r8 --- excf[] + +LOOPFOR: + MOV r5, #0 @L_tmp = 0 + MOV r6, #0 @L_tmp1 = 0 + MOV r9, #64 + MOV r12, r1 @copy of xn[] + ADD r14, r13, #20 @copy of excf[] + MOV r8, #0x8000 + +LOOPi: + LDR r11, [r14], #4 @load excf[i], excf[i+1] + LDR r10, [r12], #4 @load xn[i], xn[i+1] + SMLABB r6, r11, r11, r6 @L_tmp1 += excf[i] * excf[i] + SMLATT r6, r11, r11, r6 @L_tmp1 += excf[i+1] * excf[i+1] + SMLABB r5, r10, r11, r5 @L_tmp += xn[i] * excf[i] + SMLATT r5, r10, r11, r5 @L_tmp += xn[i+1] * excf[i+1] + LDR r11, [r14], #4 @load excf[i+2], excf[i+3] + LDR r10, [r12], #4 @load xn[i+2], xn[i+3] + SMLABB r6, r11, r11, r6 + SMLATT r6, r11, r11, r6 + SMLABB r5, r10, r11, r5 + SMLATT r5, r10, r11, r5 + SUBS r9, r9, #4 + BNE LOOPi + + @r5 --- L_tmp, r6 --- L_tmp1 + MOV r10, #1 + ADD r5, r10, r5, LSL #1 @L_tmp = (L_tmp << 1) + 1 + ADD r6, r10, r6, LSL #1 @L_tmp1 = (L_tmp1 << 1) + 1 + + CLZ r10, r5 + CMP r5, #0 + RSBLT r11, r5, #0 + CLZLT r10, r11 + SUB r10, r10, #1 @exp = norm_l(L_tmp) + + MOV r5, r5, LSL r10 @L_tmp = (L_tmp << exp) + RSB r10, r10, #30 @exp_corr = 30 - exp + MOV r11, r5, ASR #16 @corr = extract_h(L_tmp) + + CLZ r5, r6 + SUB r5, r5, #1 + MOV r6, r6, LSL r5 @L_tmp = (L_tmp1 << exp) + RSB r5, r5, #30 @exp_norm = 30 - exp + + @r10 --- exp_corr, r11 --- corr + @r6 --- L_tmp, r5 --- exp_norm + + @Isqrt_n(&L_tmp, &exp_norm) + + MOV r14, r0 + MOV r12, r1 + + STMFD sp!, {r0 - r4, r7 - r12, r14} + ADD r1, sp, #4 + ADD r0, sp, #0 + STR r6, [sp] + STRH r5, [sp, #4] + BL Isqrt_n + LDR r6, [sp] + LDRSH r5, [sp, #4] + LDMFD sp!, {r0 - r4, r7 - r12, r14} + MOV r0, r14 + MOV r1, r12 + + + MOV r6, r6, ASR #16 @norm = extract_h(L_tmp) + MUL r12, r6, r11 + ADD r12, r12, r12 @L_tmp = vo_L_mult(corr, norm) + + ADD r6, r10, r5 + ADD r6, r6, r7 @exp_corr + exp_norm + scale + + CMP r6, #0 + RSBLT r6, r6, #0 + MOVLT r12, r12, ASR r6 + MOVGT r12, r12, LSL r6 @L_tmp = L_shl(L_tmp, exp_corr + exp_norm + scale) + + ADD r12, r12, r8 + MOV r12, r12, ASR #16 @vo_round(L_tmp) + + LDR r5, [r13, #CORR_NORM] @ get corr_norm address + LDR r6, [r13, #T_MAX] @ get t_max + ADD r10, r5, r4, LSL #1 @ get corr_norm[t] address + STRH r12, [r10] @ corr_norm[t] = vo_round(L_tmp) + + CMP r4, r6 + BEQ Norm_corr_asm_end + + ADD r4, r4, #1 @ t_min ++ + + RSB r5, r4, #0 @ k + + MOV r6, #63 @ i = 63 + MOV r8, r0 @ exc[] + MOV r9, r2 @ h[] + ADD r10, r13, #20 @ excf[] + + ADD r8, r8, r5, LSL #1 @ exc[k] address + ADD r9, r9, r6, LSL #1 @ h[i] address + ADD r10, r10, r6, LSL #1 @ excf[i] address + LDRSH r11, [r8] @ tmp = exc[k] + +LOOPK: + LDRSH r8, [r9], #-2 @ load h[i] + LDRSH r12, [r10, #-2] @ load excf[i - 1] + MUL r14, r11, r8 + MOV r8, r14, ASR #15 + ADD r14, r8, r12 + STRH r14, [r10], #-2 + SUBS r6, r6, #1 + BGT LOOPK + + LDRSH r8, [r9] @ load h[0] + MUL r14, r11, r8 + LDR r6, [r13, #T_MAX] @ get t_max + MOV r8, r14, ASR #15 + STRH r8, [r10] + + CMP r4, r6 + BLE LOOPFOR + +Norm_corr_asm_end: + + ADD r13, r13, #voSTACK + LDMFD r13!, {r4 - r12, r15} + + .END + + diff --git a/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/Syn_filt_32_opt.s b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/Syn_filt_32_opt.s new file mode 100644 index 0000000..6416634 --- /dev/null +++ b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/Syn_filt_32_opt.s @@ -0,0 +1,226 @@ +@/*
+@ ** Copyright 2003-2010, VisualOn, Inc.
+@ **
+@ ** Licensed under the Apache License, Version 2.0 (the "License");
+@ ** you may not use this file except in compliance with the License.
+@ ** You may obtain a copy of the License at
+@ **
+@ ** http://www.apache.org/licenses/LICENSE-2.0
+@ **
+@ ** Unless required by applicable law or agreed to in writing, software
+@ ** distributed under the License is distributed on an "AS IS" BASIS,
+@ ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+@ ** See the License for the specific language governing permissions and
+@ ** limitations under the License.
+@ */
+@
+@void Syn_filt_32(
+@ Word16 a[], /* (i) Q12 : a[m+1] prediction coefficients */
+@ Word16 m, /* (i) : order of LP filter */
+@ Word16 exc[], /* (i) Qnew: excitation (exc[i] >> Qnew) */
+@ Word16 Qnew, /* (i) : exc scaling = 0(min) to 8(max) */
+@ Word16 sig_hi[], /* (o) /16 : synthesis high */
+@ Word16 sig_lo[], /* (o) /16 : synthesis low */
+@ Word16 lg /* (i) : size of filtering */
+@)
+@***************************************************************
+@
+@ a[] --- r0
+@ m --- r1
+@ exc[] --- r2
+@ Qnew --- r3
+@ sig_hi[] --- r4
+@ sig_lo[] --- r5
+@ lg --- r6
+
+ .section .text
+ .global Syn_filt_32_asm
+
+Syn_filt_32_asm:
+
+ STMFD r13!, {r4 - r12, r14}
+ LDR r4, [r13, #40] @ get sig_hi[] address
+ LDR r5, [r13, #44] @ get sig_lo[] address
+
+ LDRSH r6, [r0] @ load Aq[0]
+ ADD r7, r3, #4 @ 4 + Q_new
+ MOV r3, r6, ASR r7 @ a0 = Aq[0] >> (4 + Q_new)
+
+ LDR r14, =0xffff
+ LDRSH r6, [r0, #2] @ load Aq[1]
+ LDRSH r7, [r0, #4] @ load Aq[2]
+ LDRSH r8, [r0, #6] @ load Aq[3]
+ LDRSH r9, [r0, #8] @ load Aq[4]
+ AND r6, r6, r14
+ AND r8, r8, r14
+ ORR r10, r6, r7, LSL #16 @ Aq[2] -- Aq[1]
+ ORR r11, r8, r9, LSL #16 @ Aq[4] -- Aq[3]
+ STR r10, [r13, #-4]
+ STR r11, [r13, #-8]
+
+ LDRSH r6, [r0, #10] @ load Aq[5]
+ LDRSH r7, [r0, #12] @ load Aq[6]
+ LDRSH r8, [r0, #14] @ load Aq[7]
+ LDRSH r9, [r0, #16] @ load Aq[8]
+ AND r6, r6, r14
+ AND r8, r8, r14
+ ORR r10, r6, r7, LSL #16 @ Aq[6] -- Aq[5]
+ ORR r11, r8, r9, LSL #16 @ Aq[8] -- Aq[7]
+ STR r10, [r13, #-12]
+ STR r11, [r13, #-16]
+
+ LDRSH r6, [r0, #18] @ load Aq[9]
+ LDRSH r7, [r0, #20] @ load Aq[10]
+ LDRSH r8, [r0, #22] @ load Aq[11]
+ LDRSH r9, [r0, #24] @ load Aq[12]
+ AND r6, r6, r14
+ AND r8, r8, r14
+ ORR r10, r6, r7, LSL #16 @ Aq[10] -- Aq[9]
+ ORR r11, r8, r9, LSL #16 @ Aq[12] -- Aq[11]
+ STR r10, [r13, #-20]
+ STR r11, [r13, #-24]
+
+ LDRSH r6, [r0, #26] @ load Aq[13]
+ LDRSH r7, [r0, #28] @ load Aq[14]
+ LDRSH r8, [r0, #30] @ load Aq[15]
+ LDRSH r9, [r0, #32] @ load Aq[16]
+ AND r6, r6, r14
+ AND r8, r8, r14
+ ORR r10, r6, r7, LSL #16 @ Aq[14] -- Aq[13]
+ ORR r11, r8, r9, LSL #16 @ Aq[16] -- Aq[15]
+ STR r10, [r13, #-28]
+ STR r11, [r13, #-32]
+
+ MOV r8, #0 @ i = 0
+
+LOOP:
+ LDRSH r6, [r5, #-2] @ load sig_lo[i-1]
+ LDRSH r7, [r5, #-4] @ load sig_lo[i-2]
+
+ LDR r11, [r13, #-4] @ Aq[2] -- Aq[1]
+ LDRSH r9, [r5, #-6] @ load sig_lo[i-3]
+ LDRSH r10, [r5, #-8] @ load sig_lo[i-4]
+
+ SMULBB r12, r6, r11 @ sig_lo[i-1] * Aq[1]
+
+ LDRSH r6, [r5, #-10] @ load sig_lo[i-5]
+ SMLABT r12, r7, r11, r12 @ sig_lo[i-2] * Aq[2]
+ LDR r11, [r13, #-8] @ Aq[4] -- Aq[3]
+ LDRSH r7, [r5, #-12] @ load sig_lo[i-6]
+ SMLABB r12, r9, r11, r12 @ sig_lo[i-3] * Aq[3]
+ LDRSH r9, [r5, #-14] @ load sig_lo[i-7]
+ SMLABT r12, r10, r11, r12 @ sig_lo[i-4] * Aq[4]
+ LDR r11, [r13, #-12] @ Aq[6] -- Aq[5]
+ LDRSH r10, [r5, #-16] @ load sig_lo[i-8]
+ SMLABB r12, r6, r11, r12 @ sig_lo[i-5] * Aq[5]
+ LDRSH r6, [r5, #-18] @ load sig_lo[i-9]
+ SMLABT r12, r7, r11, r12 @ sig_lo[i-6] * Aq[6]
+ LDR r11, [r13, #-16] @ Aq[8] -- Aq[7]
+ LDRSH r7, [r5, #-20] @ load sig_lo[i-10]
+ SMLABB r12, r9, r11, r12 @ sig_lo[i-7] * Aq[7]
+ LDRSH r9, [r5, #-22] @ load sig_lo[i-11]
+ SMLABT r12, r10, r11, r12 @ sig_lo[i-8] * Aq[8]
+ LDR r11, [r13, #-20] @ Aq[10] -- Aq[9]
+ LDRSH r10,[r5, #-24] @ load sig_lo[i-12]
+ SMLABB r12, r6, r11, r12 @ sig_lo[i-9] * Aq[9]
+ LDRSH r6, [r5, #-26] @ load sig_lo[i-13]
+ SMLABT r12, r7, r11, r12 @ sig_lo[i-10] * Aq[10]
+ LDR r11, [r13, #-24] @ Aq[12] -- Aq[11]
+ LDRSH r7, [r5, #-28] @ load sig_lo[i-14]
+ SMLABB r12, r9, r11, r12 @ sig_lo[i-11] * Aq[11]
+ LDRSH r9, [r5, #-30] @ load sig_lo[i-15]
+ SMLABT r12, r10, r11, r12 @ sig_lo[i-12] * Aq[12]
+
+ LDR r11, [r13, #-28] @ Aq[14] -- Aq[13]
+ LDRSH r10, [r5, #-32] @ load sig_lo[i-16]
+ SMLABB r12, r6, r11, r12 @ sig_lo[i-13] * Aq[13]
+ SMLABT r12, r7, r11, r12 @ sig_lo[i-14] * Aq[14]
+
+ LDR r11, [r13, #-32] @ Aq[16] -- Aq[15]
+ LDRSH r6, [r2],#2 @ load exc[i]
+ SMLABB r12, r9, r11, r12 @ sig_lo[i-15] * Aq[15]
+ SMLABT r12, r10, r11, r12 @ sig_lo[i-16] * Aq[16]
+ MUL r7, r6, r3 @ exc[i] * a0
+ RSB r14, r12, #0 @ L_tmp
+ MOV r14, r14, ASR #11 @ L_tmp >>= 11
+ ADD r14, r14, r7, LSL #1 @ L_tmp += (exc[i] * a0) << 1
+
+
+ LDRSH r6, [r4, #-2] @ load sig_hi[i-1]
+ LDRSH r7, [r4, #-4] @ load sig_hi[i-2]
+
+ LDR r11, [r13, #-4] @ Aq[2] -- Aq[1]
+ LDRSH r9, [r4, #-6] @ load sig_hi[i-3]
+ LDRSH r10, [r4, #-8] @ load sig_hi[i-4]
+ SMULBB r12, r6, r11 @ sig_hi[i-1] * Aq[1]
+ LDRSH r6, [r4, #-10] @ load sig_hi[i-5]
+ SMLABT r12, r7, r11, r12 @ sig_hi[i-2] * Aq[2]
+
+ LDR r11, [r13, #-8] @ Aq[4] -- Aq[3]
+ LDRSH r7, [r4, #-12] @ load sig_hi[i-6]
+
+ SMLABB r12, r9, r11, r12 @ sig_hi[i-3] * Aq[3]
+ LDRSH r9, [r4, #-14] @ load sig_hi[i-7]
+
+ SMLABT r12, r10, r11, r12 @ sig_hi[i-4] * Aq[4]
+
+ LDR r11, [r13, #-12] @ Aq[6] -- Aq[5]
+ LDRSH r10, [r4, #-16] @ load sig_hi[i-8]
+
+ SMLABB r12, r6, r11, r12 @ sig_hi[i-5] * Aq[5]
+
+ LDRSH r6, [r4, #-18] @ load sig_hi[i-9]
+ SMLABT r12, r7, r11, r12 @ sig_hi[i-6] * Aq[6]
+
+ LDR r11, [r13, #-16] @ Aq[8] -- Aq[7]
+ LDRSH r7, [r4, #-20] @ load sig_hi[i-10]
+
+ SMLABB r12, r9, r11, r12 @ sig_hi[i-7] * Aq[7]
+
+ LDRSH r9, [r4, #-22] @ load sig_hi[i-11]
+
+ SMLABT r12, r10, r11, r12 @ sig_hi[i-8] * Aq[8]
+
+ LDR r11, [r13, #-20] @ Aq[10] -- Aq[9]
+ LDRSH r10,[r4, #-24] @ load sig_hi[i-12]
+
+ SMLABB r12, r6, r11, r12 @ sig_hi[i-9] * Aq[9]
+ LDRSH r6, [r4, #-26] @ load sig_hi[i-13]
+ SMLABT r12, r7, r11, r12 @ sig_hi[i-10] * Aq[10]
+
+ LDR r11, [r13, #-24] @ Aq[12] -- Aq[11]
+ LDRSH r7, [r4, #-28] @ load sig_hi[i-14]
+ SMLABB r12, r9, r11, r12 @ sig_hi[i-11] * Aq[11]
+ LDRSH r9, [r4, #-30] @ load sig_hi[i-15]
+ SMLABT r12, r10, r11, r12 @ sig_hi[i-12] * Aq[12]
+
+ LDR r11, [r13, #-28] @ Aq[14] -- Aq[13]
+ LDRSH r10, [r4, #-32] @ load sig_hi[i-16]
+ SMLABB r12, r6, r11, r12 @ sig_hi[i-13] * Aq[13]
+ SMLABT r12, r7, r11, r12 @ sig_hi[i-14] * Aq[14]
+
+ LDR r11, [r13, #-32] @ Aq[16] -- Aq[15]
+ SMLABB r12, r9, r11, r12 @ sig_hi[i-15] * Aq[15]
+ SMLABT r12, r10, r11, r12 @ sig_hi[i-16] * Aq[16]
+ ADD r6, r12, r12 @ r12 << 1
+ SUB r14, r14, r6
+ MOV r14, r14, LSL #3 @ L_tmp <<=3
+
+ MOV r7, r14, ASR #16 @ L_tmp >> 16
+
+ MOV r14, r14, ASR #4 @ L_tmp >>=4
+ STRH r7, [r4], #2 @ sig_hi[i] = L_tmp >> 16
+ SUB r9, r14, r7, LSL #12 @ sig_lo[i] = L_tmp - (sig_hi[i] << 12)
+
+ ADD r8, r8, #1
+ STRH r9, [r5], #2
+ CMP r8, #64
+ BLT LOOP
+
+Syn_filt_32_end:
+
+ LDMFD r13!, {r4 - r12, r15}
+ @ENDFUNC
+ .END
+
+
diff --git a/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/convolve_opt.s b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/convolve_opt.s new file mode 100644 index 0000000..0228bda --- /dev/null +++ b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/convolve_opt.s @@ -0,0 +1,186 @@ +@/* +@ ** Copyright 2003-2010, VisualOn, Inc. +@ ** +@ ** Licensed under the Apache License, Version 2.0 (the "License"); +@ ** you may not use this file except in compliance with the License. +@ ** You may obtain a copy of the License at +@ ** +@ ** http://www.apache.org/licenses/LICENSE-2.0 +@ ** +@ ** Unless required by applicable law or agreed to in writing, software +@ ** distributed under the License is distributed on an "AS IS" BASIS, +@ ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +@ ** See the License for the specific language governing permissions and +@ ** limitations under the License. +@ */ + + +@*void Convolve ( +@* Word16 x[], /* (i) : input vector */ +@* Word16 h[], /* (i) : impulse response */ +@* Word16 y[], /* (o) : output vector */ +@* Word16 L /* (i) : vector size */ +@*) +@ r0 --- x[] +@ r1 --- h[] +@ r2 --- y[] +@ r3 --- L + + .section .text + .global Convolve_asm + +Convolve_asm: + + STMFD r13!, {r4 - r12, r14} + MOV r3, #0 @ n + MOV r11, #0x8000 + +LOOP: + ADD r4, r1, r3, LSL #1 @ tmpH address + ADD r5, r3, #1 @ i = n + 1 + MOV r6, r0 @ tmpX = x + LDRSH r9, [r6], #2 @ *tmpX++ + LDRSH r10, [r4], #-2 @ *tmpH-- + SUB r5, r5, #1 + MUL r8, r9, r10 + +LOOP1: + CMP r5, #0 + BLE L1 + LDRSH r9, [r6], #2 @ *tmpX++ + LDRSH r10, [r4], #-2 @ *tmpH-- + LDRSH r12, [r6], #2 @ *tmpX++ + LDRSH r14, [r4], #-2 @ *tmpH-- + MLA r8, r9, r10, r8 + MLA r8, r12, r14, r8 + LDRSH r9, [r6], #2 @ *tmpX++ + LDRSH r10, [r4], #-2 @ *tmpH-- + LDRSH r12, [r6], #2 @ *tmpX++ + LDRSH r14, [r4], #-2 @ *tmpH-- + MLA r8, r9, r10, r8 + SUBS r5, r5, #4 + MLA r8, r12, r14, r8 + + B LOOP1 + +L1: + + ADD r5, r11, r8, LSL #1 + MOV r5, r5, LSR #16 @extract_h(s) + ADD r3, r3, #1 + STRH r5, [r2], #2 @y[n] + + + ADD r4, r1, r3, LSL #1 @tmpH address + ADD r5, r3, #1 + MOV r6, r0 + LDRSH r9, [r6], #2 @ *tmpX++ + LDRSH r10, [r4], #-2 + LDRSH r12, [r6], #2 + LDRSH r14, [r4], #-2 + + MUL r8, r9, r10 + SUB r5, r5, #2 + MLA r8, r12, r14, r8 + +LOOP2: + CMP r5, #0 + BLE L2 + LDRSH r9, [r6], #2 @ *tmpX++ + LDRSH r10, [r4], #-2 @ *tmpH-- + LDRSH r12, [r6], #2 @ *tmpX++ + LDRSH r14, [r4], #-2 @ *tmpH-- + MLA r8, r9, r10, r8 + MLA r8, r12, r14, r8 + LDRSH r9, [r6], #2 @ *tmpX++ + LDRSH r10, [r4], #-2 @ *tmpH-- + LDRSH r12, [r6], #2 @ *tmpX++ + LDRSH r14, [r4], #-2 @ *tmpH-- + MLA r8, r9, r10, r8 + SUBS r5, r5, #4 + MLA r8, r12, r14, r8 + B LOOP2 + +L2: + ADD r8, r11, r8, LSL #1 + MOV r8, r8, LSR #16 @extract_h(s) + ADD r3, r3, #1 + STRH r8, [r2], #2 @y[n] + + ADD r4, r1, r3, LSL #1 + ADD r5, r3, #1 + MOV r6, r0 + LDRSH r9, [r6], #2 + LDRSH r10, [r4], #-2 + LDRSH r12, [r6], #2 + LDRSH r14, [r4], #-2 + MUL r8, r9, r10 + LDRSH r9, [r6], #2 + LDRSH r10, [r4], #-2 + MLA r8, r12, r14, r8 + SUB r5, r5, #3 + MLA r8, r9, r10, r8 + +LOOP3: + CMP r5, #0 + BLE L3 + LDRSH r9, [r6], #2 @ *tmpX++ + LDRSH r10, [r4], #-2 @ *tmpH-- + LDRSH r12, [r6], #2 @ *tmpX++ + LDRSH r14, [r4], #-2 @ *tmpH-- + MLA r8, r9, r10, r8 + MLA r8, r12, r14, r8 + LDRSH r9, [r6], #2 @ *tmpX++ + LDRSH r10, [r4], #-2 @ *tmpH-- + LDRSH r12, [r6], #2 @ *tmpX++ + LDRSH r14, [r4], #-2 @ *tmpH-- + MLA r8, r9, r10, r8 + SUBS r5, r5, #4 + MLA r8, r12, r14, r8 + B LOOP3 + +L3: + ADD r8, r11, r8, LSL #1 + MOV r8, r8, LSR #16 @extract_h(s) + ADD r3, r3, #1 + STRH r8, [r2], #2 @y[n] + + ADD r5, r3, #1 @ i = n + 1 + ADD r4, r1, r3, LSL #1 @ tmpH address + MOV r6, r0 + MOV r8, #0 + +LOOP4: + CMP r5, #0 + BLE L4 + LDRSH r9, [r6], #2 @ *tmpX++ + LDRSH r10, [r4], #-2 @ *tmpH-- + LDRSH r12, [r6], #2 @ *tmpX++ + LDRSH r14, [r4], #-2 @ *tmpH-- + MLA r8, r9, r10, r8 + MLA r8, r12, r14, r8 + LDRSH r9, [r6], #2 @ *tmpX++ + LDRSH r10, [r4], #-2 @ *tmpH-- + LDRSH r12, [r6], #2 @ *tmpX++ + LDRSH r14, [r4], #-2 @ *tmpH-- + MLA r8, r9, r10, r8 + SUBS r5, r5, #4 + MLA r8, r12, r14, r8 + B LOOP4 +L4: + ADD r5, r11, r8, LSL #1 + MOV r5, r5, LSR #16 @extract_h(s) + ADD r3, r3, #1 + STRH r5, [r2], #2 @y[n] + + CMP r3, #64 + BLT LOOP + +Convolve_asm_end: + + LDMFD r13!, {r4 - r12, r15} + + @ENDFUNC + .END + + diff --git a/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/cor_h_vec_opt.s b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/cor_h_vec_opt.s new file mode 100644 index 0000000..441b984 --- /dev/null +++ b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/cor_h_vec_opt.s @@ -0,0 +1,151 @@ +@/*
+@ ** Copyright 2003-2010, VisualOn, Inc.
+@ **
+@ ** Licensed under the Apache License, Version 2.0 (the "License");
+@ ** you may not use this file except in compliance with the License.
+@ ** You may obtain a copy of the License at
+@ **
+@ ** http://www.apache.org/licenses/LICENSE-2.0
+@ **
+@ ** Unless required by applicable law or agreed to in writing, software
+@ ** distributed under the License is distributed on an "AS IS" BASIS,
+@ ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+@ ** See the License for the specific language governing permissions and
+@ ** limitations under the License.
+@ */
+@static void cor_h_vec_012(
+@ Word16 h[], /* (i) scaled impulse response */
+@ Word16 vec[], /* (i) scaled vector (/8) to correlate with h[] */
+@ Word16 track, /* (i) track to use */
+@ Word16 sign[], /* (i) sign vector */
+@ Word16 rrixix[][NB_POS], /* (i) correlation of h[x] with h[x] */
+@ Word16 cor_1[], /* (o) result of correlation (NB_POS elements) */
+@ Word16 cor_2[] /* (o) result of correlation (NB_POS elements) */
+@)
+@r0 ---- h[]
+@r1 ---- vec[]
+@r2 ---- track
+@r3 ---- sign[]
+@r4 ---- rrixix[][NB_POS]
+@r5 ---- cor_1[]
+@r6 ---- cor_2[]
+
+
+ .section .text
+ .global cor_h_vec_012_asm
+
+cor_h_vec_012_asm:
+
+ STMFD r13!, {r4 - r12, r14}
+ LDR r4, [r13, #40] @load rrixix[][NB_POS]
+ ADD r7, r4, r2, LSL #5 @r7 --- p0 = rrixix[track]
+ MOV r4, #0 @i=0
+
+ @r0 --- h[], r1 --- vec[], r2 --- pos
+ @r3 --- sign[], r4 --- i, r7 --- p0
+LOOPi:
+ MOV r5, #0 @L_sum1 = 0
+ MOV r6, #0 @L_sum2 = 0
+ ADD r9, r1, r2, LSL #1 @p2 = &vec[pos]
+ MOV r10, r0 @p1 = h
+ RSB r11, r2, #62 @j=62-pos
+
+LOOPj1:
+ LDRSH r12, [r10], #2
+ LDRSH r8, [r9], #2
+ LDRSH r14, [r9]
+ SUBS r11, r11, #1
+ MLA r5, r12, r8, r5
+ MLA r6, r12, r14, r6
+ BGE LOOPj1
+
+ LDRSH r12, [r10], #2 @*p1++
+ MOV r6, r6, LSL #2 @L_sum2 = (L_sum2 << 2)
+ MLA r5, r12, r14, r5
+ MOV r14, #0x8000
+ MOV r5, r5, LSL #2 @L_sum1 = (L_sum1 << 2)
+ ADD r10, r6, r14
+ ADD r9, r5, r14
+ MOV r5, r9, ASR #16
+ MOV r6, r10, ASR #16
+ ADD r9, r3, r2, LSL #1 @address of sign[pos]
+ ADD r8, r7, #32
+ LDRSH r10, [r9], #2 @sign[pos]
+ LDRSH r11, [r9] @sign[pos + 1]
+ MUL r12, r5, r10
+ MUL r14, r6, r11
+ MOV r5, r12, ASR #15
+ MOV r6, r14, ASR #15
+ LDR r9, [r13, #44]
+ LDR r12, [r13, #48]
+ LDRSH r10, [r7], #2 @*p0++
+ LDRSH r11, [r8] @*p3++
+ ADD r9, r9, r4, LSL #1
+ ADD r12, r12, r4, LSL #1
+ ADD r5, r5, r10
+ ADD r6, r6, r11
+ STRH r5, [r9]
+ STRH r6, [r12]
+
+ ADD r2, r2, #4
+
+ MOV r5, #0 @L_sum1 = 0
+ MOV r6, #0 @L_sum2 = 0
+ ADD r9, r1, r2, LSL #1 @p2 = &vec[pos]
+ MOV r10, r0 @p1 = h
+ RSB r11, r2, #62 @j=62-pos
+ ADD r4, r4, #1 @i++
+
+LOOPj2:
+ LDRSH r12, [r10], #2
+ LDRSH r8, [r9], #2
+ LDRSH r14, [r9]
+ SUBS r11, r11, #1
+ MLA r5, r12, r8, r5
+ MLA r6, r12, r14, r6
+ BGE LOOPj2
+
+ LDRSH r12, [r10], #2 @*p1++
+ MOV r6, r6, LSL #2 @L_sum2 = (L_sum2 << 2)
+ MLA r5, r12, r14, r5
+ MOV r14, #0x8000
+ MOV r5, r5, LSL #2 @L_sum1 = (L_sum1 << 2)
+ ADD r10, r6, r14
+ ADD r9, r5, r14
+
+ MOV r5, r9, ASR #16
+ MOV r6, r10, ASR #16
+ ADD r9, r3, r2, LSL #1 @address of sign[pos]
+ ADD r8, r7, #32
+ LDRSH r10, [r9], #2 @sign[pos]
+ LDRSH r11, [r9] @sign[pos + 1]
+ MUL r12, r5, r10
+ MUL r14, r6, r11
+ MOV r5, r12, ASR #15
+ MOV r6, r14, ASR #15
+ LDR r9, [r13, #44]
+ LDR r12, [r13, #48]
+ LDRSH r10, [r7], #2 @*p0++
+ LDRSH r11, [r8] @*p3++
+ ADD r9, r9, r4, LSL #1
+ ADD r12, r12, r4, LSL #1
+ ADD r5, r5, r10
+ ADD r6, r6, r11
+ STRH r5, [r9]
+ STRH r6, [r12]
+ ADD r4, r4, #1 @i+1
+ ADD r2, r2, #4 @pos += STEP
+ CMP r4, #16
+
+ BLT LOOPi
+
+the_end:
+ LDMFD r13!, {r4 - r12, r15}
+
+ @ENDFUNC
+ .END
+
+
+
+
+
diff --git a/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/pred_lt4_1_opt.s b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/pred_lt4_1_opt.s new file mode 100644 index 0000000..d5dd8f0 --- /dev/null +++ b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/pred_lt4_1_opt.s @@ -0,0 +1,460 @@ +@/*
+@ ** Copyright 2003-2010, VisualOn, Inc.
+@ **
+@ ** Licensed under the Apache License, Version 2.0 (the "License");
+@ ** you may not use this file except in compliance with the License.
+@ ** You may obtain a copy of the License at
+@ **
+@ ** http://www.apache.org/licenses/LICENSE-2.0
+@ **
+@ ** Unless required by applicable law or agreed to in writing, software
+@ ** distributed under the License is distributed on an "AS IS" BASIS,
+@ ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+@ ** See the License for the specific language governing permissions and
+@ ** limitations under the License.
+@ */
+@
+@void Pred_lt4(
+@ Word16 exc[], /* in/out: excitation buffer */
+@ Word16 T0, /* input : integer pitch lag */
+@ Word16 frac, /* input : fraction of lag */
+@ Word16 L_subfr /* input : subframe size */
+@ )
+
+@******************************
+@ ARM Register
+@******************************
+@ r0 --- exc[]
+@ r1 --- T0
+@ r2 --- frac
+@ r3 --- L_subfr
+
+ .section .text
+ .global pred_lt4_asm
+ .extern inter4_2
+
+pred_lt4_asm:
+
+ STMFD r13!, {r4 - r12, r14}
+ RSB r4, r1, #0 @-T0
+ RSB r2, r2, #0 @frac = -frac
+ ADD r5, r0, r4, LSL #1 @x = exc - T0
+ CMP r2, #0
+ ADDLT r2, r2, #4 @frac += UP_SAMP
+ SUBLT r5, r5, #2 @x--
+ SUB r5, r5, #30 @x -= 15
+ RSB r4, r2, #3 @k = 3 - frac
+ LDR r6, Table
+ MOV r8, r4, LSL #6
+ @MOV r7, #0 @j = 0
+ ADD r8, r6, r8 @ptr2 = &(inter4_2[k][0])
+
+ MOV r1, r5
+ MOV r5, #0x8000
+ MOV r14, #21
+@ used register
+ @r0 --- exc[] r1 --- x r7 --- j r8 --- ptr2 r5 --- 0x8000
+THREE_LOOP:
+
+ @MOV r1, r5 @ptr1 = x
+ MOV r2, r8 @ptr = ptr2
+ LDR r3, [r2], #4 @h[0], h[1]
+ LDRSH r4, [r1], #2 @x[0]
+ LDRSH r6, [r1], #2 @x[1]
+ LDRSH r9, [r1], #2 @x[2]
+
+ SMULBB r10, r4, r3 @x[0] * h[0]
+ SMULBB r11, r6, r3 @x[1] * h[0]
+ SMULBB r12, r9, r3 @x[2] * h[0]
+
+ LDRSH r4, [r1], #2 @x[3]
+ SMLABT r10, r6, r3, r10 @x[1] * h[1]
+ SMLABT r11, r9, r3, r11 @x[2] * h[1]
+ SMLABT r12, r4, r3, r12 @x[3] * h[1]
+
+ LDR r3, [r2], #4 @h[2], h[3]
+ LDRSH r6, [r1], #2 @x[4]
+ SMLABB r10, r9, r3, r10 @x[2] * h[2]
+ SMLABB r11, r4, r3, r11 @x[3] * h[2]
+ SMLABB r12, r6, r3, r12 @x[4] * h[2]
+
+ LDRSH r9, [r1], #2 @x[5]
+ SMLABT r10, r4, r3, r10 @x[3] * h[3]
+ SMLABT r11, r6, r3, r11 @x[4] * h[3]
+ SMLABT r12, r9, r3, r12 @x[5] * h[3]
+
+ LDR r3, [r2], #4 @h[4], h[5]
+ LDRSH r4, [r1], #2 @x[6]
+ SMLABB r10, r6, r3, r10 @x[4] * h[4]
+ SMLABB r11, r9, r3, r11 @x[5] * h[4]
+ SMLABB r12, r4, r3, r12 @x[6] * h[4]
+
+ LDRSH r6, [r1], #2 @x[7]
+ SMLABT r10, r9, r3, r10 @x[5] * h[5]
+ SMLABT r11, r4, r3, r11 @x[6] * h[5]
+ SMLABT r12, r6, r3, r12 @x[7] * h[5]
+
+ LDR r3, [r2], #4 @h[6], h[7]
+ LDRSH r9, [r1], #2 @x[8]
+ SMLABB r10, r4, r3, r10 @x[6] * h[6]
+ SMLABB r11, r6, r3, r11 @x[7] * h[6]
+ SMLABB r12, r9, r3, r12 @x[8] * h[6]
+
+ LDRSH r4, [r1], #2 @x[9]
+ SMLABT r10, r6, r3, r10 @x[7] * h[7]
+ SMLABT r11, r9, r3, r11 @x[8] * h[7]
+ SMLABT r12, r4, r3, r12 @x[9] * h[7]
+
+ LDR r3, [r2], #4 @h[8], h[9]
+ LDRSH r6, [r1], #2 @x[10]
+ SMLABB r10, r9, r3, r10 @x[8] * h[8]
+ SMLABB r11, r4, r3, r11 @x[9] * h[8]
+ SMLABB r12, r6, r3, r12 @x[10] * h[8]
+
+ LDRSH r9, [r1], #2 @x[11]
+ SMLABT r10, r4, r3, r10 @x[9] * h[9]
+ SMLABT r11, r6, r3, r11 @x[10] * h[9]
+ SMLABT r12, r9, r3, r12 @x[11] * h[9]
+
+ LDR r3, [r2], #4 @h[10], h[11]
+ LDRSH r4, [r1], #2 @x[12]
+ SMLABB r10, r6, r3, r10 @x[10] * h[10]
+ SMLABB r11, r9, r3, r11 @x[11] * h[10]
+ SMLABB r12, r4, r3, r12 @x[12] * h[10]
+
+ LDRSH r6, [r1], #2 @x[13]
+ SMLABT r10, r9, r3, r10 @x[11] * h[11]
+ SMLABT r11, r4, r3, r11 @x[12] * h[11]
+ SMLABT r12, r6, r3, r12 @x[13] * h[11]
+
+ LDR r3, [r2], #4 @h[12], h[13]
+ LDRSH r9, [r1], #2 @x[14]
+ SMLABB r10, r4, r3, r10 @x[12] * h[12]
+ SMLABB r11, r6, r3, r11 @x[13] * h[12]
+ SMLABB r12, r9, r3, r12 @x[14] * h[12]
+
+ LDRSH r4, [r1], #2 @x[15]
+ SMLABT r10, r6, r3, r10 @x[13] * h[13]
+ SMLABT r11, r9, r3, r11 @x[14] * h[13]
+ SMLABT r12, r4, r3, r12 @x[15] * h[13]
+
+ LDR r3, [r2], #4 @h[14], h[15]
+ LDRSH r6, [r1], #2 @x[16]
+ SMLABB r10, r9, r3, r10 @x[14] * h[14]
+ SMLABB r11, r4, r3, r11 @x[15] * h[14]
+ SMLABB r12, r6, r3, r12 @x[16] * h[14]
+
+ LDRSH r9, [r1], #2 @x[17]
+ SMLABT r10, r4, r3, r10 @x[15] * h[15]
+ SMLABT r11, r6, r3, r11 @x[16] * h[15]
+ SMLABT r12, r9, r3, r12 @x[17] * h[15]
+
+ LDR r3, [r2], #4 @h[16], h[17]
+ LDRSH r4, [r1], #2 @x[18]
+ SMLABB r10, r6, r3, r10 @x[16] * h[16]
+ SMLABB r11, r9, r3, r11 @x[17] * h[16]
+ SMLABB r12, r4, r3, r12 @x[18] * h[16]
+
+ LDRSH r6, [r1], #2 @x[19]
+ SMLABT r10, r9, r3, r10 @x[17] * h[17]
+ SMLABT r11, r4, r3, r11 @x[18] * h[17]
+ SMLABT r12, r6, r3, r12 @x[19] * h[17]
+
+ LDR r3, [r2], #4 @h[18], h[19]
+ LDRSH r9, [r1], #2 @x[20]
+ SMLABB r10, r4, r3, r10 @x[18] * h[18]
+ SMLABB r11, r6, r3, r11 @x[19] * h[18]
+ SMLABB r12, r9, r3, r12 @x[20] * h[18]
+
+ LDRSH r4, [r1], #2 @x[21]
+ SMLABT r10, r6, r3, r10 @x[19] * h[19]
+ SMLABT r11, r9, r3, r11 @x[20] * h[19]
+ SMLABT r12, r4, r3, r12 @x[21] * h[19]
+
+ LDR r3, [r2], #4 @h[20], h[21]
+ LDRSH r6, [r1], #2 @x[22]
+ SMLABB r10, r9, r3, r10 @x[20] * h[20]
+ SMLABB r11, r4, r3, r11 @x[21] * h[20]
+ SMLABB r12, r6, r3, r12 @x[22] * h[20]
+
+ LDRSH r9, [r1], #2 @x[23]
+ SMLABT r10, r4, r3, r10 @x[21] * h[21]
+ SMLABT r11, r6, r3, r11 @x[22] * h[21]
+ SMLABT r12, r9, r3, r12 @x[23] * h[21]
+
+ LDR r3, [r2], #4 @h[22], h[23]
+ LDRSH r4, [r1], #2 @x[24]
+ SMLABB r10, r6, r3, r10 @x[22] * h[22]
+ SMLABB r11, r9, r3, r11 @x[23] * h[22]
+ SMLABB r12, r4, r3, r12 @x[24] * h[22]
+
+ LDRSH r6, [r1], #2 @x[25]
+ SMLABT r10, r9, r3, r10 @x[23] * h[23]
+ SMLABT r11, r4, r3, r11 @x[24] * h[23]
+ SMLABT r12, r6, r3, r12 @x[25] * h[23]
+
+ LDR r3, [r2], #4 @h[24], h[25]
+ LDRSH r9, [r1], #2 @x[26]
+ SMLABB r10, r4, r3, r10 @x[24] * h[24]
+ SMLABB r11, r6, r3, r11 @x[25] * h[24]
+ SMLABB r12, r9, r3, r12 @x[26] * h[24]
+
+ LDRSH r4, [r1], #2 @x[27]
+ SMLABT r10, r6, r3, r10 @x[25] * h[25]
+ SMLABT r11, r9, r3, r11 @x[26] * h[25]
+ SMLABT r12, r4, r3, r12 @x[27] * h[25]
+
+ LDR r3, [r2], #4 @h[26], h[27]
+ LDRSH r6, [r1], #2 @x[28]
+ SMLABB r10, r9, r3, r10 @x[26] * h[26]
+ SMLABB r11, r4, r3, r11 @x[27] * h[26]
+ SMLABB r12, r6, r3, r12 @x[28] * h[26]
+
+ LDRSH r9, [r1], #2 @x[29]
+ SMLABT r10, r4, r3, r10 @x[27] * h[27]
+ SMLABT r11, r6, r3, r11 @x[28] * h[27]
+ SMLABT r12, r9, r3, r12 @x[29] * h[27]
+
+ LDR r3, [r2], #4 @h[28], h[29]
+ LDRSH r4, [r1], #2 @x[30]
+ SMLABB r10, r6, r3, r10 @x[28] * h[28]
+ SMLABB r11, r9, r3, r11 @x[29] * h[28]
+ SMLABB r12, r4, r3, r12 @x[30] * h[28]
+
+ LDRSH r6, [r1], #2 @x[31]
+ SMLABT r10, r9, r3, r10 @x[29] * h[29]
+ SMLABT r11, r4, r3, r11 @x[30] * h[29]
+ SMLABT r12, r6, r3, r12 @x[31] * h[29]
+
+ LDR r3, [r2], #4 @h[30], h[31]
+ LDRSH r9, [r1], #2 @x[32]
+ SMLABB r10, r4, r3, r10 @x[30] * h[30]
+ SMLABB r11, r6, r3, r11 @x[31] * h[30]
+ SMLABB r12, r9, r3, r12 @x[32] * h[30]
+
+ LDRSH r4, [r1], #-60 @x[33]
+ SMLABT r10, r6, r3, r10 @x[31] * h[31]
+ SMLABT r11, r9, r3, r11 @x[32] * h[31]
+ SMLABT r12, r4, r3, r12 @x[33] * h[31]
+
+ @SSAT r10, #32, r10, LSL #2
+ @SSAT r11, #32, r11, LSL #2
+ @SSAT r12, #32, r12, LSL #2
+
+ MOV r10, r10, LSL #1
+ MOV r11, r11, LSL #1
+ MOV r12, r12, LSL #1
+
+ QADD r10, r10, r10
+ QADD r11, r11, r11
+ QADD r12, r12, r12
+
+ QADD r10, r10, r5
+ QADD r11, r11, r5
+ QADD r12, r12, r5
+
+ SUBS r14, r14, #1
+
+ MOV r10, r10, ASR #16
+ MOV r11, r11, ASR #16
+ MOV r12, r12, ASR #16
+
+ STRH r10, [r0], #2
+ STRH r11, [r0], #2
+ STRH r12, [r0], #2
+ BNE THREE_LOOP
+
+ MOV r2, r8 @ptr = ptr2
+
+Last2LOOP:
+
+ LDR r3, [r2], #4 @h[0], h[1]
+ LDRSH r4, [r1], #2 @x[0]
+ LDRSH r6, [r1], #2 @x[1]
+ LDRSH r9, [r1], #2 @x[2]
+
+ SMULBB r10, r4, r3 @x[0] * h[0]
+ SMULBB r11, r6, r3 @x[1] * h[0]
+
+ SMLABT r10, r6, r3, r10 @x[1] * h[1]
+ SMLABT r11, r9, r3, r11 @x[2] * h[1]
+
+ LDR r3, [r2], #4 @h[2], h[3]
+ LDRSH r4, [r1], #2 @x[3]
+ LDRSH r6, [r1], #2 @x[4]
+
+ SMLABB r10, r9, r3, r10 @x[2] * h[2]
+ SMLABB r11, r4, r3, r11 @x[3] * h[2]
+
+ SMLABT r10, r4, r3, r10 @x[3] * h[3]
+ SMLABT r11, r6, r3, r11 @x[4] * h[3]
+
+ LDR r3, [r2], #4 @h[4], h[5]
+ LDRSH r9, [r1], #2 @x[5]
+ LDRSH r4, [r1], #2 @x[6]
+
+ SMLABB r10, r6, r3, r10 @x[4] * h[4]
+ SMLABB r11, r9, r3, r11 @x[5] * h[4]
+
+ SMLABT r10, r9, r3, r10 @x[5] * h[5]
+ SMLABT r11, r4, r3, r11 @x[6] * h[5]
+
+ LDR r3, [r2], #4 @h[6], h[7]
+ LDRSH r6, [r1], #2 @x[7]
+ LDRSH r9, [r1], #2 @x[8]
+
+ SMLABB r10, r4, r3, r10 @x[6] * h[6]
+ SMLABB r11, r6, r3, r11 @x[7] * h[6]
+
+ SMLABT r10, r6, r3, r10 @x[7] * h[7]
+ SMLABT r11, r9, r3, r11 @x[8] * h[7]
+
+ LDR r3, [r2], #4 @h[8], h[9]
+ LDRSH r4, [r1], #2 @x[9]
+ LDRSH r6, [r1], #2 @x[10]
+
+ SMLABB r10, r9, r3, r10 @x[8] * h[8]
+ SMLABB r11, r4, r3, r11 @x[9] * h[8]
+
+ SMLABT r10, r4, r3, r10 @x[9] * h[9]
+ SMLABT r11, r6, r3, r11 @x[10] * h[9]
+
+ LDR r3, [r2], #4 @h[10], h[11]
+ LDRSH r9, [r1], #2 @x[11]
+ LDRSH r4, [r1], #2 @x[12]
+
+ SMLABB r10, r6, r3, r10 @x[10] * h[10]
+ SMLABB r11, r9, r3, r11 @x[11] * h[10]
+
+ SMLABT r10, r9, r3, r10 @x[11] * h[11]
+ SMLABT r11, r4, r3, r11 @x[12] * h[11]
+
+ LDR r3, [r2], #4 @h[12], h[13]
+ LDRSH r6, [r1], #2 @x[13]
+ LDRSH r9, [r1], #2 @x[14]
+
+ SMLABB r10, r4, r3, r10 @x[12] * h[12]
+ SMLABB r11, r6, r3, r11 @x[13] * h[12]
+
+ SMLABT r10, r6, r3, r10 @x[13] * h[13]
+ SMLABT r11, r9, r3, r11 @x[14] * h[13]
+
+ LDR r3, [r2], #4 @h[14], h[15]
+ LDRSH r4, [r1], #2 @x[15]
+ LDRSH r6, [r1], #2 @x[16]
+
+ SMLABB r10, r9, r3, r10 @x[14] * h[14]
+ SMLABB r11, r4, r3, r11 @x[15] * h[14]
+
+ SMLABT r10, r4, r3, r10 @x[15] * h[15]
+ SMLABT r11, r6, r3, r11 @x[16] * h[15]
+
+ LDR r3, [r2], #4 @h[16], h[17]
+ LDRSH r9, [r1], #2 @x[17]
+ LDRSH r4, [r1], #2 @x[18]
+
+ SMLABB r10, r6, r3, r10 @x[16] * h[16]
+ SMLABB r11, r9, r3, r11 @x[17] * h[16]
+
+ SMLABT r10, r9, r3, r10 @x[17] * h[17]
+ SMLABT r11, r4, r3, r11 @x[18] * h[17]
+
+ LDR r3, [r2], #4 @h[18], h[19]
+ LDRSH r6, [r1], #2 @x[19]
+ LDRSH r9, [r1], #2 @x[20]
+
+ SMLABB r10, r4, r3, r10 @x[18] * h[18]
+ SMLABB r11, r6, r3, r11 @x[19] * h[18]
+
+ SMLABT r10, r6, r3, r10 @x[19] * h[19]
+ SMLABT r11, r9, r3, r11 @x[20] * h[19]
+
+ LDR r3, [r2], #4 @h[20], h[21]
+ LDRSH r4, [r1], #2 @x[21]
+ LDRSH r6, [r1], #2 @x[22]
+
+ SMLABB r10, r9, r3, r10 @x[20] * h[20]
+ SMLABB r11, r4, r3, r11 @x[21] * h[20]
+
+ SMLABT r10, r4, r3, r10 @x[21] * h[21]
+ SMLABT r11, r6, r3, r11 @x[22] * h[21]
+
+ LDR r3, [r2], #4 @h[22], h[23]
+ LDRSH r9, [r1], #2 @x[23]
+ LDRSH r4, [r1], #2 @x[24]
+
+ SMLABB r10, r6, r3, r10 @x[22] * h[22]
+ SMLABB r11, r9, r3, r11 @x[23] * h[22]
+
+ SMLABT r10, r9, r3, r10 @x[23] * h[23]
+ SMLABT r11, r4, r3, r11 @x[24] * h[23]
+
+ LDR r3, [r2], #4 @h[24], h[25]
+ LDRSH r6, [r1], #2 @x[25]
+ LDRSH r9, [r1], #2 @x[26]
+
+ SMLABB r10, r4, r3, r10 @x[24] * h[24]
+ SMLABB r11, r6, r3, r11 @x[25] * h[24]
+
+ SMLABT r10, r6, r3, r10 @x[25] * h[25]
+ SMLABT r11, r9, r3, r11 @x[26] * h[25]
+
+ LDR r3, [r2], #4 @h[26], h[27]
+ LDRSH r4, [r1], #2 @x[27]
+ LDRSH r6, [r1], #2 @x[28]
+
+ SMLABB r10, r9, r3, r10 @x[26] * h[26]
+ SMLABB r11, r4, r3, r11 @x[27] * h[26]
+
+ SMLABT r10, r4, r3, r10 @x[27] * h[27]
+ SMLABT r11, r6, r3, r11 @x[28] * h[27]
+
+ LDR r3, [r2], #4 @h[28], h[29]
+ LDRSH r9, [r1], #2 @x[29]
+ LDRSH r4, [r1], #2 @x[30]
+
+ SMLABB r10, r6, r3, r10 @x[28] * h[28]
+ SMLABB r11, r9, r3, r11 @x[29] * h[28]
+
+ SMLABT r10, r9, r3, r10 @x[29] * h[29]
+ SMLABT r11, r4, r3, r11 @x[30] * h[29]
+
+ LDR r3, [r2], #4 @h[30], h[31]
+ LDRSH r6, [r1], #2 @x[31]
+ LDRSH r9, [r1], #2 @x[32]
+
+ SMLABB r10, r4, r3, r10 @x[30] * h[30]
+ SMLABB r11, r6, r3, r11 @x[31] * h[30]
+
+ SMLABT r10, r6, r3, r10 @x[31] * h[31]
+ SMLABT r11, r9, r3, r11 @x[32] * h[31]
+
+ @SSAT r10, #32, r10, LSL #2
+ @SSAT r11, #32, r11, LSL #2
+ MOV r10, r10, LSL #1
+ MOV r11, r11, LSL #1
+
+ QADD r10, r10, r10
+ QADD r11, r11, r11
+
+ QADD r10, r10, r5
+ QADD r11, r11, r5
+
+ MOV r10, r10, ASR #16
+ MOV r11, r11, ASR #16
+
+ STRH r10, [r0], #2
+ STRH r11, [r0], #2
+
+
+pred_lt4_end:
+ LDMFD r13!, {r4 - r12, r15}
+
+Table:
+ .word inter4_2
+ @ENDFUNC
+ .END
+
+
+
+
diff --git a/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/residu_asm_opt.s b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/residu_asm_opt.s new file mode 100644 index 0000000..060d9c7 --- /dev/null +++ b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/residu_asm_opt.s @@ -0,0 +1,228 @@ +@/*
+@ ** Copyright 2003-2010, VisualOn, Inc.
+@ **
+@ ** Licensed under the Apache License, Version 2.0 (the "License");
+@ ** you may not use this file except in compliance with the License.
+@ ** You may obtain a copy of the License at
+@ **
+@ ** http://www.apache.org/licenses/LICENSE-2.0
+@ **
+@ ** Unless required by applicable law or agreed to in writing, software
+@ ** distributed under the License is distributed on an "AS IS" BASIS,
+@ ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+@ ** See the License for the specific language governing permissions and
+@ ** limitations under the License.
+@ */
+@
+@void Residu(
+@ Word16 a[], /* (i) Q12 : prediction coefficients */
+@ Word16 x[], /* (i) : speech (values x[-m..-1] are needed */
+@ Word16 y[], /* (o) x2 : residual signal */
+@ Word16 lg /* (i) : size of filtering */
+@ )
+@a[] --- r0
+@x[] --- r1
+@y[] --- r2
+@lg --- r3
+
+ .section .text
+ .global Residu_opt
+
+Residu_opt:
+
+ STMFD r13!, {r4 - r12, r14}
+
+ LDRH r5, [r0], #2
+ LDRH r6, [r0], #2
+ ORR r5, r6, r5, LSL #16 @r5 --- a0, a1
+
+ LDRH r6, [r0], #2
+ LDRH r7, [r0], #2
+ ORR r6, r7, r6, LSL #16 @r6 --- a2, a3
+
+ LDRH r7, [r0], #2
+ LDRH r8, [r0], #2
+ ORR r7, r8, r7, LSL #16 @r7 --- a4, a5
+
+ LDRH r8, [r0], #2
+ LDRH r9, [r0], #2
+ ORR r8, r9, r8, LSL #16 @r8 --- a6, a7
+
+ LDRH r9, [r0], #2
+ LDRH r10, [r0], #2
+ ORR r9, r10, r9, LSL #16 @r9 --- a8, a9
+
+ LDRH r10, [r0], #2
+ LDRH r11, [r0], #2
+ ORR r10, r11, r10, LSL #16 @r10 --- a10, a11
+
+ LDRH r11, [r0], #2
+ LDRH r12, [r0], #2
+ ORR r11, r12, r11, LSL #16 @r11 --- a12, a13
+
+ LDRH r12, [r0], #2
+ LDRH r4, [r0], #2
+ ORR r12, r4, r12, LSL #16 @r12 --- a14, a15
+
+
+ STMFD r13!, {r8 - r12} @store r8-r12
+ LDRH r4, [r0], #2 @load a16
+ MOV r14, r3, ASR #2 @one loop get 4 outputs
+ ADD r1, r1, #4
+ MOV r0, r2
+ ORR r14, r4, r14, LSL #16 @r14 --- loopnum, a16
+
+residu_loop:
+
+ LDR r10, [r1], #-4 @r10 --- x[3], x[2]
+ LDR r2, [r1], #-4 @r2 --- x[1], x[0]
+
+ SMULTB r3, r5, r2 @i1(0) --- r3 = x[0] * a0
+ SMULTT r4, r5, r2 @i2(0) --- r4 = x[1] * a0
+ SMULTB r11, r5, r10 @i3(0) --- r11 = x[2] * a0
+ SMULTT r12, r5, r10 @i4(0) --- r12 = x[3] * a0
+
+ SMLABB r4, r5, r2, r4 @i2(1) --- r4 += x[0] * a1
+ SMLABT r11, r5, r2, r11 @i3(1) --- r11 += x[1] * a0
+ SMLABB r12, r5, r10, r12 @i4(1) --- r12 += x[2] * a1
+
+ SMLATB r11, r6, r2, r11 @i3(2) --- r11 += x[0] * a2
+ SMLATT r12, r6, r2, r12 @i4(2) --- r12 += x[1] * a2
+ SMLABB r12, r6, r2, r12 @i4(3) --- r12 += x[0] * a3
+
+ LDR r2, [r1], #-4 @r2 ---- x[-1], x[-2]
+
+ SMLABT r3, r5, r2, r3 @i1(1) --- r3 += x[-1] * a1
+ SMLATT r4, r6, r2, r4 @i2(2) --- r4 += x[-1] * a2
+ SMLABT r11, r6, r2, r11 @i3(3) --- r11 += x[-1] * a3
+ SMLATT r12, r7, r2, r12 @i4(4) --- r12 += x[-1] * a4
+ SMLATB r3, r6, r2, r3 @i1(2) --- r3 += x[-2] * a2
+
+ SMLABB r4, r6, r2, r4 @ i2 (3)
+ SMLATB r11,r7, r2, r11 @ i3 (4)
+ SMLABB r12,r7, r2, r12 @ i4 (5)
+
+ LDR r2,[r1],#-4
+ SMLABT r3, r6, r2, r3 @ i1 (3)
+ SMLATT r4, r7, r2, r4 @ i2 (4)
+ SMLABT r11,r7, r2, r11 @ i3 (5)
+ SMLATT r12,r8, r2, r12 @ i4 (6)
+ SMLATB r3, r7, r2, r3 @ i1 (4)
+ SMLABB r4, r7, r2, r4 @ i2 (5)
+ SMLATB r11,r8, r2, r11 @ i3 (6)
+ SMLABB r12,r8, r2, r12 @ i4 (7)
+
+ LDR r2,[r1],#-4
+ SMLABT r3, r7, r2, r3 @ i1 (5)
+ SMLATT r4, r8, r2, r4 @ i2 (6)
+ SMLABT r11,r8, r2, r11 @ i3 (7)
+ SMLATT r12,r9, r2, r12 @ i4 (8)
+ SMLATB r3, r8, r2, r3 @ i1 (6)
+ SMLABB r4, r8, r2, r4 @ i2 (7)
+ SMLATB r11,r9, r2, r11 @ i3 (8)
+ SMLABB r12,r9, r2, r12 @ i4 (9)
+ LDR r10, [r13, #8] @ [ a10 | a11]
+
+ LDR r2,[r1],#-4
+ SMLABT r3, r8, r2, r3 @ i1 (7)
+ SMLATT r4, r9, r2, r4 @ i2 (8)
+ SMLABT r11,r9, r2, r11 @ i3 (9)
+ SMLATT r12,r10, r2, r12 @ i4 (10)
+ SMLATB r3, r9, r2, r3 @ i1 (8)
+ SMLABB r4, r9, r2, r4 @ i2 (9)
+ SMLATB r11,r10, r2, r11 @ i3 (10)
+ SMLABB r12,r10, r2, r12 @ i4 (11)
+ LDR r8, [r13, #12] @ [ a12 | a13 ]
+
+ LDR r2,[r1],#-4
+ SMLABT r3, r9, r2, r3 @ i1 (9)
+ SMLATT r4, r10, r2, r4 @ i2 (10)
+ SMLABT r11,r10, r2, r11 @ i3 (11)
+ SMLATT r12,r8, r2, r12 @ i4 (12)
+ SMLATB r3, r10, r2, r3 @ i1 (10)
+ SMLABB r4, r10, r2, r4 @ i2 (11)
+ SMLATB r11,r8, r2, r11 @ i3 (12)
+ SMLABB r12,r8, r2, r12 @ i4 (13)
+ LDR r9, [r13, #16] @ [ a14 | a15 ]
+
+ LDR r2,[r1],#-4
+ SMLABT r3, r10, r2, r3 @ i1 (11)
+ SMLATT r4, r8, r2, r4 @ i2 (12)
+ SMLABT r11,r8, r2, r11 @ i3 (13)
+ SMLATT r12,r9, r2, r12 @ i4 (14)
+ SMLATB r3, r8, r2, r3 @ i1 (12)
+ SMLABB r4, r8, r2, r4 @ i2 (13)
+ SMLATB r11,r9, r2, r11 @ i3 (14)
+ SMLABB r12,r9, r2, r12 @ i4 (15)
+
+
+ LDR r2,[r1],#-4
+ SMLABT r3, r8, r2, r3 @ i1 (13)
+ SMLATT r4, r9, r2, r4 @ i2 (14)
+ SMLABT r11,r9, r2, r11 @ i3 (15)
+ SMLABT r12,r14, r2, r12 @ i4 (16)
+ SMLATB r3, r9, r2, r3 @ i1 (14)
+ SMLABB r4, r9, r2, r4 @ i2 (15)
+ SMLABB r11,r14, r2, r11 @ i3 (16)
+ LDR r8, [r13] @ [ a6 | a7 ]
+
+ LDR r2,[r1],#44 @ Change
+ SMLABT r3, r9, r2, r3
+ SMLABB r3, r14, r2, r3
+ SMLABT r4, r14, r2, r4
+ LDR r9, [r13, #4] @ [ a8 | a9 ]
+
+
+ QADD r3,r3,r3
+ QADD r4,r4,r4
+ QADD r11,r11,r11
+ QADD r12,r12,r12
+
+ QADD r3,r3,r3
+ QADD r4,r4,r4
+ QADD r11,r11,r11
+ QADD r12,r12,r12
+
+ QADD r3,r3,r3
+ QADD r4,r4,r4
+ QADD r11,r11,r11
+ QADD r12,r12,r12
+
+ QADD r3,r3,r3
+ QADD r4,r4,r4
+ QADD r11,r11,r11
+ QADD r12,r12,r12
+
+ MOV r2,#32768
+
+ QDADD r3,r2,r3
+ QDADD r4,r2,r4
+ QDADD r11,r2,r11
+ QDADD r12,r2,r12
+
+
+ MOV r3,r3,asr #16
+ MOV r4,r4,asr #16
+ MOV r11,r11,asr #16
+ MOV r12,r12,asr #16
+
+ STRH r3,[r0],#2
+ STRH r4,[r0],#2
+ STRH r11,[r0],#2
+ STRH r12,[r0],#2
+
+ MOV r2,r14,asr #16
+ SUB r14, r14, #0x10000
+ SUBS r2,r2,#1
+ BNE residu_loop
+end:
+ LDMFD r13!, {r8 -r12}
+ LDMFD r13!, {r4 -r12,pc}
+
+ @ENDFUNC
+ .END
+
+
+
+
+
diff --git a/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/scale_sig_opt.s b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/scale_sig_opt.s new file mode 100644 index 0000000..aa9f464 --- /dev/null +++ b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/scale_sig_opt.s @@ -0,0 +1,75 @@ +@/*
+@ ** Copyright 2003-2010, VisualOn, Inc.
+@ **
+@ ** Licensed under the Apache License, Version 2.0 (the "License");
+@ ** you may not use this file except in compliance with the License.
+@ ** You may obtain a copy of the License at
+@ **
+@ ** http://www.apache.org/licenses/LICENSE-2.0
+@ **
+@ ** Unless required by applicable law or agreed to in writing, software
+@ ** distributed under the License is distributed on an "AS IS" BASIS,
+@ ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+@ ** See the License for the specific language governing permissions and
+@ ** limitations under the License.
+@ */
+@
+@void Scale_sig(
+@ Word16 x[], /* (i/o) : signal to scale */
+@ Word16 lg, /* (i) : size of x[] */
+@ Word16 exp /* (i) : exponent: x = round(x << exp) */
+@ )
+@
+@r0 --- x[]
+@r1 --- lg
+@r2 --- exp
+
+ .section .text
+ .global Scale_sig_opt
+
+Scale_sig_opt:
+
+ STMFD r13!, {r4 - r12, r14}
+ SUB r3, r1, #1 @i = lg - 1
+ CMP r2, #0 @Compare exp and 0
+ RSB r7, r2, #0 @exp = -exp
+ ADD r10, r2, #16 @16 + exp
+ ADD r4, r0, r3, LSL #1 @x[i] address
+ MOV r8, #0x7fffffff
+ MOV r9, #0x8000
+ BLE LOOP2
+
+LOOP1:
+
+ LDRSH r5, [r4] @load x[i]
+ MOV r12, r5, LSL r10
+ TEQ r5, r12, ASR r10
+ EORNE r12, r8, r5, ASR #31
+ SUBS r3, r3, #1
+ QADD r11, r12, r9
+ MOV r12, r11, ASR #16
+ STRH r12, [r4], #-2
+ BGE LOOP1
+ BL The_end
+
+LOOP2:
+
+ LDRSH r5, [r4] @load x[i]
+ MOV r6, r5, LSL #16 @L_tmp = x[i] << 16
+ MOV r5, r6, ASR r7 @L_tmp >>= exp
+ QADD r11, r5, r9
+ MOV r12, r11, ASR #16
+ SUBS r3, r3, #1
+ STRH r12, [r4], #-2
+ BGE LOOP2
+
+The_end:
+ LDMFD r13!, {r4 - r12, r15}
+
+ @ENDFUNC
+ .END
+
+
+
+
+
diff --git a/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/syn_filt_opt.s b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/syn_filt_opt.s new file mode 100644 index 0000000..e05e9e0 --- /dev/null +++ b/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/syn_filt_opt.s @@ -0,0 +1,238 @@ +@/*
+@ ** Copyright 2003-2010, VisualOn, Inc.
+@ **
+@ ** Licensed under the Apache License, Version 2.0 (the "License");
+@ ** you may not use this file except in compliance with the License.
+@ ** You may obtain a copy of the License at
+@ **
+@ ** http://www.apache.org/licenses/LICENSE-2.0
+@ **
+@ ** Unless required by applicable law or agreed to in writing, software
+@ ** distributed under the License is distributed on an "AS IS" BASIS,
+@ ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+@ ** See the License for the specific language governing permissions and
+@ ** limitations under the License.
+@ */
+@**********************************************************************/
+@void Syn_filt(
+@ Word16 a[], /* (i) Q12 : a[m+1] prediction coefficients */
+@ Word16 x[], /* (i) : input signal */
+@ Word16 y[], /* (o) : output signal */
+@ Word16 mem[], /* (i/o) : memory associated with this filtering. */
+@)
+@***********************************************************************
+@ a[] --- r0
+@ x[] --- r1
+@ y[] --- r2
+@ mem[] --- r3
+@ m --- 16 lg --- 80 update --- 1
+
+ .section .text
+ .global Syn_filt_asm
+ .extern voAWB_Copy
+
+Syn_filt_asm:
+
+ STMFD r13!, {r4 - r12, r14}
+ SUB r13, r13, #700 @ y_buf[L_FRAME16k + M16k]
+
+ MOV r4, r3 @ copy mem[] address
+ MOV r5, r13 @ copy yy = y_buf address
+
+ @ for(i = 0@ i < m@ i++)
+ @{
+ @ *yy++ = mem[i]@
+ @}
+
+ LDRH r6, [r4], #2
+ LDRH r7, [r4], #2
+ LDRH r8, [r4], #2
+ LDRH r9, [r4], #2
+ LDRH r10, [r4], #2
+ LDRH r11, [r4], #2
+ LDRH r12, [r4], #2
+ LDRH r14, [r4], #2
+
+ STRH r6, [r5], #2
+ STRH r7, [r5], #2
+ STRH r8, [r5], #2
+ STRH r9, [r5], #2
+ STRH r10, [r5], #2
+ STRH r11, [r5], #2
+ STRH r12, [r5], #2
+ STRH r14, [r5], #2
+
+ LDRH r6, [r4], #2
+ LDRH r7, [r4], #2
+ LDRH r8, [r4], #2
+ LDRH r9, [r4], #2
+ LDRH r10, [r4], #2
+ LDRH r11, [r4], #2
+ LDRH r12, [r4], #2
+ LDRH r14, [r4], #2
+
+ STRH r6, [r5], #2
+ STRH r7, [r5], #2
+ STRH r8, [r5], #2
+ STRH r9, [r5], #2
+ STRH r10, [r5], #2
+ STRH r11, [r5], #2
+ STRH r12, [r5], #2
+ STRH r14, [r5], #2
+
+ LDRSH r5, [r0] @ load a[0]
+ MOV r8, #0 @ i = 0
+ MOV r5, r5, ASR #1 @ a0 = a[0] >> 1
+ @MOV r4, r13
+ @ load all a[]
+
+ LDR r14, =0xffff
+ LDRSH r6, [r0, #2] @ load a[1]
+ LDRSH r7, [r0, #4] @ load a[2]
+ LDRSH r9, [r0, #6] @ load a[3]
+ LDRSH r11,[r0, #8] @ load a[4]
+ AND r6, r6, r14
+ AND r9, r9, r14
+ ORR r10, r6, r7, LSL #16 @ -a[2] -- -a[1]
+ ORR r12, r9, r11, LSL #16 @ -a[4] -- -a[3]
+ STR r10, [r13, #-4]
+ STR r12, [r13, #-8]
+
+ LDRSH r6, [r0, #10] @ load a[5]
+ LDRSH r7, [r0, #12] @ load a[6]
+ LDRSH r9, [r0, #14] @ load a[7]
+ LDRSH r11,[r0, #16] @ load a[8]
+ AND r6, r6, r14
+ AND r9, r9, r14
+ ORR r10, r6, r7, LSL #16 @ -a[6] -- -a[5]
+ ORR r12, r9, r11, LSL #16 @ -a[8] -- -a[7]
+ STR r10, [r13, #-12]
+ STR r12, [r13, #-16]
+
+ LDRSH r6, [r0, #18] @ load a[9]
+ LDRSH r7, [r0, #20] @ load a[10]
+ LDRSH r9, [r0, #22] @ load a[11]
+ LDRSH r11,[r0, #24] @ load a[12]
+ AND r6, r6, r14
+ AND r9, r9, r14
+ ORR r10, r6, r7, LSL #16 @ -a[10] -- -a[9]
+ ORR r12, r9, r11, LSL #16 @ -a[12] -- -a[11]
+ STR r10, [r13, #-20]
+ STR r12, [r13, #-24]
+
+ LDRSH r6, [r0, #26] @ load a[13]
+ LDRSH r7, [r0, #28] @ load a[14]
+ LDRSH r9, [r0, #30] @ load a[15]
+ LDRSH r11,[r0, #32] @ load a[16]
+ AND r6, r6, r14
+ AND r9, r9, r14
+ ORR r10, r6, r7, LSL #16 @ -a[14] -- -a[13]
+ ORR r12, r9, r11, LSL #16 @ -a[16] -- -a[15]
+ STR r10, [r13, #-28]
+ STR r12, [r13, #-32]
+
+ ADD r4, r13, #32
+LOOP:
+ LDRSH r6, [r1], #2 @ load x[i]
+ ADD r10, r4, r8, LSL #1 @ temp_p = yy + i
+
+ MUL r0, r5, r6 @ L_tmp = x[i] * a0
+ @ for(j = 1@ j <= m, j+=8)
+ LDR r7, [r13, #-4] @ -a[2] -a[1]
+ LDRSH r9, [r10, #-2] @ *(temp_p - 1)
+ LDRSH r12, [r10, #-4] @ *(temp_p - 2)
+
+
+ SMULBB r14, r9, r7 @ -a[1] * (*(temp_p -1))
+
+ LDRSH r6, [r10, #-6] @ *(temp_p - 3)
+
+ SMLABT r14, r12, r7, r14 @ -a[2] * (*(temp_p - 2))
+
+ LDR r7, [r13, #-8] @ -a[4] -a[3]
+ LDRSH r11, [r10, #-8] @ *(temp_p - 4)
+
+ SMLABB r14, r6, r7, r14 @ -a[3] * (*(temp_p -3))
+
+ LDRSH r9, [r10, #-10] @ *(temp_p - 5)
+
+ SMLABT r14, r11, r7, r14 @ -a[4] * (*(temp_p -4))
+
+ LDR r7, [r13, #-12] @ -a[6] -a[5]
+ LDRSH r12, [r10, #-12] @ *(temp_p - 6)
+
+ SMLABB r14, r9, r7, r14 @ -a[5] * (*(temp_p -5))
+
+ LDRSH r6, [r10, #-14] @ *(temp_p - 7)
+
+ SMLABT r14, r12, r7, r14 @ -a[6] * (*(temp_p - 6))
+
+ LDR r7, [r13, #-16] @ -a[8] -a[7]
+ LDRSH r11, [r10, #-16] @ *(temp_p - 8)
+
+ SMLABB r14, r6, r7, r14 @ -a[7] * (*(temp_p -7))
+
+ LDRSH r9, [r10, #-18] @ *(temp_p - 9)
+
+ SMLABT r14, r11, r7, r14 @ -a[8] * (*(temp_p -8))
+
+ LDR r7, [r13, #-20] @ -a[10] -a[9]
+ LDRSH r12, [r10, #-20] @ *(temp_p - 10)
+
+ SMLABB r14, r9, r7, r14 @ -a[9] * (*(temp_p -9))
+
+ LDRSH r6, [r10, #-22] @ *(temp_p - 11)
+
+ SMLABT r14, r12, r7, r14 @ -a[10] * (*(temp_p - 10))
+
+ LDR r7, [r13, #-24] @ -a[12] -a[11]
+ LDRSH r11, [r10, #-24] @ *(temp_p - 12)
+
+ SMLABB r14, r6, r7, r14 @ -a[11] * (*(temp_p -11))
+
+ LDRSH r9, [r10, #-26] @ *(temp_p - 13)
+
+ SMLABT r14, r11, r7, r14 @ -a[12] * (*(temp_p -12))
+
+ LDR r7, [r13, #-28] @ -a[14] -a[13]
+ LDRSH r12, [r10, #-28] @ *(temp_p - 14)
+
+ SMLABB r14, r9, r7, r14 @ -a[13] * (*(temp_p -13))
+
+ LDRSH r6, [r10, #-30] @ *(temp_p - 15)
+
+ SMLABT r14, r12, r7, r14 @ -a[14] * (*(temp_p - 14))
+
+ LDR r7, [r13, #-32] @ -a[16] -a[15]
+ LDRSH r11, [r10, #-32] @ *(temp_p - 16)
+
+ SMLABB r14, r6, r7, r14 @ -a[15] * (*(temp_p -15))
+
+ SMLABT r14, r11, r7, r14 @ -a[16] * (*(temp_p -16))
+
+ RSB r14, r14, r0
+
+ MOV r7, r14, LSL #4 @ L_tmp <<=4
+ ADD r8, r8, #1
+ ADD r14, r7, #0x8000
+ MOV r7, r14, ASR #16 @ (L_tmp + 0x8000) >> 16
+ CMP r8, #80
+ STRH r7, [r10] @ yy[i]
+ STRH r7, [r2], #2 @ y[i]
+ BLT LOOP
+
+ @ update mem[]
+ ADD r5, r13, #160 @ yy[64] address
+ MOV r1, r3
+ MOV r0, r5
+ MOV r2, #16
+ BL voAWB_Copy
+
+Syn_filt_asm_end:
+
+ ADD r13, r13, #700
+ LDMFD r13!, {r4 - r12, r15}
+ @ENDFUNC
+ .END
+
+
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