gcbv: update source files to match kernel

Change-Id: If69ec9850652fc2060c70d852e08abcb141f60a0
Signed-off-by: Bo Najdrovsky <bo@ti.com>

8 files changed, 11605 insertions, 807 deletions

diff --git a/gcbv/gc2d.h b/gcbv/gc2d.h
new file mode 100644
index 0000000..2a10b6e
--- /dev/null
+++ b/gcbv/gc2d.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2011, Texas Instruments, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Texas Instruments, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL TEXAS INSTRUMENTS, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef GC2D_H
+#define GC2D_H
+
+#include <bltsville.h>
+#include <bvinternal.h>
+#include <ocd.h>
+
+enum bverror bv_map(struct bvbuffdesc *buffdesc);
+enum bverror bv_unmap(struct bvbuffdesc *buffdesc);
+enum bverror bv_blt(struct bvbltparams *bltparams);
+
+#endif
diff --git a/gcbv/gcbv.c b/gcbv/gcbv.c
index 103325d..a1a442c 100644
--- a/gcbv/gcbv.c
+++ b/gcbv/gcbv.c
@@ -1,276 +1,441 @@
 /*
- * Copyright (c) 2011, Texas Instruments, Inc.
- * All rights reserved.
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2012 Vivante Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2012 Vivante Corporation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Texas Instruments, Inc. nor the names of its
- *       contributors may be used to endorse or promote products derived from
- *       this software without specific prior written permission.
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Vivante Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL TEXAS INSTRUMENTS, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <stdio.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <errno.h>
-#include <pthread.h>
-#include <string.h>
-#include <fcntl.h> /* open() */
-#include <sys/ioctl.h>
-#include <unistd.h> /* close() */
-#include <sys/signal.h>
-#include "bv.h"
-#include "bltsville.h"
-#include "ocd.h"
-#include "gcreg.h"
-
-#if !defined(COUNTOF)
-#	define COUNTOF(a) (sizeof(a) / sizeof(a[0]))
+#include <gcx.h>
+#include <gcioctl.h>
+#include <gc2d.h>
+#include "gcmain.h"
+
+#ifndef GC_DUMP
+#	define GC_DUMP 0
 #endif
 
-#define GET_2D_RESRC_USAGE(fg_rop, bg_rop, use_src, use_dest) \
-{ \
-	uint8_t target_only = \
-	((fg_rop == 0x00) && (bg_rop == 0x00)) ||  /* Blackness.    */ \
-	((fg_rop == 0x55) && (bg_rop == 0x55)) ||  /* Invert.       */ \
-	((fg_rop == 0xAA) && (bg_rop == 0xAA)) ||  /* No operation. */ \
-	((fg_rop == 0xFF) && (bg_rop == 0xFF));    /* Whiteness.    */ \
-	\
-	use_src = !target_only && \
-			((((fg_rop >> 2) & 0x33) != (fg_rop & 0x33)) || \
-				(((bg_rop >> 2) & 0x33) != (bg_rop & 0x33))); \
-	\
-	use_dest = (((fg_rop >> 1) & 0x55) != (fg_rop & 0x55)) || \
-			(((bg_rop >> 1) & 0x55) != (bg_rop & 0x55)); \
+#if GC_DUMP
+#	define GC_PRINT gcdump
+#else
+#	define GC_PRINT(...)
+#endif
+
+/*******************************************************************************
+** Miscellaneous defines and macros.
+*/
+
+#define EQ_ORIGIN(rect1, rect2) \
+( \
+	(rect1.left == rect2.left) && (rect1.top == rect2.top) \
+)
+
+#define EQ_SIZE(rect1, rect2) \
+( \
+	(rect1.width == rect2.width) && (rect1.height == rect2.height) \
+)
+
+#define STRUCTSIZE(structptr, lastmember) \
+( \
+	(size_t) &structptr->lastmember + \
+	sizeof(structptr->lastmember) - \
+	(size_t) structptr \
+)
+
+#define GET_MAP_HANDLE(map) \
+( \
+	((struct bvbuffmapinfo *) map->handle)->handle \
+)
+
+#define GC_CLIP_RESET_LEFT	((unsigned short) 0)
+#define GC_CLIP_RESET_TOP	((unsigned short) 0)
+#define GC_CLIP_RESET_RIGHT	((unsigned short) ((1 << 15) - 1))
+#define GC_CLIP_RESET_BOTTOM	((unsigned short) ((1 << 15) - 1))
+
+#define GC_BASE_ALIGN	16
+
+#define GPU_CMD_SIZE	(sizeof(unsigned int) * 2)
+
+/*******************************************************************************
+** Internal structures.
+*/
+
+/* Used by blitters to define an array of valid sources. */
+struct srcdesc {
+	int index;
+	union bvinbuff buf;
+	struct bvsurfgeom *geom;
+	struct bvrect *rect;
+};
+
+/* bvbuffmap struct attachment. */
+struct bvbuffmapinfo {
+	unsigned long handle;	/* Mapped handle for the buffer. */
+
+	int usermap;		/* Number of times the client explicitely
+				   mapped this buffer. */
+
+	int automap;		/* Number of times automapping happened. */
+};
+
+/* Defines a link list of scheduled unmappings. */
+struct gcschedunmap {
+	struct bvbuffdesc *bvbuffdesc;
+	struct gcschedunmap *next;
+};
+
+/* Operation finalization call. */
+struct gcbatch;
+typedef enum bverror (*gcbatchend) (struct bvbltparams *bltparams,
+					struct gcbatch *batch);
+
+/* Blit states. */
+struct gcblit {
+	unsigned int srccount;
+	struct gccmdstartderect dstrect;
+};
+
+/* Batch header. */
+struct gcbatch {
+	unsigned int structsize;	/* Used to ID structure version. */
+
+	gcbatchend batchend;		/* Pointer to the function to finilize
+					   the current operation. */
+	union {
+		struct gcblit gcblit;
+	} op;				/* States of the current operation. */
+
+	unsigned int size;		/* Total size of the command buffer. */
+
+	struct gcbuffer *bufhead;	/* Command buffer list. */
+	struct gcbuffer *buftail;
+
+	struct gcschedunmap *unmap;	/* Scheduled unmappings. */
+};
+
+/* Vacant batch header. */
+struct gcvacbatch {
+	struct gcvacbatch *next;
+};
+
+/* Driver context. */
+struct gccontext {
+	char bverrorstr[128];		/* Last generated error message. */
+
+	struct bvbuffmap *vac_buffmap;	/* Vacant mappping structures. */
+	struct gcschedunmap *vac_unmap;	/* Vacant unmapping structures. */
+
+	struct gcbuffer *vac_buffers;	/* Vacant command buffers. */
+	struct gcfixup *vac_fixups;	/* Vacant fixups. */
+	struct gcvacbatch *vac_batches;	/* Vacant batches. */
+};
+
+static struct gccontext gccontext;
+
+/*******************************************************************************
+ * Debugging.
+ */
+
+#if GC_DUMP
+static void dumpbuffer(struct gcbatch *batch)
+{
+	unsigned int bufcount = 0;
+	struct gcbuffer *buffer;
+	unsigned int datacount, i, j, cmd;
+	struct gcfixup *fixup;
+
+	GC_PRINT(GC_INFO_MSG " BATCH DUMP (0x%08X)\n",
+		__func__, __LINE__, (unsigned int) batch);
+
+	buffer = batch->bufhead;
+	while (buffer != NULL) {
+		GC_PRINT(GC_INFO_MSG "   Command buffer #%d (0x%08X)\n",
+			__func__, __LINE__, ++bufcount, (unsigned int) buffer);
+
+		fixup = buffer->fixuphead;
+		while (fixup != NULL) {
+			GC_PRINT(GC_INFO_MSG
+				"   Fixup table @ 0x%08X, count = %d:\n",
+				__func__, __LINE__,
+				(unsigned int) fixup, fixup->count);
+
+			for (i = 0; i < fixup->count; i += 1) {
+				GC_PRINT(GC_INFO_MSG
+					"   [%02d] buffer offset = 0x%08X, "
+					"surface offset = 0x%08X\n",
+					__func__, __LINE__,
+					i,
+					fixup->fixup[i].dataoffset * 4,
+					fixup->fixup[i].surfoffset);
+			}
+
+			fixup = fixup->next;
+		}
+
+		datacount = buffer->tail - buffer->head;
+		for (i = 0; i < datacount;) {
+			cmd = GETFIELD(buffer->head[i],
+					GCREG_COMMAND_LOAD_STATE,
+					COMMAND_OPCODE);
+
+			if (cmd == REGVALUE(GCREG_COMMAND_LOAD_STATE,
+						COMMAND_OPCODE, LOAD_STATE)) {
+				unsigned int count, addr;
+
+				count = GETFIELD(buffer->head[i],
+					GCREG_COMMAND_LOAD_STATE,
+					COMMAND_COUNT);
+
+				addr = GETFIELD(buffer->head[i],
+					GCREG_COMMAND_LOAD_STATE,
+					COMMAND_ADDRESS);
+
+				GC_PRINT(GC_INFO_MSG
+					"     0x%08X: 0x%08X  STATE(0x%04X, %d)\n",
+					__func__, __LINE__,
+					(i << 2), buffer->head[i], addr, count);
+				i += 1;
+
+				count |= 1;
+				for (j = 0; j < count; i += 1, j += 1) {
+					GC_PRINT(GC_INFO_MSG " %16c0x%08X\n",
+						__func__, __LINE__,
+						' ', buffer->head[i]);
+				}
+			} else if (cmd == REGVALUE(GCREG_COMMAND_START_DE,
+						COMMAND_OPCODE, START_DE)) {
+				unsigned int count;
+				unsigned int x1, y1, x2, y2;
+
+				count = GETFIELD(buffer->head[i],
+					GCREG_COMMAND_START_DE,
+					COMMAND_COUNT);
+
+				GC_PRINT(GC_INFO_MSG
+					"     0x%08X: 0x%08X  STARTDE(%d)\n",
+					__func__, __LINE__,
+					(i << 2), buffer->head[i], count);
+				i += 1;
+
+				GC_PRINT(GC_INFO_MSG " %16c0x%08X\n",
+					__func__, __LINE__,
+					' ', buffer->head[i]);
+				i += 1;
+
+				for (j = 0; j < count; j += 1) {
+					x1 = GETFIELD(buffer->head[i],
+						GCREG_COMMAND_TOP_LEFT, X);
+					y1 = GETFIELD(buffer->head[i],
+						GCREG_COMMAND_TOP_LEFT, Y);
+
+					GC_PRINT(GC_INFO_MSG
+						" %16c0x%08X  LT(%d,%d)\n",
+						__func__, __LINE__,
+						' ', buffer->head[i], x1, y1);
+
+					i += 1;
+
+					x2 = GETFIELD(buffer->head[i],
+						GCREG_COMMAND_BOTTOM_RIGHT, X);
+					y2 = GETFIELD(buffer->head[i],
+						GCREG_COMMAND_BOTTOM_RIGHT, Y);
+
+					GC_PRINT(GC_INFO_MSG
+						" %16c0x%08X  RB(%d,%d)\n",
+						__func__, __LINE__,
+						' ', buffer->head[i], x2, y2);
+
+					i += 1;
+				}
+			} else {
+				GC_PRINT(GC_INFO_MSG
+					" unsupported command: %d\n",
+					__func__, __LINE__, cmd);
+			}
+		}
+
+		buffer = buffer->next;
+	}
 }
+#endif
 
-#define CONVERT_DEST_FMT(ocdfmt) \
-	(ocdfmt == OCDFMT_ARGB12 ? AQDE_DEST_CONFIG_FORMAT_A4R4G4B4 : \
-	(ocdfmt == OCDFMT_1RGB15 ? AQDE_DEST_CONFIG_FORMAT_A1R5G5B5 : \
-	(ocdfmt == OCDFMT_xRGB16 ? AQDE_DEST_CONFIG_FORMAT_R5G6B5 : \
-	(ocdfmt == OCDFMT_ARGB24 ? AQDE_DEST_CONFIG_FORMAT_A8R8G8B8 : \
-	(ocdfmt == OCDFMT_BGRA24 ? AQDE_DEST_CONFIG_FORMAT_A8R8G8B8 : \
-	(ocdfmt == OCDFMT_RGBA24 ? AQDE_DEST_CONFIG_FORMAT_A8R8G8B8 : 0xFFFFFFFF))))))
-
-#define CONVERT_DEST_SWZZL(ocdfmt) \
-	(ocdfmt == OCDFMT_ARGB12 ? AQDE_DEST_CONFIG_SWIZZLE_RGBA : \
-	(ocdfmt == OCDFMT_1RGB15 ? AQDE_DEST_CONFIG_SWIZZLE_RGBA : \
-	(ocdfmt == OCDFMT_xRGB16 ? AQDE_DEST_CONFIG_SWIZZLE_RGBA : \
-	(ocdfmt == OCDFMT_ARGB24 ? AQDE_DEST_CONFIG_SWIZZLE_RGBA : \
-	(ocdfmt == OCDFMT_BGRA24 ? AQDE_DEST_CONFIG_SWIZZLE_ABGR : \
-	(ocdfmt == OCDFMT_RGBA24 ? AQDE_DEST_CONFIG_SWIZZLE_ARGB : 0xFFFFFFFF))))))
-
-#define CONVERT_SRC_FMT(ocdfmt) \
-	(ocdfmt == OCDFMT_ARGB12 ? AQDE_SRC_CONFIG_FORMAT_A4R4G4B4 : \
-	(ocdfmt == OCDFMT_1RGB15 ? AQDE_SRC_CONFIG_FORMAT_A1R5G5B5 : \
-	(ocdfmt == OCDFMT_xRGB16 ? AQDE_SRC_CONFIG_FORMAT_R5G6B5 : \
-	(ocdfmt == OCDFMT_ARGB24 ? AQDE_SRC_CONFIG_SOURCE_FORMAT_A8R8G8B8 : \
-	(ocdfmt == OCDFMT_BGRA24 ? AQDE_SRC_CONFIG_SOURCE_FORMAT_A8R8G8B8 : \
-	(ocdfmt == OCDFMT_RGBA24 ? AQDE_SRC_CONFIG_SOURCE_FORMAT_A8R8G8B8 : 0xFFFFFFFF))))))
-
-#define CONVERT_SRC_SWZZL(ocdfmt) \
-	(ocdfmt == OCDFMT_ARGB16 ? AQDE_SRC_CONFIG_SWIZZLE_RGBA : \
-	(ocdfmt == OCDFMT_ARGB24 ? AQDE_SRC_CONFIG_SWIZZLE_RGBA : \
-	(ocdfmt == OCDFMT_BGRA24 ? AQDE_SRC_CONFIG_SWIZZLE_ABGR : \
-	(ocdfmt == OCDFMT_RGBA24 ? AQDE_SRC_CONFIG_SWIZZLE_ARGB : 0xFFFFFFFF))))
-
-#define CONVERT_SRC1_FMT(ocdfmt) \
-	CONVERT_SRC_FMT(ocdfmt)
-
-#define CONVERT_SRC2_FMT(ocdfmt) \
-	CONVERT_SRC_FMT(ocdfmt)
-
-#define CONVERT_SRC_GCFMT(ocdfmt) \
-	(ocdfmt == OCDFMT_ARGB16 ? GCREG_DE_SRC_CONFIG_SOURCE_FORMAT_R5G6B5 : \
-	(ocdfmt == OCDFMT_ARGB24 ? GCREG_DE_SRC_CONFIG_SOURCE_FORMAT_A8R8G8B8 : \
-	(ocdfmt == OCDFMT_BGRA24 ? GCREG_DE_SRC_CONFIG_SOURCE_FORMAT_A8R8G8B8 : \
-	(ocdfmt == OCDFMT_RGBA24 ? GCREG_DE_SRC_CONFIG_SOURCE_FORMAT_A8R8G8B8 : 0xFFFFFFFF))))
-
-#define CONVERT_SRC1_GCFMT(ocdfmt) \
-	CONVERT_SRC_GCFMT(ocdfmt)
-
-#define CONVERT_SRC2_GCFMT(ocdfmt) \
-	CONVERT_SRC_GCFMT(ocdfmt)
-
-#define db(x) \
-	fprintf(stdout, "%s(%d): %s=(%08ld)\n", __FUNCTION__, __LINE__, #x, (unsigned long)x); \
-	fflush(stdout)
-
-#define dbx(x) \
-	fprintf(stdout, "%s(%d): %s=(0x%08lx)\n", __FUNCTION__, __LINE__, #x, (unsigned long)x); \
-	fflush(stdout)
-
-#define dbs(x) \
-	fprintf(stdout, "%s(%d): %s=(%s)\n", __FUNCTION__, __LINE__, #x, x); \
-	fflush(stdout)
-
-#define BLT _IOW('x', 100, uint32_t)
-#define MAP _IOWR('x', 101, uint32_t)
-#define UMAP _IOW('x', 102, uint32_t)
+/*******************************************************************************
+ * Error handling.
+ */
 
-#define MAX_THRD 1
+#define SETERROR(message) \
+do { \
+	snprintf(gccontext.bverrorstr, sizeof(gccontext.bverrorstr), \
+		"%s(%d): " message, __func__, __LINE__); \
+	GC_PRINT(GC_ERR_MSG " %s\n", __func__, __LINE__, \
+		gccontext.bverrorstr); \
+} while (0)
+
+#define SETERRORARG(message, arg) \
+do { \
+	snprintf(gccontext.bverrorstr, sizeof(gccontext.bverrorstr), \
+		"%s(%d): " message, __func__, __LINE__, arg); \
+	GC_PRINT(GC_ERR_MSG " %s\n", __func__, __LINE__, \
+		gccontext.bverrorstr); \
+} while (0)
+
+#define BVSETERROR(error, message) \
+do { \
+	SETERROR(message); \
+	bverror = error; \
+} while (0)
+
+#define BVSETERRORARG(error, message, arg) \
+do { \
+	SETERRORARG(message, arg); \
+	bverror = error; \
+} while (0)
+
+#define BVSETBLTERROR(error, message) \
+do { \
+	BVSETERROR(error, message); \
+	bltparams->errdesc = gccontext.bverrorstr; \
+} while (0)
+
+#define BVSETBLTERRORARG(error, message, arg) \
+do { \
+	BVSETERRORARG(error, message, arg); \
+	bltparams->errdesc = gccontext.bverrorstr; \
+} while (0)
+
+#define BVSETSURFERROR(errorid, errordesc) \
+do { \
+	snprintf(gccontext.bverrorstr, sizeof(gccontext.bverrorstr), \
+		g_surferr[errorid].message, __func__, __LINE__, errordesc.id); \
+	GC_PRINT(GC_ERR_MSG " %s\n", __func__, __LINE__, \
+		gccontext.bverrorstr); \
+	bverror = errordesc.base + g_surferr[errorid].offset; \
+} while (0)
+
+#define BVSETBLTSURFERROR(errorid, errordesc) \
+do { \
+	BVSETSURFERROR(errorid, errordesc); \
+	bltparams->errdesc = gccontext.bverrorstr; \
+} while (0)
+
+#define BVERR_DESC		0
+#define BVERR_DESC_VERS		1
+#define BVERR_DESC_VIRTADDR	2
+#define BVERR_TILE		3
+#define BVERR_TILE_VERS		4
+#define BVERR_TILE_VIRTADDR	5
+#define BVERR_GEOM		6
+#define BVERR_GEOM_VERS		7
+#define BVERR_GEOM_FORMAT	8
+
+struct bvsurferrorid {
+	char *id;
+	enum bverror base;
+};
 
-struct blt {
-	uint32_t *cmdbuf;
-	uint32_t cmdlen;
-	uint32_t offset[128];
-	uint32_t linkindex[128];
-	uint32_t linkvalue[128];
+struct bvsurferror {
+	unsigned int offset;
+	char *message;
 };
 
-struct bv_alpha {
-	/*
-		The blending formulas used are as follows:
-		outR = srcR * srcRFactor + dstR * dstRFactor
-		outG = srcG * srcGFactor + dstG * dstGFactor
-		outB = srcB * srcBFactor + dstB * dstBFactor
-		outA = srcA * srcAFactor + dstA * dstAFactor
-	*/
+static struct bvsurferror g_surferr[] = {
+	/* BVERR_DESC */
+	{    0, "%s(%d): %s desc structure is not set" },
 
-	/*
-		Global color values.
-	*/
-	unsigned int src_global_color;
-	unsigned int dst_global_color;
+	/* BVERR_DESC_VERS */
+	{  100, "%s(%d): %s desc structure has invalid size" },
 
-	/*
-		NORMAL:
-			pick straight alpha value;
-		INVERSED:
-			get the inverse of alpha value.
-	*/
-	unsigned char src_inverse_alpha;
-	unsigned char dst_inverse_alpha;
+	/* BVERR_DESC_VIRTADDR */
+	{  200, "%s(%d): %s desc virtual pointer is not set" },
 
-	/*
-		NORMAL:
-			pick the pixel (local) alpha value;
-		GLOBAL:
-			pick the global alpha value;
-		SCALED:
-			use the multiplication product of local and
-			global alphas.
-	*/
-	unsigned char src_global_alpha_mode;
-	unsigned char dst_global_alpha_mode;
+	/* BVERR_TILE: FIXME/TODO define error code */
+	{    0, "%s(%d): %s tileparams structure is not set" },
 
-	/*
-		ZERO:
-			R/G/B/A blending factors = 0;
-		ONE:
-			R/G/B/A blending factors = 1;
-		NORMAL:
-			R/G/B/A blending factors are the alpha value determined
-			above;
-		INVERSED:
-			R/G/B/A blending factors are the inversed alpha value
-			determined above;
-		COLOR:
-			R/G/B blending factors is the color of the pixel;
-			A blending factor is the alpha value determined above;
-		COLOR_INVERSED:
-			R/G/B blending factors is the inversed color
-			of the pixel;
-			A blending factor is the inversed alpha value
-			determined above;
-		SATURATED_ALPHA:
-			Factors are set as follows (source mode pseudo code):
-			srcFactorA = 1.0
-			srcFactorR = srcFactorG = srcFactorB =
-				(srcAlpha < (1.0 - dstAlpha))
-					? srcAlpha
-					: (1.0 - dstAlpha)
-			Note:
-			1. srcAlpha and dstAlpha are the determined
-			   alpha values of source and destination
-			   pixels.
-			2. Similar formula is used for the destination
-			   factos.
-		SATURATED_DEST_ALPHA:
-			Same as above with the exception of alpha values
-			reversed (source vs. destination).
-	*/
-	unsigned char src_factor_mode;
-	unsigned char dst_factor_mode;
+	/* BVERR_TILE_VERS */
+	{ 3000, "%s(%d): %s tileparams structure has invalid size" },
 
-	/*
-		DISABLED:
-			Source factors are based off of the destination pixel;
-			Destination factors are based off of the source pixel;
-		ENABLED:
-			Source factors are based off of the source pixel;
-			Destination factors are based off of the destination
-			pixel;
-	*/
-	unsigned char src_alpha_factor;
-	unsigned char dst_alpha_factor;
+	/* BVERR_TILE_VIRTADDR: FIXME/TODO define error code */
+	{  200, "%s(%d): %s tileparams virtual pointer is not set" },
 
-	/*
-		DISABLED:
-			Premultiplication is disabled.
-		ENABLED:
-			Premultipy the color by its own alpha value
-			(alpha value stays the same).
-	*/
-	unsigned char src_premul_src_alpha;
-	unsigned char dst_premul_dst_alpha;
+	/* BVERR_GEOM */
+	{ 1000, "%s(%d): %s geom structure is not set" },
 
-	/*
-		DISABLE:
-			Premultiplication is disabled.
-		ALPHA:
-			Premultipy the color by the global source alpha value
-			(alpha value stays the same).
-		COLOR:
-			Premultipy the color by the global source color values
-			(alpha value stays the same).
-	*/
-	unsigned char src_premul_global_mode;
+	/* BVERR_GEOM_VERS */
+	{ 1100, "%s(%d): %s geom structure has invalid size" },
 
-	/*
-		DISABLED:
-			Division is disabled.
-		ENABLED:
-			Divide blended color by its own alpha value
-			(alpha value stays the same).
-	*/
-	unsigned char dst_demul_dst_alpha;
+	/* BVERR_GEOM_FORMAT */
+	{ 1200, "%s(%d): %s invalid format specified" },
 };
 
-static const char *file = "/dev/gc-core";
-static int fd;
-static pthread_t id[MAX_THRD];
+static struct bvsurferrorid g_destsurferr = { "dst",  BVERR_DSTDESC };
+static struct bvsurferrorid g_src1surferr = { "src1", BVERR_SRC1DESC };
+static struct bvsurferrorid g_src2surferr = { "src2", BVERR_SRC2DESC };
+static struct bvsurferrorid g_masksurferr = { "mask", BVERR_MASKDESC };
 
-extern void bv_init(void) __attribute__((constructor));
-extern void bv_exit(void) __attribute__((destructor));
+/*******************************************************************************
+ * Threads etc... TBD
+ */
+
+#if 0
+#define MAX_THRD 1
+static pthread_t id[MAX_THRD];
 
 /* TODO: check that we aren't using more logic than we need */
 static void sig_handler(int sig)
 {
-	fprintf(stdout, "%s::%d:%lx:%d\n", __FUNCTION__, __LINE__,
-		(unsigned long)pthread_self(), sig);
-	fflush(stdout);
+	GC_PRINT(GC_INFO_MSG " %s(%d): %lx:%d\n", __func__, __LINE__,
+		(unsigned long) pthread_self(), sig);
 	sleep(2); sched_yield();
 }
 
 /* TODO: check that we aren't using more logic than we need */
-static void * thread(void *p)
+static void *thread(void *p)
 {
 	int r = 0;
 	sigset_t set;
@@ -282,120 +447,849 @@ static void * thread(void *p)
 	sigaction(SIGUSR1, &sa, NULL);
 
 	while (1) {
-		fprintf(stdout, "%s::%d\n", __FUNCTION__, __LINE__); fflush(stdout);
+		GC_PRINT(GC_INFO_MSG " %s(%d)\n", __func__, __LINE__);
 		sigwait(&set, &r);
-		fprintf(stdout, "%s::%d\n", __FUNCTION__, __LINE__); fflush(stdout);
+		GC_PRINT(GC_INFO_MSG " %s(%d)\n", __func__, __LINE__);
 	}
+
 	return NULL;
 }
+#endif
 
-extern void bv_init(void)
+/*******************************************************************************
+ * Memory management.
+ */
+
+static enum bverror do_map(struct bvbuffdesc *buffdesc, int client,
+				struct bvbuffmap **map)
 {
-	int32_t res, i;
+	static const int mapsize
+		= sizeof(struct bvbuffmap)
+		+ sizeof(struct bvbuffmapinfo);
+
+	enum bverror bverror;
+	struct bvbuffmap *bvbuffmap;
+	struct bvbuffmapinfo *bvbuffmapinfo;
+	struct gcmap gcmap;
+	void *logical;
+	unsigned int offset;
+
+	/* Try to find existing mapping. */
+	bvbuffmap = buffdesc->map;
+	while (bvbuffmap != NULL) {
+		if (bvbuffmap->bv_unmap == bv_unmap)
+			break;
+		bvbuffmap = bvbuffmap->nextmap;
+	}
 
-	fd = open(file, O_RDWR);
-	if (fd == -1) {
-		fprintf(stderr, "%s(%d): failed to open device (%d)\n",
-			__FUNCTION__, __LINE__, errno);
-		fflush(stderr);
-		goto exit;
+	/* Already mapped? */
+	if (bvbuffmap != NULL) {
+		bvbuffmapinfo = (struct bvbuffmapinfo *) bvbuffmap->handle;
+
+		if (client)
+			bvbuffmapinfo->usermap += 1;
+		else
+			bvbuffmapinfo->automap += 1;
+
+		*map = bvbuffmap;
+		return BVERR_NONE;
 	}
 
-	for (i = 0; i < MAX_THRD; i++) {
-		res = pthread_create(&id[i], NULL, thread, NULL);
-		if(res != 0) {
-			fprintf(stderr, "%s(%d): failed to start a thread (%d)\n",
-				__FUNCTION__, __LINE__, res);
-			fflush(stderr);
+	/* New mapping, allocate a record. */
+	if (gccontext.vac_buffmap == NULL) {
+		bvbuffmap = gcalloc(struct bvbuffmap, mapsize);
+		if (bvbuffmap == NULL) {
+			BVSETERROR(BVERR_OOM,
+					"failed to allocate mapping record");
 			goto exit;
 		}
+
+		bvbuffmap->structsize = sizeof(struct bvbuffmap);
+		bvbuffmap->bv_unmap = bv_unmap;
+		bvbuffmap->handle = (unsigned long) (bvbuffmap + 1);
+	} else {
+		bvbuffmap = gccontext.vac_buffmap;
+		gccontext.vac_buffmap = bvbuffmap->nextmap;
+	}
+
+	/* Align the base address as required by 2D hardware. */
+	logical = (void *) ((unsigned int) buffdesc->virtaddr
+		& ~(GC_BASE_ALIGN - 1));
+	offset = (unsigned int) buffdesc->virtaddr
+		& (GC_BASE_ALIGN - 1);
+
+	/* Map the buffer. */
+	gcmap.gcerror = GCERR_NONE;
+	gcmap.logical = logical;
+	gcmap.size = buffdesc->length + offset;
+	gcmap.handle = 0;
+
+	gc_map_wrapper(&gcmap);
+	if (gcmap.gcerror != GCERR_NONE) {
+		BVSETERRORARG(BVERR_UNK, "mapping error occured (0x%08X)",
+					 gcmap.gcerror);
+		goto exit;
+	}
+
+	bvbuffmapinfo = (struct bvbuffmapinfo *) bvbuffmap->handle;
+
+	bvbuffmapinfo->handle = gcmap.handle;
+
+	if (client) {
+		bvbuffmapinfo->usermap = 1;
+		bvbuffmapinfo->automap = 0;
+	} else {
+		bvbuffmapinfo->usermap = 0;
+		bvbuffmapinfo->automap = 1;
+	}
+
+	bvbuffmap->nextmap = buffdesc->map;
+	buffdesc->map = bvbuffmap;
+
+	*map = bvbuffmap;
+	return BVERR_NONE;
+
+exit:
+	if (bvbuffmap != NULL) {
+		bvbuffmap->nextmap = gccontext.vac_buffmap;
+		gccontext.vac_buffmap = bvbuffmap;
 	}
 
-exit:;
+	return bverror;
 }
 
-extern void bv_exit(void)
+static enum bverror do_unmap(struct bvbuffdesc *buffdesc, int client)
 {
-	int32_t res, i;
+	enum bverror bverror;
+	struct bvbuffmap *prev = NULL;
+	struct bvbuffmap *bvbuffmap;
+	struct bvbuffmapinfo *bvbuffmapinfo;
+	struct gcmap gcmap;
+
+	/* Try to find existing mapping. */
+	bvbuffmap = buffdesc->map;
+	while (bvbuffmap != NULL) {
+		if (bvbuffmap->bv_unmap == bv_unmap)
+			break;
+		prev = bvbuffmap;
+		bvbuffmap = bvbuffmap->nextmap;
+	}
 
-	for (i = 0; i < MAX_THRD; i++) {
-		if (id[i] != 0) {
-			res = pthread_cancel(id[i]);
-			if (res == 0) {
-				id[i] = 0;
-			} else {
-				fprintf(stderr, "%s(%d): failed to cancel a thread (%d)\n",
-					__FUNCTION__, __LINE__, res);
-				fflush(stderr);
-			}
+	/* No mapping found? */
+	if (bvbuffmap == NULL) {
+		bverror = BVERR_NONE;
+		goto exit;
+	}
+
+	/* Get the info structure. */
+	bvbuffmapinfo = (struct bvbuffmapinfo *) bvbuffmap->handle;
+
+	/* Dereference. */
+	if (client)
+		bvbuffmapinfo->usermap = 0;
+	else
+		bvbuffmapinfo->automap -= 1;
+
+	/* Still referenced? */
+	if (bvbuffmapinfo->usermap || bvbuffmapinfo->automap) {
+		bverror = BVERR_NONE;
+		goto exit;
+	}
+
+	/* Setup buffer unmapping. */
+	gcmap.gcerror = GCERR_NONE;
+	gcmap.logical = buffdesc->virtaddr;
+	gcmap.size = buffdesc->length;
+	gcmap.handle = GET_MAP_HANDLE(bvbuffmap);
+
+	/* Remove mapping record. */
+	if (prev == NULL)
+		buffdesc->map = bvbuffmap->nextmap;
+	else
+		prev->nextmap = bvbuffmap->nextmap;
+
+	bvbuffmap->nextmap = gccontext.vac_buffmap;
+	gccontext.vac_buffmap = bvbuffmap;
+
+	/* Unmap the buffer. */
+	gc_unmap_wrapper(&gcmap);
+	if (gcmap.gcerror != GCERR_NONE) {
+		BVSETERRORARG(BVERR_UNK, "unmapping error occured (0x%08X)",
+					 gcmap.gcerror);
+		goto exit;
+	}
+
+	bverror = BVERR_NONE;
+
+exit:
+	return bverror;
+}
+
+static enum bverror schedule_unmap(struct gcbatch *batch,
+					struct bvbuffdesc *buffdesc)
+{
+	enum bverror bverror;
+	struct gcschedunmap *gcschedunmap;
+
+	if (gccontext.vac_unmap == NULL) {
+		gcschedunmap = gcalloc(struct gcschedunmap,
+					sizeof(struct gcschedunmap));
+		if (gcschedunmap == NULL) {
+			BVSETERROR(BVERR_OOM, "failed to schedule unmapping");
+			goto exit;
 		}
+	} else {
+		gcschedunmap = gccontext.vac_unmap;
+		gccontext.vac_unmap = gcschedunmap->next;
 	}
 
-	if (fd != 0) {
-		close(fd);
-		fd = 0;
+	gcschedunmap->bvbuffdesc = buffdesc;
+	gcschedunmap->next = batch->unmap;
+	batch->unmap = gcschedunmap;
+
+	bverror = BVERR_NONE;
+
+exit:
+	return bverror;
+}
+
+static enum bverror process_scheduled_unmap(struct gcbatch *batch)
+{
+	enum bverror bverror = BVERR_NONE;
+	struct gcschedunmap *gcschedunmap;
+
+	while (batch->unmap != NULL) {
+		gcschedunmap = batch->unmap;
+
+		bverror = do_unmap(gcschedunmap->bvbuffdesc, 0);
+		if (bverror != BVERR_NONE)
+			break;
+
+		batch->unmap = gcschedunmap->next;
+		gcschedunmap->next = gccontext.vac_unmap;
+		gccontext.vac_unmap = gcschedunmap;
 	}
+
+	return bverror;
 }
 
-enum bverror bv_map(struct bvbuffdesc *buffdesc)
+/*******************************************************************************
+ * Batch memory manager.
+ */
+
+static enum bverror allocate_batch(struct gcbatch **batch);
+static void free_batch(struct gcbatch *batch);
+static enum bverror append_buffer(struct gcbatch *batch);
+
+static enum bverror do_end(struct bvbltparams *bltparams,
+				struct gcbatch *batch)
 {
-	int32_t res;
+	GC_PRINT(GC_INFO_MSG " dummy operation end\n", __func__, __LINE__);
+	return BVERR_NONE;
+}
 
-	if (!buffdesc) {
-		fprintf(stderr, "%s(%d): invalid argument\n", __FUNCTION__, __LINE__);
-		fflush(stderr);
-		res = BVERR_UNK;
-		goto exit;
+static enum bverror allocate_batch(struct gcbatch **batch)
+{
+	enum bverror bverror;
+	struct gcbatch *temp;
+
+	if (gccontext.vac_batches == NULL) {
+		temp = gcalloc(struct gcbatch, sizeof(struct gcbatch));
+		if (temp == NULL) {
+			BVSETERROR(BVERR_OOM,
+					"batch header allocation failed");
+			goto exit;
+		}
+	} else {
+		temp = (struct gcbatch *) gccontext.vac_batches;
+		gccontext.vac_batches = gccontext.vac_batches->next;
 	}
 
-	if (sizeof(*buffdesc) != sizeof(struct bvbuffdesc)) {
-		fprintf(stderr, "%s(%d): invalid argument\n", __FUNCTION__, __LINE__);
-		fflush(stderr);
-		res = BVERR_BUFFERDESC_VERS;
+	memset(temp, 0, sizeof(struct gcbatch));
+	temp->structsize = sizeof(struct gcbatch);
+	temp->batchend = do_end;
+
+	bverror = append_buffer(temp);
+	if (bverror != BVERR_NONE) {
+		free_batch(temp);
 		goto exit;
 	}
 
-	res = ioctl(fd, MAP, buffdesc);
-	if ((res == -1) || (buffdesc->map == NULL)) {
-		fprintf(stderr, "%s(%d): mapping failed\n", __FUNCTION__, __LINE__);
-		fflush(stderr);
-		res = BVERR_UNK;
-		goto exit;
+	*batch = temp;
+
+exit:
+	return bverror;
+}
+
+static void free_batch(struct gcbatch *batch)
+{
+	struct gcbuffer *buffer;
+
+	buffer = batch->bufhead;
+	if (buffer != NULL) {
+		do {
+			if (buffer->fixuphead != NULL) {
+				buffer->fixuptail->next = gccontext.vac_fixups;
+				gccontext.vac_fixups = buffer->fixuphead;
+			}
+			buffer = buffer->next;
+		} while (buffer != NULL);
+
+		batch->buftail->next = gccontext.vac_buffers;
+		gccontext.vac_buffers = batch->bufhead;
+	}
+
+	((struct gcvacbatch *) batch)->next = gccontext.vac_batches;
+	gccontext.vac_batches = (struct gcvacbatch *) batch;
+}
+
+static enum bverror append_buffer(struct gcbatch *batch)
+{
+	enum bverror bverror;
+	struct gcbuffer *temp;
+
+	GC_PRINT(GC_INFO_MSG " batch = 0x%08X\n",
+		__func__, __LINE__, (unsigned int) batch);
+
+	if (gccontext.vac_buffers == NULL) {
+		temp = gcalloc(struct gcbuffer, GC_BUFFER_SIZE);
+		if (temp == NULL) {
+			BVSETERROR(BVERR_OOM,
+					"command buffer allocation failed");
+			goto exit;
+		}
+	} else {
+		temp = gccontext.vac_buffers;
+		gccontext.vac_buffers = temp->next;
 	}
 
-	res = BVERR_NONE;
+	memset(temp, 0, sizeof(struct gcbuffer));
+	temp->head =
+	temp->tail = (unsigned int *) (temp + 1);
+	temp->available = GC_BUFFER_SIZE - sizeof(struct gcbuffer);
+
+	if (batch->bufhead == NULL)
+		batch->bufhead = temp;
+	else
+		batch->buftail->next = temp;
+	batch->buftail = temp;
+
+	GC_PRINT(GC_INFO_MSG " new buffer appended = 0x%08X\n",
+		__func__, __LINE__, (unsigned int) temp);
+
+	bverror = BVERR_NONE;
 
 exit:
-	return res;
+	return bverror;
 }
 
-struct bvblendxlate {
-	uint8_t match1;
-	uint8_t match2;
+static enum bverror add_fixup(struct gcbatch *batch, unsigned int *fixup,
+				unsigned int surfoffset)
+{
+	enum bverror bverror;
+	struct gcbuffer *buffer;
+	struct gcfixup *temp;
+
+	GC_PRINT(GC_INFO_MSG " batch = 0x%08X, fixup ptr = 0x%08X\n",
+		__func__, __LINE__, (unsigned int) batch, (unsigned int) fixup);
+
+	buffer = batch->buftail;
+	temp = buffer->fixuptail;
+
+	GC_PRINT(GC_INFO_MSG " buffer = 0x%08X, fixup struct = 0x%08X\n",
+		__func__, __LINE__, (unsigned int) buffer, (unsigned int) temp);
+
+	if ((temp == NULL) || (temp->count == GC_FIXUP_MAX)) {
+		if (gccontext.vac_fixups == NULL) {
+			temp = gcalloc(struct gcfixup, sizeof(struct gcfixup));
+			if (temp == NULL) {
+				BVSETERROR(BVERR_OOM,
+						"fixup allocation failed");
+				goto exit;
+			}
+		} else {
+			temp = gccontext.vac_fixups;
+			gccontext.vac_fixups = temp->next;
+		}
 
-	uint8_t dst_factor_mode;
-	uint8_t dst_alpha_factor;
+		temp->next = NULL;
+		temp->count = 0;
 
-	uint8_t src_factor_mode;
-	uint8_t src_alpha_factor;
+		if (buffer->fixuphead == NULL)
+			buffer->fixuphead = temp;
+		else
+			buffer->fixuptail->next = temp;
+		buffer->fixuptail = temp;
+
+		GC_PRINT(GC_INFO_MSG " new fixup struct allocated = 0x%08X\n",
+			__func__, __LINE__, (unsigned int) temp);
+
+	} else {
+		GC_PRINT(GC_INFO_MSG " fixups accumulated = %d\n",
+			__func__, __LINE__, temp->count);
+	}
+
+	temp->fixup[temp->count].dataoffset = fixup - buffer->head;
+	temp->fixup[temp->count].surfoffset = surfoffset;
+	temp->count += 1;
+
+	GC_PRINT(GC_INFO_MSG " fixup offset = 0x%08X\n",
+		__func__, __LINE__, fixup - buffer->head);
+	GC_PRINT(GC_INFO_MSG " surface offset = 0x%08X\n",
+		__func__, __LINE__, surfoffset);
+
+	bverror = BVERR_NONE;
+
+exit:
+	return bverror;
+}
+
+static enum bverror claim_buffer(struct gcbatch *batch,
+					unsigned int size,
+					void **buffer)
+{
+	enum bverror bverror;
+	struct gcbuffer *curbuf;
+
+	/* Get the current command buffer. */
+	curbuf = batch->buftail;
+
+	GC_PRINT(GC_INFO_MSG " batch = 0x%08X, buffer = 0x%08X\n",
+		__func__, __LINE__,
+		(unsigned int) batch, (unsigned int) curbuf);
+
+	GC_PRINT(GC_INFO_MSG " available = %d, requested = %d\n",
+		__func__, __LINE__, curbuf->available, size);
+
+	if (curbuf->available < size) {
+		bverror = append_buffer(batch);
+		if (bverror != BVERR_NONE)
+			goto exit;
+
+		curbuf = batch->buftail;
+	}
+
+	*buffer = curbuf->tail;
+	curbuf->tail = (unsigned int *) ((unsigned char *) curbuf->tail + size);
+	curbuf->available -= size;
+	batch->size += size;
+	bverror = BVERR_NONE;
+
+exit:
+	return bverror;
+}
+
+/*******************************************************************************
+ * Pixel format parser.
+ */
+
+/* FIXME/TODO: change to use BLTsvile defines. */
+
+#if defined(OCDFMTDEF_ALPHA_SHIFT)
+#	undef OCDFMTDEF_ALPHA_SHIFT
+#endif
+
+#if defined(OCDFMTDEF_ALPHA_MASK)
+#	undef OCDFMTDEF_ALPHA_MASK
+#endif
+
+#define OCDFMTDEF_ALPHA_SHIFT 18
+#define OCDFMTDEF_ALPHA_MASK (1 << OCDFMTDEF_ALPHA_SHIFT)
+
+#define OCDFMTDEF_PLACEMENT_SHIFT 9
+#define OCDFMTDEF_PLACEMENT_MASK (3 << OCDFMTDEF_PLACEMENT_SHIFT)
+
+#define OCDFMTDEF_BITS_SHIFT 3
+#define OCDFMTDEF_BITS_MASK (3 << OCDFMTDEF_BITS_SHIFT)
+
+#define OCDFMTDEF_BITS12 (0 << OCDFMTDEF_BITS_SHIFT)
+#define OCDFMTDEF_BITS15 (1 << OCDFMTDEF_BITS_SHIFT)
+#define OCDFMTDEF_BITS16 (2 << OCDFMTDEF_BITS_SHIFT)
+#define OCDFMTDEF_BITS24 (3 << OCDFMTDEF_BITS_SHIFT)
+
+struct bvcomponent {
+	unsigned int shift;
+	unsigned int size;
+	unsigned int mask;
 };
 
+struct bvcsrgb {
+	struct bvcomponent r;
+	struct bvcomponent g;
+	struct bvcomponent b;
+	struct bvcomponent a;
+};
 
-/***********************************************
-** Color factor is an alpha variant.
-*/
+struct bvformatxlate {
+	unsigned bitspp;
+	unsigned format;
+	unsigned swizzle;
+	struct bvcsrgb rgba;
+};
+
+#define BVFORMATRGBA(BPP, Format, Swizzle, R, G, B, A) \
+{ \
+	BPP, \
+	GCREG_DE_FORMAT_ ## Format, \
+	GCREG_DE_SWIZZLE_ ## Swizzle, \
+	{ R, G, B, A } \
+}
+
+#define BVCOMP(Shift, Size) \
+	{ Shift, Size, ((1 << Size) - 1) << Shift }
+
+#define BVRED(Shift, Size) \
+	BVCOMP(Shift, Size)
+
+#define BVGREEN(Shift, Size) \
+	BVCOMP(Shift, Size)
+
+#define BVBLUE(Shift, Size) \
+	BVCOMP(Shift, Size)
+
+#define BVALPHA(Shift, Size) \
+	BVCOMP(Shift, Size)
+
+#define BVFORMATINVALID \
+	{ 0, 0, 0, { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 } } }
+
+static struct bvformatxlate formatxlate[] = {
+	/* BITS=12 ALPHA=0 REVERSED=0 LEFT_JUSTIFIED=0 */
+	BVFORMATRGBA(16, X4R4G4B4, RGBA,
+		BVRED(12, 4), BVGREEN(8, 4), BVBLUE(4, 4), BVALPHA(0, 0)),
+
+	/* BITS=12 ALPHA=0 REVERSED=0 LEFT_JUSTIFIED=1 */
+	BVFORMATRGBA(16, X4R4G4B4, ARGB,
+		BVRED(8, 4), BVGREEN(4, 4), BVBLUE(0, 4), BVALPHA(12, 0)),
+
+	/* BITS=12 ALPHA=0 REVERSED=1 LEFT_JUSTIFIED=0 */
+	BVFORMATRGBA(16, X4R4G4B4, BGRA,
+		BVRED(4, 4), BVGREEN(8, 4), BVBLUE(12, 4), BVALPHA(0, 0)),
+
+	/* BITS=12 ALPHA=0 REVERSED=1 LEFT_JUSTIFIED=1 */
+	BVFORMATRGBA(16, X4R4G4B4, ABGR,
+		BVRED(0, 4), BVGREEN(4, 4), BVBLUE(8, 4), BVALPHA(12, 0)),
+
+	/* BITS=12 ALPHA=1 REVERSED=0 LEFT_JUSTIFIED=0 */
+	BVFORMATRGBA(16, A4R4G4B4, RGBA,
+		BVRED(12, 4), BVGREEN(8, 4), BVBLUE(4, 4), BVALPHA(0, 4)),
+
+	/* BITS=12 ALPHA=1 REVERSED=0 LEFT_JUSTIFIED=1 */
+	BVFORMATRGBA(16, A4R4G4B4, ARGB,
+		BVRED(8, 4), BVGREEN(4, 4), BVBLUE(0, 4), BVALPHA(12, 4)),
+
+	/* BITS=12 ALPHA=1 REVERSED=1 LEFT_JUSTIFIED=0 */
+	BVFORMATRGBA(16, A4R4G4B4, BGRA,
+		BVRED(4, 4), BVGREEN(8, 4), BVBLUE(12, 4), BVALPHA(0, 4)),
+
+	/* BITS=12 ALPHA=1 REVERSED=1 LEFT_JUSTIFIED=1 */
+	BVFORMATRGBA(16, A4R4G4B4, ABGR,
+		BVRED(0, 4), BVGREEN(4, 4), BVBLUE(8, 4), BVALPHA(12, 4)),
+
+	/***********************************************/
+
+	/* BITS=15 ALPHA=0 REVERSED=0 LEFT_JUSTIFIED=0 */
+	BVFORMATRGBA(16, X1R5G5B5, RGBA,
+		BVRED(11, 5), BVGREEN(6, 5), BVBLUE(1, 5), BVALPHA(0, 0)),
+
+	/* BITS=15 ALPHA=0 REVERSED=0 LEFT_JUSTIFIED=1 */
+	BVFORMATRGBA(16, X1R5G5B5, ARGB,
+		BVRED(10, 5), BVGREEN(5, 5), BVBLUE(0, 5), BVALPHA(15, 0)),
+
+	/* BITS=15 ALPHA=0 REVERSED=1 LEFT_JUSTIFIED=0 */
+	BVFORMATRGBA(16, X1R5G5B5, BGRA,
+		BVRED(1, 5), BVGREEN(6, 5), BVBLUE(11, 5), BVALPHA(0, 0)),
+
+	/* BITS=15 ALPHA=0 REVERSED=1 LEFT_JUSTIFIED=1 */
+	BVFORMATRGBA(16, X1R5G5B5, ABGR,
+		BVRED(0, 5), BVGREEN(5, 5), BVBLUE(10, 5), BVALPHA(15, 0)),
+
+	/* BITS=15 ALPHA=1 REVERSED=0 LEFT_JUSTIFIED=0 */
+	BVFORMATRGBA(16, A1R5G5B5, RGBA,
+		BVRED(11, 5), BVGREEN(6, 5), BVBLUE(1, 5), BVALPHA(0, 1)),
+
+	/* BITS=15 ALPHA=1 REVERSED=0 LEFT_JUSTIFIED=1 */
+	BVFORMATRGBA(16, A1R5G5B5, ARGB,
+		BVRED(10, 5), BVGREEN(5, 5), BVBLUE(0, 5), BVALPHA(15, 1)),
+
+	/* BITS=15 ALPHA=1 REVERSED=1 LEFT_JUSTIFIED=0 */
+	BVFORMATRGBA(16, A1R5G5B5, BGRA,
+		BVRED(1, 5), BVGREEN(6, 5), BVBLUE(11, 5), BVALPHA(0, 1)),
+
+	/* BITS=15 ALPHA=1 REVERSED=1 LEFT_JUSTIFIED=1 */
+	BVFORMATRGBA(16, A1R5G5B5, ABGR,
+		BVRED(0, 5), BVGREEN(5, 5), BVBLUE(10, 5), BVALPHA(15, 1)),
+
+	/***********************************************/
+
+	/* BITS=16 ALPHA=0 REVERSED=0 LEFT_JUSTIFIED=0 */
+	BVFORMATRGBA(16, R5G6B5, ARGB,
+		BVRED(11, 5), BVGREEN(5, 6), BVBLUE(0, 5), BVALPHA(0, 0)),
+
+	/* BITS=16 ALPHA=0 REVERSED=0 LEFT_JUSTIFIED=1 */
+	BVFORMATRGBA(16, R5G6B5, ARGB,
+		BVRED(11, 5), BVGREEN(5, 6), BVBLUE(0, 5), BVALPHA(0, 0)),
+
+	/* BITS=16 ALPHA=0 REVERSED=1 LEFT_JUSTIFIED=0 */
+	BVFORMATRGBA(16, R5G6B5, ABGR,
+		BVRED(0, 5), BVGREEN(5, 6), BVBLUE(11, 5), BVALPHA(0, 0)),
+
+	/* BITS=16 ALPHA=0 REVERSED=1 LEFT_JUSTIFIED=1 */
+	BVFORMATRGBA(16, R5G6B5, ABGR,
+		BVRED(0, 5), BVGREEN(5, 6), BVBLUE(11, 5), BVALPHA(0, 0)),
+
+	/* BITS=16 ALPHA=1 REVERSED=0 LEFT_JUSTIFIED=0 */
+	BVFORMATINVALID,
+
+	/* BITS=16 ALPHA=1 REVERSED=0 LEFT_JUSTIFIED=1 */
+	BVFORMATINVALID,
+
+	/* BITS=16 ALPHA=1 REVERSED=1 LEFT_JUSTIFIED=0 */
+	BVFORMATINVALID,
+
+	/* BITS=16 ALPHA=1 REVERSED=1 LEFT_JUSTIFIED=1 */
+	BVFORMATINVALID,
+
+	/***********************************************/
+
+	/* BITS=24 ALPHA=0 REVERSED=0 LEFT_JUSTIFIED=0 */
+	BVFORMATRGBA(32, X8R8G8B8, RGBA,
+		BVRED(24, 8), BVGREEN(16, 8), BVBLUE(8, 8), BVALPHA(0, 0)),
+
+	/* BITS=24 ALPHA=0 REVERSED=0 LEFT_JUSTIFIED=1 */
+	BVFORMATRGBA(32, X8R8G8B8, ARGB,
+		BVRED(16, 8), BVGREEN(8, 8), BVBLUE(0, 8), BVALPHA(0, 0)),
+
+	/* BITS=24 ALPHA=0 REVERSED=1 LEFT_JUSTIFIED=0 */
+	BVFORMATRGBA(32, X8R8G8B8, BGRA,
+		BVRED(8, 8), BVGREEN(16, 8), BVBLUE(24, 8), BVALPHA(0, 0)),
+
+	/* BITS=24 ALPHA=0 REVERSED=1 LEFT_JUSTIFIED=1 */
+	BVFORMATRGBA(32, X8R8G8B8, ABGR,
+		BVRED(0, 8), BVGREEN(8, 8), BVBLUE(16, 8), BVALPHA(0, 0)),
+
+	/* BITS=24 ALPHA=1 REVERSED=0 LEFT_JUSTIFIED=0 */
+	BVFORMATRGBA(32, A8R8G8B8, RGBA,
+		BVRED(24, 8), BVGREEN(16, 8), BVBLUE(8, 8), BVALPHA(0, 8)),
+
+	/* BITS=24 ALPHA=1 REVERSED=0 LEFT_JUSTIFIED=1 */
+	BVFORMATRGBA(32, A8R8G8B8, ARGB,
+		BVRED(16, 8), BVGREEN(8, 8), BVBLUE(0, 8), BVALPHA(24, 8)),
+
+	/* BITS=24 ALPHA=1 REVERSED=1 LEFT_JUSTIFIED=0 */
+	BVFORMATRGBA(32, A8R8G8B8, BGRA,
+		BVRED(8, 8), BVGREEN(16, 8), BVBLUE(24, 8), BVALPHA(0, 8)),
+
+	/* BITS=24 ALPHA=1 REVERSED=1 LEFT_JUSTIFIED=1 */
+	BVFORMATRGBA(32, A8R8G8B8, ABGR,
+		BVRED(0, 8), BVGREEN(8, 8), BVBLUE(16, 8), BVALPHA(24, 0)),
+};
+
+static int parse_format(enum ocdformat ocdformat, struct bvformatxlate **format)
+{
+	static unsigned int containers[] = {
+		  8,	/* OCDFMTDEF_CONTAINER_8BIT */
+		 16,	/* OCDFMTDEF_CONTAINER_16BIT */
+		 24,	/* OCDFMTDEF_CONTAINER_24BIT */
+		 32,	/* OCDFMTDEF_CONTAINER_32BIT */
+		~0U,	/* reserved */
+		 48,	/* OCDFMTDEF_CONTAINER_48BIT */
+		~0U,	/* reserved */
+		 64	/* OCDFMTDEF_CONTAINER_64BIT */
+	};
+
+	unsigned int cs;
+	unsigned int bits;
+	unsigned int swizzle;
+	unsigned int alpha;
+	unsigned int index;
+	unsigned int cont;
+
+	GC_PRINT(GC_INFO_MSG " ocdformat = 0x%08X\n",
+		__func__, __LINE__, ocdformat);
+
+	cs = (ocdformat & OCDFMTDEF_CS_MASK) >> OCDFMTDEF_CS_SHIFT;
+	bits = (ocdformat & OCDFMTDEF_COMPONENTSIZEMINUS1_MASK)
+		>> OCDFMTDEF_COMPONENTSIZEMINUS1_SHIFT;
+	cont = (ocdformat & OCDFMTDEF_CONTAINER_MASK)
+		>> OCDFMTDEF_CONTAINER_SHIFT;
+
+	switch (cs) {
+	case (OCDFMTDEF_CS_RGB >> OCDFMTDEF_CS_SHIFT):
+		GC_PRINT(GC_INFO_MSG " OCDFMTDEF_CS_RGB\n",
+			__func__, __LINE__);
+
+		GC_PRINT(GC_INFO_MSG " bits = %d\n",
+			__func__, __LINE__, bits);
+
+		GC_PRINT(GC_INFO_MSG " cont = %d\n",
+			__func__, __LINE__, cont);
+
+		if ((ocdformat & OCDFMTDEF_LAYOUT_MASK) != OCDFMTDEF_PACKED)
+			return 0;
+
+		swizzle = (ocdformat & OCDFMTDEF_PLACEMENT_MASK)
+			>> OCDFMTDEF_PLACEMENT_SHIFT;
+		alpha = (ocdformat & OCDFMTDEF_ALPHA_MASK)
+			>> OCDFMTDEF_ALPHA_SHIFT;
+
+		GC_PRINT(GC_INFO_MSG " swizzle = %d\n",
+			__func__, __LINE__, swizzle);
+
+		GC_PRINT(GC_INFO_MSG " alpha = %d\n",
+			__func__, __LINE__, alpha);
+
+		index = swizzle | (alpha << 2);
+
+		switch (bits) {
+		case 12 - 1:
+			index |= OCDFMTDEF_BITS12;
+			break;
+
+		case 15 - 1:
+			index |= OCDFMTDEF_BITS15;
+			break;
+
+		case 16 - 1:
+			index |= OCDFMTDEF_BITS16;
+			break;
+
+		case 24 - 1:
+			index |= OCDFMTDEF_BITS24;
+			break;
+
+		default:
+			return 0;
+		}
+
+		GC_PRINT(GC_INFO_MSG " index = %d\n",
+			__func__, __LINE__, index);
+
+		break;
+
+	default:
+		return 0;
+	}
+
+	if (formatxlate[index].bitspp != containers[cont])
+		return 0;
+
+	*format = &formatxlate[index];
+
+	return 1;
+}
+
+static inline unsigned int extract_component(unsigned int pixel,
+						struct bvcomponent *desc)
+{
+	unsigned int component;
+	unsigned int component8;
+
+	component = (pixel & desc->mask) >> desc->shift;
+
+	switch (desc->size) {
+	case 0:
+		component8 = 0xFF;
+		break;
+
+	case 1:
+		component8 = component ? 0xFF : 0x00;
+		break;
+
+	case 4:
+		component8 = component | (component << 4);
+		break;
+
+	case 5:
+		component8 = (component << 3) | (component >> 2);
+		break;
+
+	case 6:
+		component8 = (component << 2) | (component >> 4);
+		break;
+
+	default:
+		component8 = component;
+	}
+
+	return component8;
+}
+
+static unsigned int getinternalcolor(void *ptr, struct bvformatxlate *format)
+{
+	unsigned int pixel;
+	unsigned int r, g, b, a;
+
+	switch (format->bitspp) {
+	case 16:
+		pixel = *(unsigned short *) ptr;
+		break;
+
+	case 32:
+		pixel = *(unsigned int *) ptr;
+		break;
+
+	default:
+		pixel = 0;
+	}
+
+	r = extract_component(pixel, &format->rgba.r);
+	g = extract_component(pixel, &format->rgba.g);
+	b = extract_component(pixel, &format->rgba.b);
+	a = extract_component(pixel, &format->rgba.a);
+
+	return	(a << 24) |
+		(r << 16) |
+		(g <<  8) |
+		 b;
+}
+
+/*******************************************************************************
+ * Alpha blending parser.
+ */
+
+struct gcblendconfig {
+	unsigned char factor_mode;
+	unsigned char color_reverse;
+
+	unsigned char destuse;
+	unsigned char srcuse;
+};
+
+struct gcalpha {
+	unsigned int src_global_color;
+	unsigned int dst_global_color;
+
+	unsigned char src_global_alpha_mode;
+	unsigned char dst_global_alpha_mode;
+
+	struct gcblendconfig *src_config;
+	struct gcblendconfig *dst_config;
+};
+
+struct bvblendxlate {
+	unsigned char match1;
+	unsigned char match2;
+
+	struct gcblendconfig dst;
+	struct gcblendconfig src;
+};
 
 #define BVBLENDMATCH(Mode, Inverse, Normal) \
+( \
 	BVBLENDDEF_ ## Mode | \
 	BVBLENDDEF_ ## Inverse | \
-	BVBLENDDEF_ ## Normal
+	BVBLENDDEF_ ## Normal \
+)
 
-#define BVBLENDMODE(Mode, Inverse) \
-	GCDE_BLENDING_MODE_ ## Mode, \
-	GCDE_FACTOR_INVERSE_ ## Inverse
+#define BVDEST(Use) \
+	Use
+
+#define BVSRC(Use) \
+	Use
 
 #define BVBLENDUNDEFINED() \
-	~0, ~0
+	{ ~0, ~0, { 0, 0, 0, 0 }, { 0, 0, 0, 0 } }
 
 static struct bvblendxlate blendxlate[64] = {
 	/**********************************************************************/
@@ -405,8 +1299,21 @@ static struct bvblendxlate blendxlate[64] = {
 		0x00,
 		0x00,
 
-		BVBLENDMODE(ZERO, DISABLE),	/* K0/K3 */
-		BVBLENDMODE(ZERO, DISABLE)	/* K1/K2 */
+		{
+			/* k1 * Cd = 0 * Cd
+			   k3 * Ad = 0 * Ad */
+			GCREG_BLENDING_MODE_ZERO,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(0), BVSRC(0),
+		},
+
+		{
+			/* k2 * Cs = 0 * Cs
+			   k4 * As = 0 * As */
+			GCREG_BLENDING_MODE_ZERO,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(0), BVSRC(0)
+		}
 	},
 
 	/* color factor: 00 00 01 A:(1-Cd,Ad)=Ad
@@ -415,13 +1322,26 @@ static struct bvblendxlate blendxlate[64] = {
 		BVBLENDMATCH(ONLY_A, INV_C1, NORM_A1),
 		BVBLENDMATCH(ONLY_A, INV_C2, NORM_A1),
 
-		BVBLENDMODE(NORMAL, ENABLE),	/* K0/K3 */
-		BVBLENDMODE(NORMAL, DISABLE)	/* K1/K2 */
+		{
+			/* k1 * Cd = Ad * Cd
+			   k3 * Ad = Ad * Ad */
+			GCREG_BLENDING_MODE_NORMAL,
+			GCREG_FACTOR_INVERSE_ENABLE,
+			BVDEST(1), BVSRC(0),
+		},
+
+		{
+			/* k2 * Cs = Ad * Cs
+			   k4 * As = Ad * As */
+			GCREG_BLENDING_MODE_NORMAL,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(1)
+		}
 	},
 
 	/* color factor: 00 00 10 A:(1-Cd,Cs)=undefined
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 00 00 11 A:(1-Cd,As)=As
 	   alpha factor: As ==> 00 00 11 or 00 10 11 */
@@ -429,8 +1349,21 @@ static struct bvblendxlate blendxlate[64] = {
 		BVBLENDMATCH(ONLY_A, INV_C1, NORM_A2),
 		BVBLENDMATCH(ONLY_A, INV_C2, NORM_A2),
 
-		BVBLENDMODE(NORMAL, DISABLE),	/* K0/K3 */
-		BVBLENDMODE(NORMAL, ENABLE)	/* K1/K2 */
+		{
+			/* k1 * Cd = As * Cd
+			   k3 * Ad = As * Ad */
+			GCREG_BLENDING_MODE_NORMAL,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(1),
+		},
+
+		{
+			/* k2 * Cs = As * Cs
+			   k4 * As = As * As */
+			GCREG_BLENDING_MODE_NORMAL,
+			GCREG_FACTOR_INVERSE_ENABLE,
+			BVDEST(0), BVSRC(1)
+		}
 	},
 
 	/* color factor: 00 01 00 A:(1-Ad,Cd)=1-Ad
@@ -439,13 +1372,26 @@ static struct bvblendxlate blendxlate[64] = {
 		BVBLENDMATCH(ONLY_A, INV_A1, NORM_C1),
 		BVBLENDMATCH(ONLY_A, INV_A1, NORM_C2),
 
-		BVBLENDMODE(INVERSED, ENABLE),	/* K0/K3 */
-		BVBLENDMODE(INVERSED, DISABLE)	/* K1/K2 */
+		{
+			/* k1 * Cd = (1 - Ad) * Cd
+			   k3 * Ad = (1 - Ad) * Ad */
+			GCREG_BLENDING_MODE_INVERSED,
+			GCREG_FACTOR_INVERSE_ENABLE,
+			BVDEST(1), BVSRC(0),
+		},
+
+		{
+			/* k2 * Cs = (1 - Ad) * Cs
+			   k4 * As = (1 - Ad) * As */
+			GCREG_BLENDING_MODE_INVERSED,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(1)
+		}
 	},
 
 	/* color factor: 00 01 01 A:(1-Ad,Ad)=undefined
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 00 01 10 A:(1-Ad,Cs)=1-Ad
 	   alpha factor: 1-Ad ==> 00 01 00 or 00 01 10 */
@@ -453,17 +1399,30 @@ static struct bvblendxlate blendxlate[64] = {
 		BVBLENDMATCH(ONLY_A, INV_A1, NORM_C1),
 		BVBLENDMATCH(ONLY_A, INV_A1, NORM_C2),
 
-		BVBLENDMODE(INVERSED, ENABLE),	/* K0/K3 */
-		BVBLENDMODE(INVERSED, DISABLE)	/* K1/K2 */
+		{
+			/* k1 * Cd = (1 - Ad) * Cd
+			   k3 * Ad = (1 - Ad) * Ad */
+			GCREG_BLENDING_MODE_INVERSED,
+			GCREG_FACTOR_INVERSE_ENABLE,
+			BVDEST(1), BVSRC(0),
+		},
+
+		{
+			/* k2 * Cs = (1 - Ad) * Cs
+			   k4 * As = (1 - Ad) * As */
+			GCREG_BLENDING_MODE_INVERSED,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(1)
+		}
 	},
 
 	/* color factor: 00 01 11 A:(1-Ad,As)=undefined
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 00 10 00 A:(1-Cs,Cd)=undefined
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 00 10 01 A:(1-Cs,Ad)=Ad
 	   alpha factor: Ad ==> 00 00 01 or 00 10 01 */
@@ -471,13 +1430,26 @@ static struct bvblendxlate blendxlate[64] = {
 		BVBLENDMATCH(ONLY_A, INV_C1, NORM_A1),
 		BVBLENDMATCH(ONLY_A, INV_C2, NORM_A1),
 
-		BVBLENDMODE(NORMAL, ENABLE),	/* K0/K3 */
-		BVBLENDMODE(NORMAL, DISABLE)	/* K1/K2 */
+		{
+			/* k1 * Cd = Ad * Cd
+			   k3 * Ad = Ad * Ad */
+			GCREG_BLENDING_MODE_NORMAL,
+			GCREG_FACTOR_INVERSE_ENABLE,
+			BVDEST(1), BVSRC(0),
+		},
+
+		{
+			/* k2 * Cs = Ad * Cs
+			   k4 * As = Ad * As */
+			GCREG_BLENDING_MODE_NORMAL,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(1)
+		}
 	},
 
 	/* color factor: 00 10 10 A:(1-Cs,Cs)=undefined
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 00 10 11 A:(1-Cs,As)=As
 	   alpha factor: As ==> 00 00 11 or 00 10 11 */
@@ -485,8 +1457,21 @@ static struct bvblendxlate blendxlate[64] = {
 		BVBLENDMATCH(ONLY_A, INV_C1, NORM_A2),
 		BVBLENDMATCH(ONLY_A, INV_C2, NORM_A2),
 
-		BVBLENDMODE(NORMAL, DISABLE),	/* K0/K3 */
-		BVBLENDMODE(NORMAL, ENABLE)	/* K1/K2 */
+		{
+			/* k1 * Cd = As * Cd
+			   k3 * Ad = As * Ad */
+			GCREG_BLENDING_MODE_NORMAL,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(1),
+		},
+
+		{
+			/* k2 * Cs = As * Cs
+			   k4 * As = As * As */
+			GCREG_BLENDING_MODE_NORMAL,
+			GCREG_FACTOR_INVERSE_ENABLE,
+			BVDEST(0), BVSRC(1)
+		}
 	},
 
 	/* color factor: 00 11 00 A:(1-As,Cd)=1-As
@@ -495,13 +1480,26 @@ static struct bvblendxlate blendxlate[64] = {
 		BVBLENDMATCH(ONLY_A, INV_A2, NORM_C1),
 		BVBLENDMATCH(ONLY_A, INV_A2, NORM_C2),
 
-		BVBLENDMODE(INVERSED, DISABLE),	/* K0/K3 */
-		BVBLENDMODE(INVERSED, ENABLE)	/* K1/K2 */
+		{
+			/* k1 * Cd = (1 - As) * Cd
+			   k3 * Ad = (1 - As) * Ad */
+			GCREG_BLENDING_MODE_INVERSED,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(1),
+		},
+
+		{
+			/* k2 * Cs = (1 - As) * Cs
+			   k4 * As = (1 - As) * As */
+			GCREG_BLENDING_MODE_INVERSED,
+			GCREG_FACTOR_INVERSE_ENABLE,
+			BVDEST(0), BVSRC(1)
+		}
 	},
 
 	/* color factor: 00 11 01 A:(1-As,Ad)=undefined
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 00 11 10 A:(1-As,Cs)=1-As
 	   alpha factor: 1-As ==> 00 11 00 or 00 11 10 */
@@ -509,42 +1507,55 @@ static struct bvblendxlate blendxlate[64] = {
 		BVBLENDMATCH(ONLY_A, INV_A2, NORM_C1),
 		BVBLENDMATCH(ONLY_A, INV_A2, NORM_C2),
 
-		BVBLENDMODE(INVERSED, DISABLE),	/* K0/K3 */
-		BVBLENDMODE(INVERSED, ENABLE)	/* K1/K2 */
+		{
+			/* k1 * Cd = (1 - As) * Cd
+			   k3 * Ad = (1 - As) * Ad */
+			GCREG_BLENDING_MODE_INVERSED,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(1),
+		},
+
+		{
+			/* k2 * Cs = (1 - As) * Cs
+			   k4 * As = (1 - As) * As */
+			GCREG_BLENDING_MODE_INVERSED,
+			GCREG_FACTOR_INVERSE_ENABLE,
+			BVDEST(0), BVSRC(1)
+		}
 	},
 
 	/* color factor: 00 11 11 A:(1-As,As)=undefined
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/**********************************************************************/
 	/* color factor: 01 00 00 MIN:(1-Cd,Cd) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 01 00 01 MIN:(1-Cd,Ad) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 01 00 10 MIN:(1-Cd,Cs) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 01 00 11 MIN:(1-Cd,As) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 01 01 00 MIN:(1-Ad,Cd) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 01 01 01 MIN:(1-Ad,Ad) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 01 01 10 MIN:(1-Ad,Cs) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 01 01 11 MIN:(1-Ad,As)
 	   alpha factor: one ==> 11 11 11 */
@@ -552,29 +1563,42 @@ static struct bvblendxlate blendxlate[64] = {
 		0x3F,
 		0x3F,
 
-		BVBLENDMODE(SATURATED_DEST_ALPHA, DISABLE),	/* K0/K3 */
-		BVBLENDMODE(SATURATED_ALPHA, DISABLE)		/* K1/K2 */
+		{
+			/* k1 * Cd = MIN:(1 - Ad, As) * Cd
+			   k3 * Ad = 1 * Ad */
+			GCREG_BLENDING_MODE_SATURATED_DEST_ALPHA,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(1),
+		},
+
+		{
+			/* k2 * Cs = MIN:(1 - Ad, As) * Cs
+			   k4 * As = 1 * As */
+			GCREG_BLENDING_MODE_SATURATED_ALPHA,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(1)
+		}
 	},
 
 	/* color factor: 01 10 00 MIN:(1-Cs,Cd) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 01 10 01 MIN:(1-Cs,Ad) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 01 10 10 MIN:(1-Cs,Cs) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 01 10 11 MIN:(1-Cs,As) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 01 11 00 MIN:(1-As,Cd) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 01 11 01 MIN:(1-As,Ad)
 	   alpha factor: one ==> 11 11 11 */
@@ -582,87 +1606,100 @@ static struct bvblendxlate blendxlate[64] = {
 		0x3F,
 		0x3F,
 
-		BVBLENDMODE(SATURATED_ALPHA, DISABLE),		/* K0/K3 */
-		BVBLENDMODE(SATURATED_DEST_ALPHA, DISABLE)	/* K1/K2 */
+		{
+			/* k1 * Cd = MIN:(1 - As, Ad) * Cd
+			   k3 * Ad = 1 * Ad */
+			GCREG_BLENDING_MODE_SATURATED_ALPHA,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(1),
+		},
+
+		{
+			/* k2 * Cs = MIN:(1 - As, Ad) * Cs
+			   k4 * As = 1 * As */
+			GCREG_BLENDING_MODE_SATURATED_DEST_ALPHA,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(1)
+		}
 	},
 
 	/* color factor: 01 11 10 MIN:(1-As,Cs) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 01 11 11 MIN:(1-As,As) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/**********************************************************************/
 	/* color factor: 10 00 00 MAX:(1-Cd,Cd) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 10 00 01 MAX:(1-Cd,Ad) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 10 00 10 MAX:(1-Cd,Cs) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 10 00 11 MAX:(1-Cd,As) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 10 01 00 MAX:(1-Ad,Cd) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 10 01 01 MAX:(1-Ad,Ad) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 10 01 10 MAX:(1-Ad,Cs) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 10 01 11 MAX:(1-Ad,As) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 10 10 00 MAX:(1-Cs,Cd) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 10 10 01 MAX:(1-Cs,Ad) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 10 10 10 MAX:(1-Cs,Cs) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 10 10 11 MAX:(1-Cs,As) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 10 11 00 MAX:(1-As,Cd) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 10 11 01 MAX:(1-As,Ad) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 10 11 10 MAX:(1-As,Cs) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 10 11 11 MAX:(1-As,As) ==> not supported
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/**********************************************************************/
 	/* color factor: 11 00 00 C:(1-Cd,Cd)=undefined
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 11 00 01 C:(1-Cd,Ad)=1-Cd
 	   alpha factor: 1-Ad ==> 00 01 00 or 00 01 10 */
@@ -670,15 +1707,26 @@ static struct bvblendxlate blendxlate[64] = {
 		BVBLENDMATCH(ONLY_A, INV_A1, NORM_C1),
 		BVBLENDMATCH(ONLY_A, INV_A1, NORM_C2),
 
-		BVBLENDMODE(COLOR_INVERSED, ENABLE),	/* K0/K3 */
-		BVBLENDMODE(COLOR_INVERSED, DISABLE)	/* K1/K2 */
+		{
+			/* k1 * Cd = (1 - Cd) * Cd
+			   k3 * Ad = (1 - Ad) * Ad */
+			GCREG_BLENDING_MODE_COLOR_INVERSED,
+			GCREG_FACTOR_INVERSE_ENABLE,
+			BVDEST(1), BVSRC(0),
+		},
+
+		{
+			/* k2 * Cs = (1 - Cd) * Cs
+			   k4 * As = (1 - Ad) * As */
+			GCREG_BLENDING_MODE_COLOR_INVERSED,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(1)
+		}
 	},
 
 	/* color factor: 11 00 10 C:(1-Cd,Cs)=undefined
 	   alpha factor: N/A */
-	{
-		BVBLENDUNDEFINED()
-	},
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 11 00 11 C:(1-Cd,As)=1-Cd
 	   alpha factor: 1-Ad ==> 00 01 00 or 00 01 10 */
@@ -686,8 +1734,21 @@ static struct bvblendxlate blendxlate[64] = {
 		BVBLENDMATCH(ONLY_A, INV_A1, NORM_C1),
 		BVBLENDMATCH(ONLY_A, INV_A1, NORM_C2),
 
-		BVBLENDMODE(COLOR_INVERSED, ENABLE),	/* K0/K3 */
-		BVBLENDMODE(COLOR_INVERSED, DISABLE)	/* K1/K2 */
+		{
+			/* k1 * Cd = (1 - Cd) * Cd
+			   k3 * Ad = (1 - Ad) * Ad */
+			GCREG_BLENDING_MODE_COLOR_INVERSED,
+			GCREG_FACTOR_INVERSE_ENABLE,
+			BVDEST(1), BVSRC(0),
+		},
+
+		{
+			/* k2 * Cs = (1 - Cd) * Cs
+			   k4 * As = (1 - Ad) * As */
+			GCREG_BLENDING_MODE_COLOR_INVERSED,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(1)
+		}
 	},
 
 	/* color factor: 11 01 00 C:(1-Ad,Cd)=Cd
@@ -696,13 +1757,26 @@ static struct bvblendxlate blendxlate[64] = {
 		BVBLENDMATCH(ONLY_A, INV_C1, NORM_A1),
 		BVBLENDMATCH(ONLY_A, INV_C2, NORM_A1),
 
-		BVBLENDMODE(COLOR, ENABLE),		/* K0/K3 */
-		BVBLENDMODE(COLOR, DISABLE)		/* K1/K2 */
+		{
+			/* k1 * Cd = Cd * Cd
+			   k3 * Ad = Ad * Ad */
+			GCREG_BLENDING_MODE_COLOR,
+			GCREG_FACTOR_INVERSE_ENABLE,
+			BVDEST(1), BVSRC(0),
+		},
+
+		{
+			/* k2 * Cs = Cd * Cs
+			   k4 * As = Ad * As */
+			GCREG_BLENDING_MODE_COLOR,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(1)
+		}
 	},
 
 	/* color factor: 11 01 01 C:(1-Ad,Ad)=undefined
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 11 01 10 C:(1-Ad,Cs)=Cs
 	   alpha factor: As ==> 00 00 11 or 00 10 11 */
@@ -710,17 +1784,30 @@ static struct bvblendxlate blendxlate[64] = {
 		BVBLENDMATCH(ONLY_A, INV_C1, NORM_A2),
 		BVBLENDMATCH(ONLY_A, INV_C2, NORM_A2),
 
-		BVBLENDMODE(COLOR, DISABLE),		/* K0/K3 */
-		BVBLENDMODE(COLOR, ENABLE)		/* K1/K2 */
+		{
+			/* k1 * Cd = Cs * Cd
+			   k3 * Ad = As * Ad */
+			GCREG_BLENDING_MODE_COLOR,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(1),
+		},
+
+		{
+			/* k2 * Cs = Cs * Cs
+			   k4 * As = As * As */
+			GCREG_BLENDING_MODE_COLOR,
+			GCREG_FACTOR_INVERSE_ENABLE,
+			BVDEST(0), BVSRC(1)
+		}
 	},
 
 	/* color factor: 11 01 11 C:(1-Ad,As)=undefined
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 11 10 00 C:(1-Cs,Cd)=undefined
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 11 10 01 C:(1-Cs,Ad)=1-Cs
 	   alpha factor: 1-As ==> 00 11 00 or 00 11 10 */
@@ -728,13 +1815,26 @@ static struct bvblendxlate blendxlate[64] = {
 		BVBLENDMATCH(ONLY_A, INV_A2, NORM_C1),
 		BVBLENDMATCH(ONLY_A, INV_A2, NORM_C2),
 
-		BVBLENDMODE(COLOR_INVERSED, DISABLE),	/* K0/K3 */
-		BVBLENDMODE(COLOR_INVERSED, ENABLE)	/* K1/K2 */
+		{
+			/* k1 * Cd = (1 - Cs) * Cd
+			   k3 * Ad = (1 - As) * Ad */
+			GCREG_BLENDING_MODE_COLOR_INVERSED,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(1),
+		},
+
+		{
+			/* k2 * Cs = (1 - Cs) * Cs
+			   k4 * As = (1 - As) * As */
+			GCREG_BLENDING_MODE_COLOR_INVERSED,
+			GCREG_FACTOR_INVERSE_ENABLE,
+			BVDEST(0), BVSRC(1)
+		}
 	},
 
 	/* color factor: 11 10 10 C:(1-Cs,Cs)=undefined
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 11 10 11 C:(1-Cs,As)=1-Cs
 	   alpha factor: 1-As ==> 00 11 00 or 00 11 10 */
@@ -742,8 +1842,21 @@ static struct bvblendxlate blendxlate[64] = {
 		BVBLENDMATCH(ONLY_A, INV_A2, NORM_C1),
 		BVBLENDMATCH(ONLY_A, INV_A2, NORM_C2),
 
-		BVBLENDMODE(COLOR_INVERSED, DISABLE),	/* K0/K3 */
-		BVBLENDMODE(COLOR_INVERSED, ENABLE)	/* K1/K2 */
+		{
+			/* k1 * Cd = (1 - Cs) * Cd
+			   k3 * Ad = (1 - As) * Ad */
+			GCREG_BLENDING_MODE_COLOR_INVERSED,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(1),
+		},
+
+		{
+			/* k2 * Cs = (1 - Cs) * Cs
+			   k4 * As = (1 - As) * As */
+			GCREG_BLENDING_MODE_COLOR_INVERSED,
+			GCREG_FACTOR_INVERSE_ENABLE,
+			BVDEST(0), BVSRC(0)
+		}
 	},
 
 	/* color factor: 11 11 00 C:(1-As,Cd)=Cd
@@ -752,13 +1865,26 @@ static struct bvblendxlate blendxlate[64] = {
 		BVBLENDMATCH(ONLY_A, INV_C1, NORM_A1),
 		BVBLENDMATCH(ONLY_A, INV_C2, NORM_A1),
 
-		BVBLENDMODE(COLOR, ENABLE),		/* K0/K3 */
-		BVBLENDMODE(COLOR, DISABLE)		/* K1/K2 */
+		{
+			/* k1 * Cd = Cd * Cd
+			   k3 * Ad = Ad * Ad */
+			GCREG_BLENDING_MODE_COLOR,
+			GCREG_FACTOR_INVERSE_ENABLE,
+			BVDEST(1), BVSRC(0),
+		},
+
+		{
+			/* k2 * Cs = Cd * Cs
+			   k4 * As = Ad * As */
+			GCREG_BLENDING_MODE_COLOR,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(1)
+		}
 	},
 
 	/* color factor: 11 11 01 C:(1-As,Ad)=undefined
 	   alpha factor: N/A */
-	{ BVBLENDUNDEFINED() },
+	BVBLENDUNDEFINED(),
 
 	/* color factor: 11 11 10 C:(1-As,Cs)=Cs
 	   alpha factor: As ==> 00 00 11 or 00 10 11 */
@@ -766,8 +1892,21 @@ static struct bvblendxlate blendxlate[64] = {
 		BVBLENDMATCH(ONLY_A, INV_C1, NORM_A2),
 		BVBLENDMATCH(ONLY_A, INV_C2, NORM_A2),
 
-		BVBLENDMODE(COLOR, DISABLE),		/* K0/K3 */
-		BVBLENDMODE(COLOR, ENABLE)		/* K1/K2 */
+		{
+			/* k1 * Cd = Cs * Cd
+			   k3 * Ad = As * Ad */
+			GCREG_BLENDING_MODE_COLOR,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(1),
+		},
+
+		{
+			/* k2 * Cs = Cs * Cs
+			   k4 * As = As * As */
+			GCREG_BLENDING_MODE_COLOR,
+			GCREG_FACTOR_INVERSE_ENABLE,
+			BVDEST(0), BVSRC(1)
+		}
 	},
 
 	/* color factor: 11 11 11 C:(1-As,As)=one
@@ -776,25 +1915,36 @@ static struct bvblendxlate blendxlate[64] = {
 		0x3F,
 		0x3F,
 
-		BVBLENDMODE(ONE, DISABLE),	/* K0/K3 */
-		BVBLENDMODE(ONE, DISABLE)	/* K1/K2 */
+		{
+			/* k1 * Cd = 1 * Cd
+			   k3 * Ad = 1 * Ad */
+			GCREG_BLENDING_MODE_ONE,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(1), BVSRC(0),
+		},
+
+		{
+			/* k2 * Cs = 1 * Cs
+			   k4 * As = 1 * As */
+			GCREG_BLENDING_MODE_ONE,
+			GCREG_FACTOR_INVERSE_DISABLE,
+			BVDEST(0), BVSRC(1)
+		}
 	}
 };
 
 static enum bverror parse_blend(struct bvbltparams *bltparams,
-	enum bvblend blend, struct bv_alpha *bva)
+	enum bvblend blend, struct gcalpha *gca)
 {
-	enum bverror res;
-	uint32_t global;
-	uint32_t k1, k2, k3, k4;
+	enum bverror bverror;
+	unsigned int global;
+	unsigned int k1, k2, k3, k4;
 	struct bvblendxlate *dstxlate;
 	struct bvblendxlate *srcxlate;
+	unsigned int alpha;
 
 	if ((blend & BVBLENDDEF_REMOTE) != 0) {
-		fprintf(stderr, "%s(%d): remote alpha not supported\n",
-			__FUNCTION__, __LINE__);
-		fflush(stderr);
-		res = BVERR_BLEND;
+		BVSETBLTERROR(BVERR_BLEND, "remote alpha not supported");
 		goto exit;
 	}
 
@@ -802,39 +1952,49 @@ static enum bverror parse_blend(struct bvbltparams *bltparams,
 
 	switch (global) {
 	case (BVBLENDDEF_GLOBAL_NONE >> BVBLENDDEF_GLOBAL_SHIFT):
-		bva->src_global_alpha_mode = AQDE_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_NORMAL;
-		bva->dst_global_alpha_mode = AQDE_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_NORMAL;
+		GC_PRINT(GC_INFO_MSG " BVBLENDDEF_GLOBAL_NONE\n",
+			__func__, __LINE__);
+
+		gca->src_global_alpha_mode = GCREG_GLOBAL_ALPHA_MODE_NORMAL;
+		gca->dst_global_alpha_mode = GCREG_GLOBAL_ALPHA_MODE_NORMAL;
+
+		gca->src_global_alpha_mode =
+		gca->dst_global_alpha_mode = 0;
 		break;
 
 	case (BVBLENDDEF_GLOBAL_UCHAR >> BVBLENDDEF_GLOBAL_SHIFT):
-		bva->src_global_color =
-		bva->dst_global_color =
-			((uint32_t) bltparams->globalalpha.size8) << 24;
+		GC_PRINT(GC_INFO_MSG " BVBLENDDEF_GLOBAL_UCHAR\n",
+			__func__, __LINE__);
 
-		bva->src_global_alpha_mode = AQDE_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_GLOBAL;
-		bva->dst_global_alpha_mode = AQDE_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_GLOBAL;
+		gca->src_global_color =
+		gca->dst_global_color =
+			((unsigned int) bltparams->globalalpha.size8) << 24;
+
+		gca->src_global_alpha_mode = GCREG_GLOBAL_ALPHA_MODE_GLOBAL;
+		gca->dst_global_alpha_mode = GCREG_GLOBAL_ALPHA_MODE_GLOBAL;
 		break;
 
 	case (BVBLENDDEF_GLOBAL_FLOAT >> BVBLENDDEF_GLOBAL_SHIFT):
-		bva->src_global_color =
-		bva->dst_global_color =
-			((uint32_t) ((uint8_t) (255.0f * bltparams->globalalpha.fp))) << 24;
+		GC_PRINT(GC_INFO_MSG " BVBLENDDEF_GLOBAL_FLOAT\n",
+			__func__, __LINE__);
+
+		alpha = gcfp2norm8(bltparams->globalalpha.fp);
+
+		gca->src_global_color =
+		gca->dst_global_color = alpha << 24;
 
-		bva->src_global_alpha_mode = AQDE_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_GLOBAL;
-		bva->dst_global_alpha_mode = AQDE_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_GLOBAL;
+		gca->src_global_alpha_mode = GCREG_GLOBAL_ALPHA_MODE_GLOBAL;
+		gca->dst_global_alpha_mode = GCREG_GLOBAL_ALPHA_MODE_GLOBAL;
 		break;
 
 	default:
-		fprintf(stderr, "%s(%d): invalid global alpha mode.\n",
-			__FUNCTION__, __LINE__);
-		fflush(stderr);
-		res = BVERR_BLEND;
+		BVSETBLTERROR(BVERR_BLEND, "invalid global alpha mode");
 		goto exit;
 	}
 
 	/*
-		Co = K1 x Cd + K2 x Cs
-		Ao = K3 x Ad + K4 x As
+		Co = k1 x Cd + k2 x Cs
+		Ao = k3 x Ad + k4 x As
 	*/
 
 	k1 = (blend >> 18) & 0x3F;
@@ -842,526 +2002,1206 @@ static enum bverror parse_blend(struct bvbltparams *bltparams,
 	k3 = (blend >>  6) & 0x3F;
 	k4 =  blend        & 0x3F;
 
+	GC_PRINT(GC_INFO_MSG " blend = 0x%08X\n", __func__, __LINE__, blend);
+	GC_PRINT(GC_INFO_MSG " k1 = %d\n", __func__, __LINE__, k1);
+	GC_PRINT(GC_INFO_MSG " k2 = %d\n", __func__, __LINE__, k2);
+	GC_PRINT(GC_INFO_MSG " k3 = %d\n", __func__, __LINE__, k3);
+	GC_PRINT(GC_INFO_MSG " k4 = %d\n", __func__, __LINE__, k4);
+
 	dstxlate = &blendxlate[k1];
 	srcxlate = &blendxlate[k2];
 
 	if (((k3 != dstxlate->match1) && (k3 != dstxlate->match2)) ||
 		((k4 != srcxlate->match1) && (k4 != srcxlate->match2))) {
-		fprintf(stderr, "%s(%d): not supported coefficient combination.\n",
-			__FUNCTION__, __LINE__);
-		fflush(stderr);
-		res = BVERR_BLEND;
+		BVSETBLTERROR(BVERR_BLEND,
+				"not supported coefficient combination");
 		goto exit;
 	}
 
-	bva->dst_factor_mode = dstxlate->dst_factor_mode;
-	bva->dst_alpha_factor = dstxlate->dst_alpha_factor;
+	gca->src_config = &dstxlate->dst;
+	gca->dst_config = &srcxlate->src;
 
-	bva->src_factor_mode = srcxlate->src_factor_mode;
-	bva->src_alpha_factor = srcxlate->src_alpha_factor;
+	bverror = BVERR_NONE;
 
-	bva->src_inverse_alpha = AQDE_ALPHA_MODES_SRC_ALPHA_MODE_NORMAL;
-	bva->dst_inverse_alpha = AQDE_ALPHA_MODES_DST_ALPHA_MODE_NORMAL;
+exit:
+	return bverror;
+}
 
-	res = BVERR_NONE;
+/*******************************************************************************
+ * Surface validation.
+ */
 
-exit:
-	return res;
+static int verify_surface(unsigned int tile,
+				union bvinbuff *surf,
+				struct bvsurfgeom *geom,
+				struct bvrect *rect)
+{
+	if (tile) {
+		if (surf->tileparams == NULL)
+			return BVERR_TILE;
+
+		if (surf->tileparams->structsize != STRUCTSIZE(surf->tileparams,
+								srcheight))
+			return BVERR_TILE_VERS;
+
+		if (surf->tileparams->virtaddr == NULL)
+			return BVERR_TILE_VIRTADDR;
+
+		/* FIXME/TODO */
+		return BVERR_TILE;
+	} else {
+		if (surf->desc == NULL)
+			return BVERR_DESC;
+
+		if (surf->desc->structsize != STRUCTSIZE(surf->desc, map))
+			return BVERR_DESC_VERS;
+
+		if (surf->desc->virtaddr == NULL)
+			return BVERR_DESC_VIRTADDR;
+	}
+
+	if (geom == NULL)
+		return BVERR_GEOM;
+
+	if (geom->structsize != STRUCTSIZE(geom, palette))
+		return BVERR_GEOM_VERS;
+
+#if GC_DUMP
+	{
+		struct bvformatxlate *format;
+		if (parse_format(geom->format, &format)) {
+			unsigned int geomsize;
+			unsigned int rectsize;
+
+			geomsize
+				= (geom->width
+				*  geom->height
+				*  format->bitspp) / 8;
+
+			rectsize
+				= (rect->top + rect->height - 1)
+				* geom->virtstride
+				+ ((rect->left + rect->width)
+				* format->bitspp) / 8;
+
+			if (geomsize > surf->desc->length) {
+				GC_PRINT(GC_INFO_MSG
+					" *** invalid geometry %dx%d\n",
+					__func__, __LINE__,
+					geom->width, geom->height);
+			}
+
+			if (rectsize > surf->desc->length) {
+				GC_PRINT(GC_INFO_MSG
+					" *** invalid rectangle "
+					"(%d,%d %dx%d)\n",
+					__func__, __LINE__,
+					rect->left, rect->top,
+					rect->width, rect->height);
+			}
+		}
+	}
+#endif
+
+	return -1;
 }
 
-static enum bverror fill(struct bvbltparams *bltparams)
+/*******************************************************************************
+ * Primitive renderers.
+ */
+
+static enum bverror do_fill(struct bvbltparams *bltparams,
+				struct gcbatch *batch,
+				struct srcdesc *srcdesc)
 {
-	int32_t res;
+	enum bverror bverror;
+	enum bverror unmap_bverror;
 
-	uint32_t buffer[32 * 2];
-	uint32_t *head, *tail;
-	int count;
+	struct gcmofill *gcmofill;
 
-	uint32_t swizzle, format;
-	uint32_t fillcolor;
-	uint8_t use_src = 0, use_dest = 0;
-	int unmap_dest = 0;
-	int k = 0;
+	unsigned char *fillcolorptr;
 
-	int l, t, r, b;
+	struct bvformatxlate *srcformat;
+	struct bvformatxlate *dstformat;
 
-	struct blt blt = {0};
-	struct bvsurfgeom *destgeom = bltparams->dstgeom;
-	struct bvrect *destrect = &bltparams->dstrect;
+	struct bvbuffmap *dstmap = NULL;
+	struct bvsurfgeom *dstgeom = bltparams->dstgeom;
+	struct bvrect *dstrect = &bltparams->dstrect;
+	unsigned int dstoffset;
 
-	swizzle = CONVERT_DEST_SWZZL(destgeom->format);
-	if (swizzle == 0xFFFFFFFF) {
-		fprintf(stderr, "%s(%d): invalid format (%d)\n", __FUNCTION__, __LINE__, destgeom->format);
-		fflush(stderr);
-		res = BVERR_DSTGEOM_FORMAT;
+	if (!parse_format(srcdesc->geom->format, &srcformat)) {
+		BVSETBLTERRORARG((srcdesc->index == 0)
+					? BVERR_SRC1GEOM_FORMAT
+					: BVERR_SRC2GEOM_FORMAT,
+				"invalid source format (%d)",
+				srcdesc->geom->format);
 		goto exit;
 	}
 
-	format = CONVERT_DEST_FMT(destgeom->format);
-	if (format == 0xFFFFFFFF) {
-		fprintf(stderr, "%s(%d): invalid format (%d)\n", __FUNCTION__, __LINE__, destgeom->format);
-		fflush(stderr);
-		res = BVERR_DSTGEOM_FORMAT;
+	if (!parse_format(dstgeom->format, &dstformat)) {
+		BVSETBLTERRORARG(BVERR_DSTGEOM_FORMAT,
+				"invalid destination format (%d)",
+				dstgeom->format);
 		goto exit;
 	}
 
-	if (bltparams->dstdesc->map == NULL) {
-		res = bv_map(bltparams->dstdesc);
-		if (res != 0) {
-			goto exit;
-		}
-		unmap_dest = 1;
+	bverror = do_map(bltparams->dstdesc, 0, &dstmap);
+	if (bverror != BVERR_NONE) {
+		bltparams->errdesc = gccontext.bverrorstr;
+		goto exit;
 	}
 
-	fillcolor = * (uint32_t *) bltparams->src1.desc->virtaddr;
+	dstoffset = (((unsigned int) bltparams->dstdesc->virtaddr
+			& (GC_BASE_ALIGN - 1)) * 8) / dstformat->bitspp;
 
-	GET_2D_RESRC_USAGE(bltparams->op.rop, bltparams->op.rop, use_src, use_dest);
+	bverror = claim_buffer(batch, sizeof(struct gcmofill),
+				(void **) &gcmofill);
+	if (bverror != BVERR_NONE) {
+		BVSETBLTERROR(BVERR_OOM, "failed to allocate command buffer");
+		goto exit;
+	}
 
-	l = destrect->left;
-	t = destrect->top;
-	r = destrect->left + destrect->width;
-	b = destrect->top + destrect->height;
+	memset(gcmofill, 0, sizeof(struct gcmofill));
 
-	head = tail = buffer;
+	GC_PRINT(GC_INFO_MSG " allocated %d of commmand buffer\n",
+		__func__, __LINE__, sizeof(struct gcmofill));
 
-	*tail++ = LS(AQPipeSelectRegAddrs, 1);
-	*tail++ = CONFIG_GPU_PIPE(PIPE2D);
+	/***********************************************************************
+	** Set destination.
+	*/
 
-	*tail++ = LS(AQDESrcRotationConfigRegAddrs, 1);
-	*tail++ =
-		CONFIG_SRC_ROT_MODE(NORMAL) |
-		CONFIG_SRC_ROT_WIDTH(destgeom->width);
+	add_fixup(batch, &gcmofill->dst.address, 0);
+
+	/* Set surface parameters. */
+	gcmofill->dst.address_ldst = gcmodst_address_ldst;
+	gcmofill->dst.address = GET_MAP_HANDLE(dstmap);
+	gcmofill->dst.stride = dstgeom->virtstride;
+	gcmofill->dst.config.reg.swizzle = dstformat->swizzle;
+	gcmofill->dst.config.reg.format = dstformat->format;
+
+	/* Set surface width and height. */
+	gcmofill->dst.rotation.reg.surf_width = dstgeom->width + dstoffset;
+	gcmofill->dst.rotationheight_ldst = gcmodst_rotationheight_ldst;
+	gcmofill->dst.rotationheight.reg.height = dstgeom->height;
+
+	/* Set BLT command. */
+	gcmofill->dst.config.reg.command = GCREG_DEST_CONFIG_COMMAND_CLEAR;
+
+	/* Set clipping. */
+	gcmofill->dst.clip.lt_ldst = gcmoclip_lt_ldst;
+
+	if ((bltparams->flags & BVFLAG_CLIP) == BVFLAG_CLIP) {
+		gcmofill->dst.clip.lt.reg.left
+			= bltparams->cliprect.left + dstoffset;
+		gcmofill->dst.clip.lt.reg.top
+			= bltparams->cliprect.top;
+		gcmofill->dst.clip.rb.reg.right
+			= gcmofill->dst.clip.lt.reg.left
+			+ bltparams->cliprect.width;
+		gcmofill->dst.clip.rb.reg.bottom
+			= gcmofill->dst.clip.lt.reg.top
+			+ bltparams->cliprect.height;
+	} else {
+		gcmofill->dst.clip.lt.reg.left = GC_CLIP_RESET_LEFT;
+		gcmofill->dst.clip.lt.reg.top = GC_CLIP_RESET_TOP;
+		gcmofill->dst.clip.rb.reg.right = GC_CLIP_RESET_RIGHT;
+		gcmofill->dst.clip.rb.reg.bottom = GC_CLIP_RESET_BOTTOM;
+	}
 
-	*tail++ = LS(AQDESrcRotationHeightRegAddrs, 1);
-	*tail++ = CONFIG_SRC_ROT_HEIGHT(destgeom->height);
+	/***********************************************************************
+	** Set source.
+	*/
 
-	*tail++ = LS(AQDEDestAddressRegAddrs, 1);
-	*tail++ = (uint32_t) bltparams->dstdesc->map;
-	blt.offset[k++] = tail - head;
+	/* Set surface dummy width and height. */
+	gcmofill->src.rotation_ldst = gcmofillsrc_rotation_ldst;
+	gcmofill->src.rotation.reg.surf_width = dstgeom->width;
+	gcmofill->src.rotationheight_ldst = gcmofillsrc_rotationheight_ldst;
+	gcmofill->src.rotationheight.reg.height = dstgeom->height;
 
-	*tail++ = LS(AQDEDestStrideRegAddrs, 1);
-	*tail++ = destgeom->virtstride;
+	/* Set ROP3. */
+	gcmofill->src.rop_ldst = gcmofillsrc_rop_ldst;
+	gcmofill->src.rop.reg.type = GCREG_ROP_TYPE_ROP3;
+	gcmofill->src.rop.reg.fg = (unsigned char) bltparams->op.rop;
 
-	*tail++ = LS(AQDEDestRotationConfigRegAddrs, 1);
-	*tail++ =
-		CONFIG_DEST_ROT_MODE(NORMAL) |
-		CONFIG_DEST_ROT_WIDTH(destgeom->width);
+	/***********************************************************************
+	** Set fill color.
+	*/
 
-	*tail++ = LS(AQDEDestConfigRegAddrs, 1);
-	*tail++ =
-		CONFIG_DEST_CMD(CLEAR) |
-		CONFIG_DEST_SWIZZLE(swizzle) |
-		CONFIG_DEST_FMT(format);
+	fillcolorptr
+		= (unsigned char *) srcdesc->buf.desc->virtaddr
+		+ srcdesc->rect->top * srcdesc->geom->virtstride
+		+ srcdesc->rect->left * srcformat->bitspp / 8;
 
-	*tail++ = LS((AQDEDstRotationHeightRegAddrs), 1);
-	*tail++ = destgeom->height;
+	gcmofill->clearcolor_ldst = gcmofill_clearcolor_ldst;
+	gcmofill->clearcolor.raw = getinternalcolor(fillcolorptr, srcformat);
 
-	*tail++ = LS(AQDEClipTopLeftRegAddrs, 1);
-	*tail++ = CONFIG_CLIP_LFTTOP(l, t);
-	*tail++ = LS(AQDEClipBottomRightRegAddrs, 1);
-	*tail++ = CONFIG_CLIP_RHTBTM(r, b);
+	/***********************************************************************
+	** Configure and start fill.
+	*/
 
-	*tail++ = LS(AQDEClearPixelValue32RegAddrs, 1);
-	*tail++ = fillcolor;
+	/* Set START_DE command. */
+	gcmofill->start.startde.cmd.fld = gcfldstartde;
 
-	if (use_src || use_dest) {
-		*tail++ = LS(AQFlushRegAddrs, 1);
-		*tail++ = CONFIG_PE2DCACHE_FLUSH();
-	}
+	/* Set destination rectangle. */
+	gcmofill->start.rect.left
+		= dstrect->left + dstoffset;
+	gcmofill->start.rect.top
+		= dstrect->top;
+	gcmofill->start.rect.right
+		= gcmofill->start.rect.left + dstrect->width;
+	gcmofill->start.rect.bottom
+		= gcmofill->start.rect.top + dstrect->height;
 
-	*tail++ = LS(AQDERopRegAddrs, 1);
-	*tail++ =
-		CONFIG_ROP_TYPE(AQDE_ROP_TYPE_ROP3) |
-		CONFIG_ROP_FORGND(bltparams->op.rop);
-
-	*tail++ = CONFIG_START_DE(1);
-	*tail++ = 0xC0FFEE;
-	*tail++ = CONFIG_START_DE_LFTTOP(l, t);
-	*tail++ = CONFIG_START_DE_RGHBTM(r, b);
-
-	*tail++ = LS(AQFlushRegAddrs, 1);
-	*tail++ = CONFIG_PE2DCACHE_FLUSH();
-
-	count = tail - head;
-	if (count > COUNTOF(buffer)) {
-		fprintf(stderr, "%s(%d): !!! buffer overrun (%d) !!!\n",
-			__FUNCTION__, __LINE__, count);
-		fflush(stderr);
-		res = BVERR_OOM;
-		goto exit;
+	/* Flush PE cache. */
+	gcmofill->start.flush.flush_ldst = gcmoflush_flush_ldst;
+	gcmofill->start.flush.flush.reg = gcregflush_pe2D;
+
+exit:
+	if (dstmap != NULL) {
+		unmap_bverror = schedule_unmap(batch, bltparams->dstdesc);
+		if ((unmap_bverror != BVERR_NONE) && (bverror == BVERR_NONE)) {
+			bltparams->errdesc = gccontext.bverrorstr;
+			bverror = unmap_bverror;
+		}
 	}
 
-	blt.cmdbuf = head;
-	blt.cmdlen = count * sizeof(uint32_t);
+	return bverror;
+}
+
+static enum bverror do_blit_end(struct bvbltparams *bltparams,
+				struct gcbatch *batch)
+{
+	enum bverror bverror;
+	struct gcmomultisrc *gcmomultisrc;
+	struct gcmostart *gcmostart;
+	unsigned int buffersize;
+
+	GC_PRINT(GC_INFO_MSG " finalizing the blit, scrcount = %d\n",
+		__func__, __LINE__, batch->op.gcblit.srccount);
 
-	res = ioctl(fd, BLT, (uint32_t) &blt);
-	if (res != 0) {
-		fprintf(stderr, "%s(%d): ioctl failed\n", __FUNCTION__, __LINE__);
-		fflush(stderr);
-		res = BVERR_UNK;
+	buffersize
+		= sizeof(struct gcmomultisrc)
+		+ sizeof(struct gcmostart);
+
+	bverror = claim_buffer(batch, buffersize, (void **) &gcmomultisrc);
+	if (bverror != BVERR_NONE) {
+		BVSETBLTERROR(BVERR_OOM, "failed to allocate command buffer");
 		goto exit;
 	}
 
-	/* no errors, so exit */
-	res = BVERR_NONE;
+	/* Reset the finalizer. */
+	batch->batchend = do_end;
+
+	/***********************************************************************
+	** Set multi-source control.
+	*/
+
+	gcmomultisrc->control_ldst = gcmomultisrc_control_ldst;
+	gcmomultisrc->control.reg.srccount = batch->op.gcblit.srccount - 1;
+	gcmomultisrc->control.reg.horblock
+		= GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL128;
+
+	gcmostart = (struct gcmostart *) (gcmomultisrc + 1);
+
+	/* Set START_DE command. */
+	gcmostart->startde.cmd.fld = gcfldstartde;
+
+	/* Set destination rectangle. */
+	gcmostart->rect = batch->op.gcblit.dstrect;
+
+	/* Flush PE cache. */
+	gcmostart->flush.flush_ldst = gcmoflush_flush_ldst;
+	gcmostart->flush.flush.reg = gcregflush_pe2D;
 
 exit:
-	if (unmap_dest) bv_unmap(bltparams->dstdesc);
-	return res;
+	return bverror;
 }
 
-static enum bverror blit(struct bvbltparams *bltparams)
+static enum bverror do_blit(struct bvbltparams *bltparams,
+				struct gcbatch *batch,
+				struct srcdesc *srcdesc,
+				unsigned int srccount,
+				struct gcalpha *gca)
 {
-	int32_t res;
-
-	uint32_t buffer[128 * 2];
-	uint32_t *head, *tail;
-	int count;
-
-	int i, k = 0;
-	uint32_t index;
-	uint32_t src_swizzle, src_format;
-	uint32_t dst_swizzle, dst_format;
-	uint8_t use_src = 0, use_dest = 0;
-	uint8_t rop_fg, rop_bg;
-	int l, t, r, b;
-	int unmap_dest = 0, unmap_src[2] = {0};
-
-	int enable_blend;
-	struct bv_alpha bva = {0};
-
-	struct blt blt = {0};
-	struct bvsurfgeom *destgeom = bltparams->dstgeom;
-	struct bvrect *destrect = &bltparams->dstrect;
-
-	struct bvbuffdesc *srcdesc[2];
-	struct bvsurfgeom *srcgeom[2];
-	struct bvrect *srcrect[2];
-
-	dst_swizzle = CONVERT_DEST_SWZZL(destgeom->format);
-	if (dst_swizzle == 0xFFFFFFFF) {
-		fprintf(stderr, "%s(%d): invalid format (%d)\n", __FUNCTION__, __LINE__, destgeom->format);
-		fflush(stderr);
-		res = BVERR_DSTGEOM_FORMAT;
+	enum bverror bverror;
+	enum bverror unmap_bverror;
+
+	unsigned int buffersize;
+	void *buffer;
+	struct gcmodst *gcmodst;
+	struct gcmosrc *gcmosrc;
+
+	unsigned int i, index;
+	unsigned int startblit;
+
+	struct bvformatxlate *srcformat[2];
+	struct bvbuffmap *srcmap[2] = { NULL, NULL };
+	struct bvsurfgeom *srcgeom;
+	struct bvrect *srcrect;
+	int srcsurfleft, srcsurftop;
+	int srcleft[2], srctop[2];
+	int srcshift[2];
+	int srcoffset;
+	int srcadjust;
+
+	struct bvformatxlate *dstformat;
+	struct bvbuffmap *dstmap = NULL;
+	struct bvsurfgeom *dstgeom = bltparams->dstgeom;
+	unsigned int dstleft, dsttop;
+	unsigned int dstright, dstbottom;
+	unsigned int dstoffset;
+
+	unsigned int multiblit = 1;
+
+	if (!parse_format(dstgeom->format, &dstformat)) {
+		BVSETBLTERRORARG(BVERR_DSTGEOM_FORMAT,
+				"invalid destination format (%d)",
+				dstgeom->format);
 		goto exit;
 	}
 
-	dst_format = CONVERT_DEST_FMT(destgeom->format);
-	if (dst_format == 0xFFFFFFFF) {
-		fprintf(stderr, "%s(%d): invalid format (%d)\n", __FUNCTION__, __LINE__, destgeom->format);
-		fflush(stderr);
-		res = BVERR_DSTGEOM_FORMAT;
+	bverror = do_map(bltparams->dstdesc, 0, &dstmap);
+	if (bverror != BVERR_NONE) {
+		bltparams->errdesc = gccontext.bverrorstr;
 		goto exit;
 	}
 
-	enable_blend = (bltparams->flags == BVFLAG_BLEND);
-	if (enable_blend) {
-		res = parse_blend(bltparams, bltparams->op.blend, &bva);
-		if (res != BVERR_NONE) {
+	/* Determine destination coordinates. */
+	dstleft   = bltparams->dstrect.left;
+	dsttop    = bltparams->dstrect.top;
+	dstright  = bltparams->dstrect.width  + dstleft;
+	dstbottom = bltparams->dstrect.height + dsttop;
+
+	dstoffset = (((unsigned int) bltparams->dstdesc->virtaddr
+			& (GC_BASE_ALIGN - 1)) * 8) / dstformat->bitspp;
+
+	GC_PRINT(GC_INFO_MSG " dstaddr = 0x%08X\n",
+		__func__, __LINE__,
+		(unsigned int) bltparams->dstdesc->virtaddr);
+
+	GC_PRINT(GC_INFO_MSG " dstsurf = %dx%d, stride = %ld\n",
+		__func__, __LINE__,
+		bltparams->dstgeom->width, bltparams->dstgeom->height,
+		bltparams->dstgeom->virtstride);
+
+	GC_PRINT(GC_INFO_MSG " dstrect = (%d,%d)-(%d,%d), dstoffset = %d\n",
+		__func__, __LINE__,
+		dstleft, dsttop, dstright, dstbottom, dstoffset);
+
+	GC_PRINT(GC_INFO_MSG " dstrect = %dx%d\n",
+		__func__, __LINE__,
+		bltparams->dstrect.width, bltparams->dstrect.height);
+
+	dstleft  += dstoffset;
+	dstright += dstoffset;
+
+	/* Set destination coordinates. */
+	batch->op.gcblit.dstrect.left   = dstleft;
+	batch->op.gcblit.dstrect.top    = dsttop;
+	batch->op.gcblit.dstrect.right  = dstright;
+	batch->op.gcblit.dstrect.bottom = dstbottom;
+
+	for (i = 0; i < srccount; i += 1) {
+		srcgeom = srcdesc[i].geom;
+		srcrect = srcdesc[i].rect;
+
+		if (!parse_format(srcgeom->format, &srcformat[i])) {
+			BVSETBLTERRORARG((srcdesc[i].index == 0)
+						? BVERR_SRC1GEOM_FORMAT
+						: BVERR_SRC2GEOM_FORMAT,
+					"invalid source format (%d)",
+					srcgeom->format);
 			goto exit;
 		}
-	}
 
-	if ((destgeom->format & OCDFMTDEF_NON_PREMULT) != 0) {
-		bva.dst_premul_dst_alpha = AQDE_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_ENABLE;
-		bva.dst_demul_dst_alpha = AQDE_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_ENABLE;
-	} else {
-		bva.dst_premul_dst_alpha = AQDE_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_DISABLE;
-		bva.dst_demul_dst_alpha = AQDE_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_DISABLE;
-	}
+		srcoffset = (((unsigned int) srcdesc[i].buf.desc->virtaddr
+				& (GC_BASE_ALIGN - 1)) * 8)
+				/ srcformat[i]->bitspp;
 
-	bva.src_premul_global_mode = AQDE_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_DISABLE;
+		GC_PRINT(GC_INFO_MSG " srcaddr[%d] = 0x%08X\n",
+			__func__, __LINE__,
+			i, (unsigned int) srcdesc[i].buf.desc->virtaddr);
 
-	l = destrect->left;
-	t = destrect->top;
-	r = destrect->left + destrect->width;
-	b = destrect->top + destrect->height;
+		GC_PRINT(GC_INFO_MSG " srcsurf%d = %dx%d, stride%d = %ld\n",
+			__func__, __LINE__,
+			i, srcgeom->width, srcgeom->height,
+			i, srcgeom->virtstride);
 
-	srcdesc[0] = bltparams->src1.desc;
-	srcdesc[1] = bltparams->src2.desc;
+		GC_PRINT(GC_INFO_MSG
+			" srcrect%d = (%d,%d)-(%d,%d), srcoffset%d = %d\n",
+			__func__, __LINE__,
+			i,
+			srcrect->left, srcrect->top,
+			srcrect->left + srcrect->width,
+			srcrect->top  + srcrect->height,
+			i,
+			srcoffset);
 
-	srcgeom[0] = bltparams->src1geom;
-	srcgeom[1] = bltparams->src2geom;
+		GC_PRINT(GC_INFO_MSG " srcrect%d = %dx%d\n",
+			__func__, __LINE__,
+			i, srcrect->width, srcrect->height);
 
-	srcrect[0] = &bltparams->src1rect;
-	srcrect[1] = &bltparams->src2rect;
+		srcsurfleft = srcrect->left - dstleft + srcoffset;
+		srcsurftop  = srcrect->top  - dsttop;
 
-	head = tail = buffer;
+		GC_PRINT(GC_INFO_MSG " source %d surface origin = %d,%d\n",
+			__func__, __LINE__, i, srcsurfleft, srcsurftop);
 
-	*tail++ = LS(AQPipeSelectRegAddrs, 1);
-	*tail++ = CONFIG_GPU_PIPE(PIPE2D);
+		srcadjust = srcsurfleft % 4;
+		srcsurfleft -= srcadjust;
+		srcleft[i] = dstleft + srcadjust;
+		srctop[i]  = dsttop;
 
-	for (i = 0, index = 0; i < 2; i += 1) {
-		if (srcdesc[i] == NULL) {
-			continue;
-		}
+		GC_PRINT(GC_INFO_MSG " srcadjust%d = %d\n",
+			__func__, __LINE__, i, srcadjust);
+
+		GC_PRINT(GC_INFO_MSG
+			" adjusted source %d surface origin = %d,%d\n",
+			__func__, __LINE__, i, srcsurfleft, srcsurftop);
+
+		GC_PRINT(GC_INFO_MSG " source %d rectangle origin = %d,%d\n",
+			__func__, __LINE__, i, srcleft[i], srctop[i]);
+
+		srcshift[i]
+			= srcsurftop * (int) srcgeom->virtstride
+			+ srcsurfleft * (int) srcformat[i]->bitspp / 8;
+
+		if (srcadjust != 0)
+			multiblit = 0;
 
-		src_swizzle = CONVERT_SRC_SWZZL(srcgeom[i]->format);
-		if (src_swizzle == 0xFFFFFFFF) {
-			fprintf(stderr, "%s(%d): invalid format (%d)\n",
-				__FUNCTION__, __LINE__, srcgeom[i]->format);
-			fflush(stderr);
-			i == 0 ? (res = BVERR_SRC1GEOM_FORMAT) : (res = BVERR_SRC2GEOM_FORMAT);
+		GC_PRINT(GC_INFO_MSG " srcshift[%d] = 0x%08X\n",
+			__func__, __LINE__, i, srcshift[i]);
+
+		bverror = do_map(srcdesc[i].buf.desc, 0, &srcmap[i]);
+		if (bverror != BVERR_NONE) {
+			bltparams->errdesc = gccontext.bverrorstr;
 			goto exit;
 		}
+	}
+
+	GC_PRINT(GC_INFO_MSG " multiblit = %d\n",
+		__func__, __LINE__, multiblit);
 
-		src_format = CONVERT_SRC_GCFMT(srcgeom[i]->format);
-		if (src_format == 0xFFFFFFFF) {
-			fprintf(stderr, "%s(%d): invalid format (%d)\n",
-				__FUNCTION__, __LINE__, srcgeom[i]->format);
-			fflush(stderr);
-			i == 0 ? (res = BVERR_SRC1GEOM_FORMAT) : (res = BVERR_SRC2GEOM_FORMAT);
+	if ((batch->batchend == do_blit_end) &&
+		(batch->op.gcblit.srccount < 4)) {
+		GC_PRINT(GC_ERR_MSG " adding new source to the operation\n",
+			__func__, __LINE__);
+
+		startblit = 0;
+		buffersize = sizeof(struct gcmosrc) * srccount;
+	} else {
+		if (batch->batchend == do_blit_end) {
+			GC_PRINT(GC_INFO_MSG
+				" maximum number of sources reached\n",
+				__func__, __LINE__);
+		} else {
+			GC_PRINT(GC_INFO_MSG
+				" another operation in progress\n",
+				__func__, __LINE__);
+		}
+
+		bverror = batch->batchend(bltparams, batch);
+		if (bverror != BVERR_NONE)
 			goto exit;
+
+		startblit = 1;
+		buffersize
+			= sizeof(struct gcmodst)
+			+ sizeof(struct gcmosrc) * srccount;
+
+		batch->batchend = do_blit_end;
+		batch->op.gcblit.srccount = 0;
+	}
+
+	bverror = claim_buffer(batch, buffersize, &buffer);
+	if (bverror != BVERR_NONE) {
+		BVSETBLTERROR(BVERR_OOM, "failed to allocate command buffer");
+		goto exit;
+	}
+
+	memset(buffer, 0, buffersize);
+
+	GC_PRINT(GC_INFO_MSG " allocated %d of commmand buffer\n",
+		__func__, __LINE__, buffersize);
+
+	/***********************************************************************
+	** Set destination.
+	*/
+
+	if (startblit) {
+		GC_PRINT(GC_INFO_MSG " processing the destiantion\n",
+			__func__, __LINE__);
+
+		gcmodst = (struct gcmodst *) buffer;
+
+		add_fixup(batch, &gcmodst->address, 0);
+
+		/* Set surface parameters. */
+		gcmodst->address_ldst = gcmodst_address_ldst;
+		gcmodst->address = GET_MAP_HANDLE(dstmap);
+		gcmodst->stride = dstgeom->virtstride;
+		gcmodst->config.reg.swizzle = dstformat->swizzle;
+		gcmodst->config.reg.format = dstformat->format;
+
+		/* Set surface width and height. */
+		gcmodst->rotation.reg.surf_width = dstgeom->width + dstoffset;
+		gcmodst->rotationheight_ldst = gcmodst_rotationheight_ldst;
+		gcmodst->rotationheight.reg.height = dstgeom->height;
+
+		/* Set BLT command. */
+		gcmodst->config.reg.command = multiblit
+			? GCREG_DEST_CONFIG_COMMAND_MULTI_SOURCE_BLT
+			: GCREG_DEST_CONFIG_COMMAND_BIT_BLT;
+
+		/* Set clipping. */
+		gcmodst->clip.lt_ldst = gcmoclip_lt_ldst;
+
+		if ((bltparams->flags & BVFLAG_CLIP) == BVFLAG_CLIP) {
+			gcmodst->clip.lt.reg.left
+				= bltparams->cliprect.left + dstoffset;
+			gcmodst->clip.lt.reg.top
+				= bltparams->cliprect.top;
+			gcmodst->clip.rb.reg.right
+				= gcmodst->clip.lt.reg.left
+				+ bltparams->cliprect.width;
+			gcmodst->clip.rb.reg.bottom
+				= gcmodst->clip.lt.reg.top
+				+ bltparams->cliprect.height;
+		} else {
+			gcmodst->clip.lt.reg.left = GC_CLIP_RESET_LEFT;
+			gcmodst->clip.lt.reg.top = GC_CLIP_RESET_TOP;
+			gcmodst->clip.rb.reg.right = GC_CLIP_RESET_RIGHT;
+			gcmodst->clip.rb.reg.bottom = GC_CLIP_RESET_BOTTOM;
 		}
 
-		if (srcdesc[i]->map == NULL) {
-			res = bv_map(srcdesc[i]);
-			if (res != 0)
-				goto exit;
-			unmap_src[i] = 1;
+		/* Determine location of source states. */
+		gcmosrc = (struct gcmosrc *) (gcmodst + 1);
+	} else {
+		GC_PRINT(GC_INFO_MSG " skipping the destiantion\n",
+			__func__, __LINE__);
+
+		/* Determine location of source states. */
+		gcmosrc = (struct gcmosrc *) buffer;
+	}
+
+	/***********************************************************************
+	** Set source(s).
+	*/
+
+	GC_PRINT(GC_INFO_MSG " processing %d sources\n",
+		__func__, __LINE__, srccount);
+
+	index = batch->op.gcblit.srccount;
+
+	for (i = 0; i < srccount; i += 1, index += 1) {
+		srcgeom = srcdesc[i].geom;
+
+		add_fixup(batch, &gcmosrc->address, srcshift[i]);
+
+		/* Set surface parameters. */
+		gcmosrc->address_ldst = gcmosrc_address_ldst[index];
+		gcmosrc->address = GET_MAP_HANDLE(srcmap[i]);
+
+		gcmosrc->stride_ldst = gcmosrc_stride_ldst[index];
+		gcmosrc->stride = srcgeom->virtstride;
+
+		gcmosrc->rotation_ldst = gcmosrc_rotation_ldst[index];
+		gcmosrc->rotation.reg.surf_width = dstleft + srcgeom->width;
+
+		gcmosrc->config_ldst = gcmosrc_config_ldst[index];
+		gcmosrc->config.reg.swizzle = srcformat[i]->swizzle;
+		gcmosrc->config.reg.format = srcformat[i]->format;
+
+		gcmosrc->origin_ldst = gcmosrc_origin_ldst[index];
+		if (multiblit) {
+			gcmosrc->origin.reg = gcregsrcorigin_min;
+		} else {
+			gcmosrc->origin.reg.x = srcleft[i];
+			gcmosrc->origin.reg.y = srctop[i];
 		}
 
-		if (enable_blend) {
-			rop_fg = 0xCC;
-			rop_bg = 0xCC;
+		gcmosrc->size_ldst = gcmosrc_size_ldst[index];
+		gcmosrc->size.reg = gcregsrcsize_max;
+
+		gcmosrc->rotationheight_ldst
+			= gcmosrc_rotationheight_ldst[index];
+		gcmosrc->rotationheight.reg.height = dsttop + srcgeom->height;
+
+		gcmosrc->rop_ldst = gcmosrc_rop_ldst[index];
+		gcmosrc->rop.reg.type = GCREG_ROP_TYPE_ROP3;
+		gcmosrc->rop.reg.fg = (gca != NULL)
+			? 0xCC : (unsigned char) bltparams->op.rop;
+
+		gcmosrc->mult_ldst = gcmosrc_mult_ldst[index];
+		gcmosrc->mult.reg.srcglobalpremul
+		= GCREG_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_DISABLE;
+
+		if ((srcgeom->format & OCDFMTDEF_NON_PREMULT) != 0)
+			gcmosrc->mult.reg.srcpremul
+			= GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_ENABLE;
+		else
+			gcmosrc->mult.reg.srcpremul
+			= GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_DISABLE;
+
+		if ((dstgeom->format & OCDFMTDEF_NON_PREMULT) != 0) {
+			gcmosrc->mult.reg.dstpremul
+			= GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_ENABLE;
+
+			gcmosrc->mult.reg.dstdemul
+			= GCREG_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_ENABLE;
 		} else {
-			rop_fg = bltparams->op.rop;
-			rop_bg = bltparams->op.rop;
+			gcmosrc->mult.reg.dstpremul
+			= GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_DISABLE;
+
+			gcmosrc->mult.reg.dstdemul
+			= GCREG_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_DISABLE;
 		}
 
-		GET_2D_RESRC_USAGE(rop_fg, rop_bg, use_src, use_dest);
-
-		bva.src_premul_src_alpha
-			= ((srcgeom[i]->format & OCDFMTDEF_NON_PREMULT) != 0)
-				? AQDE_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_ENABLE
-				: AQDE_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_DISABLE;
-
-		*tail++ = LS((gcregDESrcAddressRegAddrs + index), 1);
-		*tail++ = (uint32_t) srcdesc[i]->map;
-		blt.offset[k++] = tail - head;
-
-		*tail++ = LS((gcregDESrcStrideRegAddrs + index), 1);
-		*tail++ = srcgeom[i]->virtstride;
-
-		*tail++ = LS((gcregDESrcRotationConfigRegAddrs + index), 1);
-		*tail++ =
-			CONFIG_MLTSRC_ROT_MODE(NORMAL) |
-			CONFIG_MLTSRC_ROT_WIDTH(srcrect[i]->width);
-
-		*tail++ = LS((gcregDESrcConfigRegAddrs + index), 1);
-		*tail++ =
-			CONFIG_MLTSRC_LOC(MEMORY) |
-			CONFIG_MLTSRC_FMT(src_format) |
-			CONFIG_MLTSRC_SWIZZLE(src_swizzle);
-
-		*tail++ = LS((gcregDESrcOriginRegAddrs + index), 1);
-		*tail++ =
-			CONFIG_MLTSRC_ORIGIN(srcrect[i]->top, srcrect[i]->left);
-
-		*tail++ = LS((gcregDESrcSizeRegAddrs + index), 1);
-		*tail++ =
-			CONFIG_MLTSRC_SIZE(srcrect[i]->left + srcrect[i]->width,
-					srcrect[i]->top + srcrect[i]->height);
-
-		*tail++ = LS((gcregDERopRegAddrs + index), 1);
-		*tail++ =
-			CONFIG_MLTSRC_ROP_TYPE(GCREG_DE_ROP_TYPE_ROP4) |
-			CONFIG_MLTSRC_ROP_BCKGND(rop_bg) |
-			CONFIG_MLTSRC_ROP_FORGND(rop_fg);
-
-		*tail++ = LS((gcregDESrcRotationHeightRegAddrs + index), 1);
-		*tail++ = srcrect[i]->height;
-
-		/* blend */
-		if (enable_blend && (i > 0)) {
-			*tail++ = LS(gcregDEAlphaControlRegAddrs + index, 1);
-			*tail++ = CONFIG_ALPHA_CTRL(ON);
-
-			*tail++ = LS(gcregDEAlphaModesRegAddrs + index, 1);
-			*tail++ =
-				SETFIELD(0, AQDE_ALPHA_MODES, SRC_ALPHA_MODE, bva.src_inverse_alpha) |
-				SETFIELD(0, AQDE_ALPHA_MODES, DST_ALPHA_MODE, bva.dst_inverse_alpha) |
-				SETFIELD(0, AQDE_ALPHA_MODES, GLOBAL_SRC_ALPHA_MODE, bva.src_global_alpha_mode) |
-				SETFIELD(0, AQDE_ALPHA_MODES, GLOBAL_DST_ALPHA_MODE, bva.dst_global_alpha_mode) |
-				SETFIELD(0, AQDE_ALPHA_MODES, SRC_BLENDING_MODE, bva.src_factor_mode) |
-				SETFIELD(0, AQDE_ALPHA_MODES, DST_BLENDING_MODE, bva.dst_factor_mode) |
-				SETFIELD(0, AQDE_ALPHA_MODES, SRC_ALPHA_FACTOR, bva.src_alpha_factor) |
-				SETFIELD(0, AQDE_ALPHA_MODES, DST_ALPHA_FACTOR, bva.dst_alpha_factor);
-
-			if (bva.src_global_alpha_mode != AQDE_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_NORMAL) {
-				*tail++ = LS(gcregDEGlobalSrcColorRegAddrs + index, 1);
-				*tail++ = bva.src_global_color;
-			}
+		gcmosrc->alphacontrol_ldst = gcmosrc_alphacontrol_ldst[index];
+		gcmosrc->alphamodes_ldst = gcmosrc_alphamodes_ldst[index];
+		gcmosrc->srcglobal_ldst = gcmosrc_srcglobal_ldst[index];
+		gcmosrc->dstglobal_ldst = gcmosrc_dstglobal_ldst[index];
+
+		if ((gca != NULL) && ((srccount == 1) || (i > 0))) {
+			gcmosrc->alphacontrol.reg.enable
+				= GCREG_ALPHA_CONTROL_ENABLE_ON;
+
+			gcmosrc->alphamodes.reg.src_global_alpha
+				= gca->src_global_alpha_mode;
+			gcmosrc->alphamodes.reg.dst_global_alpha
+				= gca->dst_global_alpha_mode;
+			gcmosrc->alphamodes.reg.src_blend
+				= gca->src_config->factor_mode;
+			gcmosrc->alphamodes.reg.dst_blend
+				= gca->dst_config->factor_mode;
+			gcmosrc->alphamodes.reg.src_color_reverse
+				= gca->src_config->color_reverse;
+			gcmosrc->alphamodes.reg.dst_color_reverse
+				= gca->dst_config->color_reverse;
+
+			gcmosrc->srcglobal.raw = gca->src_global_color;
+			gcmosrc->dstglobal.raw = gca->dst_global_color;
+		} else
+			gcmosrc->alphacontrol.reg.enable
+				= GCREG_ALPHA_CONTROL_ENABLE_OFF;
+
+		gcmosrc += 1;
+		batch->op.gcblit.srccount += 1;
+	}
 
-			if (bva.dst_global_alpha_mode != AQDE_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_NORMAL) {
-				*tail++ = LS(gcregDEGlobalDestColorRegAddrs + index, 1);
-				*tail++ = bva.dst_global_color;
+exit:
+	for (i = 0; i < 2; i += 1)
+		if (srcmap[i] != NULL) {
+			unmap_bverror = schedule_unmap(batch,
+							srcdesc[i].buf.desc);
+			if ((unmap_bverror != BVERR_NONE) &&
+				(bverror == BVERR_NONE)) {
+				bltparams->errdesc = gccontext.bverrorstr;
+				bverror = unmap_bverror;
 			}
-		} else {
-			*tail++ = LS(gcregDEAlphaControlRegAddrs + index, 1);
-			*tail++ = CONFIG_ALPHA_CTRL(OFF);
 		}
 
-		*tail++ = LS(gcregDEColorMultiplyModesRegAddrs + index, 1);
-		*tail++ =
-			SETFIELD(0, AQDE_COLOR_MULTIPLY_MODES, SRC_PREMULTIPLY, bva.src_premul_src_alpha) |
-			SETFIELD(0, AQDE_COLOR_MULTIPLY_MODES, DST_PREMULTIPLY, bva.dst_premul_dst_alpha) |
-			SETFIELD(0, AQDE_COLOR_MULTIPLY_MODES, SRC_GLOBAL_PREMULTIPLY, bva.src_premul_global_mode) |
-			SETFIELD(0, AQDE_COLOR_MULTIPLY_MODES, DST_DEMULTIPLY, bva.dst_demul_dst_alpha);
+	if (dstmap != NULL) {
+		unmap_bverror = schedule_unmap(batch, bltparams->dstdesc);
+		if ((unmap_bverror != BVERR_NONE) && (bverror == BVERR_NONE)) {
+			bltparams->errdesc = gccontext.bverrorstr;
+			bverror = unmap_bverror;
+		}
+	}
+
+	return bverror;
+}
+
+static enum bverror do_filter(struct bvbltparams *bltparams,
+				struct gcbatch *batch)
+{
+	enum bverror bverror;
+	BVSETBLTERROR(BVERR_UNK, "FIXME/TODO");
+	return bverror;
+}
+
+/*******************************************************************************
+ * Library constructor and destructor.
+ */
 
-		index += 1;
+void bv_init(void)
+{
+}
+
+void bv_exit(void)
+{
+	struct bvbuffmap *bufmap;
+	struct gcschedunmap *bufunmap;
+	struct gcbuffer *buffer;
+	struct gcfixup *fixup;
+	struct gcvacbatch *batch;
+
+	while (gccontext.vac_buffmap != NULL) {
+		bufmap = gccontext.vac_buffmap;
+		gccontext.vac_buffmap = bufmap->nextmap;
+		gcfree(bufmap);
 	}
 
-	if (index == 0) {
-		fprintf(stderr, "%s(%d): no source specified\n",
-			__FUNCTION__, __LINE__);
-		fflush(stderr);
-		res = BVERR_UNK;
-		goto exit;
+	while (gccontext.vac_unmap != NULL) {
+		bufunmap = gccontext.vac_unmap;
+		gccontext.vac_unmap = bufunmap->next;
+		gcfree(bufunmap);
 	}
 
-	if (bltparams->dstdesc->map == NULL) {
-		res = bv_map(bltparams->dstdesc);
-		if (res != 0)
-			goto exit;
-		unmap_dest = 1;
+	while (gccontext.vac_buffers != NULL) {
+		buffer = gccontext.vac_buffers;
+		gccontext.vac_buffers = buffer->next;
+		gcfree(buffer);
+	}
+
+	while (gccontext.vac_fixups != NULL) {
+		fixup = gccontext.vac_fixups;
+		gccontext.vac_fixups = fixup->next;
+		gcfree(fixup);
 	}
 
-	*tail++ = LS(AQDEDestAddressRegAddrs, 1);
-	*tail++ = (uint32_t) bltparams->dstdesc->map;
-	blt.offset[k++] = tail - head;
-
-	*tail++ = LS(AQDEDestStrideRegAddrs, 1);
-	*tail++ = destgeom->virtstride;
-
-	*tail++ = LS(AQDEDestRotationConfigRegAddrs, 1);
-	*tail++ =
-		CONFIG_DEST_ROT_MODE(NORMAL) |
-		CONFIG_DEST_ROT_WIDTH(destgeom->width);
-
-	*tail++ = LS(AQDEDestConfigRegAddrs, 1);
-	*tail++ =
-		((index == 1)
-			? CONFIG_DEST_CMD(BIT_BLT)
-			: CONFIG_DEST_CMD(MULTI_SOURCE_BLT)) |
-		CONFIG_DEST_SWIZZLE(dst_swizzle) |
-		CONFIG_DEST_FMT(dst_format);
-
-	*tail++ = LS((AQDEDstRotationHeightRegAddrs), 1);
-	*tail++ = destgeom->height;
-
-	*tail++ = LS(AQDEClipTopLeftRegAddrs, 1);
-	*tail++ = CONFIG_CLIP_LFTTOP(l, t);
-	*tail++ = LS(AQDEClipBottomRightRegAddrs, 1);
-	*tail++ = CONFIG_CLIP_RHTBTM(r, b);
-
-	if (index > 1 ) {
-		*tail++ = LS(gcregDEMultiSourceRegAddrs, 1);
-		*tail++ = CONFIG_MLTSRC_CTRL(index - 1);
+	while (gccontext.vac_batches != NULL) {
+		batch = gccontext.vac_batches;
+		gccontext.vac_batches = batch->next;
+		gcfree(batch);
 	}
+}
+
+/*******************************************************************************
+ * Library API.
+ */
 
-	*tail++ = CONFIG_START_DE(1);
-	*tail++ = 0xC0FFEE;
-	*tail++ = CONFIG_START_DE_LFTTOP(l, t);
-	*tail++ = CONFIG_START_DE_RGHBTM(r, b);
+enum bverror bv_map(struct bvbuffdesc *buffdesc)
+{
+	enum bverror bverror;
+	struct bvbuffmap *bvbuffmap;
 
-	*tail++ = LS(AQFlushRegAddrs, 1);
-	*tail++ = CONFIG_PE2DCACHE_FLUSH();
+	/* FIXME/TODO: add check for initialization success. */
 
-	count = tail - head;
-	if (count > COUNTOF(buffer)) {
-		fprintf(stderr, "%s(%d): !!! buffer overrun (%d) !!!\n",
-			__FUNCTION__, __LINE__, count);
-		fflush(stderr);
-		res = BVERR_OOM;
+	if (buffdesc == NULL) {
+		BVSETERROR(BVERR_UNK, "invalid argument");
 		goto exit;
 	}
 
-	blt.cmdbuf = head;
-	blt.cmdlen = count * sizeof(uint32_t);
-
-	res = ioctl(fd, BLT, (uint32_t) &blt);
-	if (res != 0) {
-		fprintf(stderr, "%s(%d): ioctl failed\n", __FUNCTION__, __LINE__);
-		fflush(stderr);
-		res = BVERR_UNK;
+	if (buffdesc->structsize != STRUCTSIZE(buffdesc, map)) {
+		BVSETERROR(BVERR_BUFFERDESC_VERS, "argument has invalid size");
 		goto exit;
 	}
 
-	/* no errors, so exit */
-	res = BVERR_NONE;
+	bverror = do_map(buffdesc, 1, &bvbuffmap);
 
 exit:
-	for (i = 0; i < 2; i++)
-		if (unmap_src[i]) bv_unmap(srcdesc[i]);
-	if (unmap_dest) bv_unmap(bltparams->dstdesc);
-
-	return res;
+	return bverror;
 }
+EXPORT_SYMBOL(bv_map);
 
-enum bverror bv_blt(struct bvbltparams *bltparams)
+enum bverror bv_unmap(struct bvbuffdesc *buffdesc)
 {
-	int32_t res;
+	enum bverror bverror;
+	struct bvbuffmap *bvbuffmap;
+	struct bvbuffmapinfo *bvbuffmapinfo;
 
-	if (bltparams == NULL) {
-		res = BVERR_UNK;
+	/* FIXME/TODO: add check for initialization success. */
+
+	if (buffdesc == NULL) {
+		BVSETERROR(BVERR_UNK, "invalid argument");
 		goto exit;
 	}
 
-	if (bltparams->structsize != sizeof(struct bvbltparams)) {
-		res = BVERR_BUFFERDESC_VERS;
+	if (buffdesc->structsize != STRUCTSIZE(buffdesc, map)) {
+		BVSETERROR(BVERR_BUFFERDESC_VERS, "argument has invalid size");
 		goto exit;
 	}
 
-	if (bltparams->flags == BVFLAG_TILE_SRC1 ||
-			bltparams->flags == BVFLAG_TILE_SRC2 ||
-			bltparams->flags == BVFLAG_TILE_MASK) {
-		/* tiling */
-		res = BVERR_FLAGS;
-	} else if ((bltparams->flags == BVFLAG_ROP) ||
-		(bltparams->flags == BVFLAG_BLEND)) {
-		if ((bltparams->src1rect.width == bltparams->dstrect.width) &&
-				(bltparams->src1rect.height == bltparams->dstrect.height)) {
-			res = blit(bltparams);
-		} else if ((bltparams->src1rect.width == 1) &&
-				(bltparams->src1rect.height == 1)) {
-			res = fill(bltparams);
-		} else {
-			res = BVERR_FLAGS;
-		}
-	} else if (bltparams->flags == BVFLAG_FILTER) {
-		res = BVERR_FLAGS;
+	bvbuffmap = buffdesc->map;
+	if (bvbuffmap == NULL)
+		return BVERR_NONE;
+
+	if (bvbuffmap->structsize != STRUCTSIZE(bvbuffmap, nextmap)) {
+		BVSETERROR(BVERR_UNK, "invalid map structure size");
+		goto exit;
+	}
+
+	/* Not our mapping? */
+	if (bvbuffmap->bv_unmap != bv_unmap) {
+		bverror = bvbuffmap->bv_unmap(buffdesc);
+		goto exit;
+	}
+
+	/* Get the info structure. */
+	bvbuffmapinfo = (struct bvbuffmapinfo *) bvbuffmap->handle;
+
+	/* Are there any existing auto-mappings? */
+	if (bvbuffmapinfo->automap) {
+		/* Reset user mappings if any. */
+		bvbuffmapinfo->usermap = 0;
+
+		/* Are there mappings from alternative implementations? */
+		if (bvbuffmap->nextmap != NULL) {
+			/* Temporarily remove the record from the mapping
+			   list so that other implementations can proceeed. */
+			buffdesc->map = bvbuffmap->nextmap;
+
+			/* Call other implementations. */
+			bverror = bv_unmap(buffdesc);
+
+			/* Link the record back into the list. */
+			bvbuffmap->nextmap = buffdesc->map;
+			buffdesc->map = bvbuffmap;
+		} else
+			bverror = BVERR_NONE;
+
+	/* No auto-mappings, must be user mapping. */
 	} else {
-		/* error */
-		res = BVERR_FLAGS;
+		/* Unmap the buffer. */
+		bverror = do_unmap(buffdesc, 1);
+		if (bverror != BVERR_NONE)
+			goto exit;
+
+		/* Call other implementations. */
+		bverror = bv_unmap(buffdesc);
 	}
 
 exit:
-	return res;
+	return bverror;
 }
+EXPORT_SYMBOL(bv_unmap);
 
-enum bverror bv_unmap(struct bvbuffdesc *buffdesc)
+enum bverror bv_blt(struct bvbltparams *bltparams)
 {
-	int32_t res;
+	enum bverror bverror = BVERR_NONE;
+	struct gcalpha *gca = NULL;
+	struct gcalpha _gca;
+	unsigned int op, type;
+	unsigned int batchflags;
+	unsigned int batchexec = 0;
+	struct gcbatch *batch;
+	int src1used, src2used, maskused;
+	struct srcdesc srcdesc[2];
+	unsigned short rop, blend, format;
+	struct gccommit gccommit;
+	int srccount, res;
+
+	/* FIXME/TODO: add check for initialization success. */
+
+	/* Verify blt parameters structure. */
+	if (bltparams == NULL) {
+		BVSETERROR(BVERR_UNK,
+				"pointer to bvbltparams struct is expected");
+		goto exit;
+	}
 
-	if (buffdesc == NULL) {
-		res = BVERR_UNK;
+	if (bltparams->structsize != STRUCTSIZE(bltparams, callbackdata)) {
+		BVSETERROR(BVERR_BLTPARAMS_VERS, "argument has invalid size");
 		goto exit;
 	}
 
-	if (buffdesc->structsize != sizeof(struct bvbuffdesc)) {
-		res = BVERR_BUFFERDESC_VERS;
+	/* Reset the error message. */
+	bltparams->errdesc = NULL;
+
+	/* Verify the destination parameters structure. */
+	res = verify_surface(0, (union bvinbuff *) &bltparams->dstdesc,
+				bltparams->dstgeom, &bltparams->dstrect);
+	if (res != -1) {
+		BVSETBLTSURFERROR(res, g_destsurferr);
 		goto exit;
 	}
 
-	res = ioctl(fd, UMAP, buffdesc);
-	if ((res == -1) || (buffdesc->map == NULL)) {
-		res = BVERR_UNK;
+	/* Extract the operation flags. */
+	op = (bltparams->flags & BVFLAG_OP_MASK) >> BVFLAG_OP_SHIFT;
+	type = (bltparams->flags & BVFLAG_BATCH_MASK) >> BVFLAG_BATCH_SHIFT;
+
+	switch (type) {
+	case (BVFLAG_BATCH_NONE >> BVFLAG_BATCH_SHIFT):
+		GC_PRINT(GC_INFO_MSG " BVFLAG_BATCH_NONE\n",
+			__func__, __LINE__);
+		bverror = allocate_batch(&batch);
+		if (bverror != BVERR_NONE) {
+			bltparams->errdesc = gccontext.bverrorstr;
+			goto exit;
+		}
+
+		batchexec = 1;
+		batchflags = 0x7FFFFFFF;
+		break;
+
+	case (BVFLAG_BATCH_BEGIN >> BVFLAG_BATCH_SHIFT):
+		GC_PRINT(GC_INFO_MSG " BVFLAG_BATCH_BEGIN\n",
+			__func__, __LINE__);
+		bverror = allocate_batch(&batch);
+		if (bverror != BVERR_NONE) {
+			bltparams->errdesc = gccontext.bverrorstr;
+			goto exit;
+		}
+
+		bltparams->batch = (struct bvbatch *) batch;
+
+		batchexec = 0;
+		bltparams->batchflags =
+		batchflags = 0x7FFFFFFF;
+		break;
+
+	case (BVFLAG_BATCH_CONTINUE >> BVFLAG_BATCH_SHIFT):
+		GC_PRINT(GC_INFO_MSG " BVFLAG_BATCH_CONTINUE\n",
+			__func__, __LINE__);
+		batch = (struct gcbatch *) bltparams->batch;
+		if (batch == NULL) {
+			BVSETBLTERROR(BVERR_BATCH, "batch is not initialized");
+			goto exit;
+		}
+
+		if (batch->structsize != STRUCTSIZE(batch, unmap)) {
+			BVSETBLTERROR(BVERR_BATCH, "invalid batch");
+			goto exit;
+		}
+
+		batchexec = 0;
+		batchflags = bltparams->batchflags;
+		break;
+
+	case (BVFLAG_BATCH_END >> BVFLAG_BATCH_SHIFT):
+		GC_PRINT(GC_INFO_MSG " BVFLAG_BATCH_END\n",
+			__func__, __LINE__);
+		batch = (struct gcbatch *) bltparams->batch;
+		if (batch == NULL) {
+			BVSETBLTERROR(BVERR_BATCH, "batch is not initialized");
+			goto exit;
+		}
+
+		if (batch->structsize != STRUCTSIZE(batch, unmap)) {
+			BVSETBLTERROR(BVERR_BATCH, "invalid batch");
+			goto exit;
+		}
+
+		batchexec = 1;
+		batchflags = (bltparams->batchflags & BVBATCH_ENDNOP)
+			? 0
+			: bltparams->batchflags;
+		break;
+
+	default:
+		BVSETBLTERROR(BVERR_BATCH, "unrecognized batch type");
 		goto exit;
 	}
 
-	res = BVERR_NONE;
+	GC_PRINT(GC_INFO_MSG " batchflags=0x%08X\n",
+		__func__, __LINE__, batchflags);
+
+	if (batchflags != 0) {
+		switch (op) {
+		case (BVFLAG_ROP >> BVFLAG_OP_SHIFT):
+			GC_PRINT(GC_INFO_MSG " BVFLAG_ROP\n",
+				__func__, __LINE__);
+			rop = bltparams->op.rop;
+			src1used = ((rop & 0xCCCC) >> 2)
+					^  (rop & 0x3333);
+			src2used = ((rop & 0xF0F0) >> 4)
+					^  (rop & 0x0F0F);
+			maskused = ((rop & 0xFF00) >> 8)
+					^  (rop & 0x00FF);
+			break;
+
+		case (BVFLAG_BLEND >> BVFLAG_OP_SHIFT):
+			GC_PRINT(GC_INFO_MSG " BVFLAG_BLEND\n",
+				__func__, __LINE__);
+			blend = bltparams->op.blend;
+			format = (blend & BVBLENDDEF_FORMAT_MASK)
+				>> BVBLENDDEF_FORMAT_SHIFT;
+
+			bverror = parse_blend(bltparams,
+						bltparams->op.blend, &_gca);
+			if (bverror != BVERR_NONE)
+				goto exit;
+
+			gca = &_gca;
+
+			/* FIXME/TODO: logic here is incorrect */
+			switch (format) {
+			case (BVBLENDDEF_FORMAT_CLASSIC
+				>> BVBLENDDEF_FORMAT_SHIFT):
+				src1used
+					= gca->dst_config->destuse
+					| gca->src_config->destuse;
+				src2used
+					= gca->dst_config->srcuse
+					| gca->src_config->srcuse;
+				maskused
+					= blend & BVBLENDDEF_REMOTE;
+				break;
+
+			default:
+				BVSETBLTERROR(BVERR_BLEND,
+						"unrecognized blend format");
+				goto exit;
+			}
+			break;
+
+		case (BVFLAG_FILTER >> BVFLAG_OP_SHIFT):
+			GC_PRINT(GC_INFO_MSG " BVFLAG_FILTER\n",
+				__func__, __LINE__);
+			BVSETBLTERROR(BVERR_UNK, "FIXME/TODO");
+			goto exit;
+
+		default:
+			BVSETBLTERROR(BVERR_OP, "unrecognized operation");
+			goto exit;
+		}
+
+		srccount = 0;
+
+		/* Verify the src1 parameters structure. */
+		if (src1used) {
+			GC_PRINT(GC_INFO_MSG " src1used\n",
+				__func__, __LINE__);
+
+			res = verify_surface(
+				bltparams->flags & BVBATCH_TILE_SRC1,
+				&bltparams->src1, bltparams->src1geom,
+				&bltparams->src1rect);
+			if (res != -1) {
+				BVSETBLTSURFERROR(res, g_src1surferr);
+				goto exit;
+			}
+
+			/* Same as the destination? */
+			if ((bltparams->src1.desc->virtaddr
+				== bltparams->dstdesc->virtaddr) &&
+				EQ_ORIGIN(bltparams->src1rect,
+						bltparams->dstrect) &&
+				EQ_SIZE(bltparams->src1rect,
+						bltparams->dstrect)) {
+				GC_PRINT(GC_INFO_MSG
+					" src1 is the same as dst\n",
+					__func__, __LINE__);
+			} else {
+				srcdesc[srccount].index = 0;
+				srcdesc[srccount].buf = bltparams->src1;
+				srcdesc[srccount].geom = bltparams->src1geom;
+				srcdesc[srccount].rect = &bltparams->src1rect;
+
+				srccount += 1;
+			}
+		}
+
+		/* Verify the src2 parameters structure. */
+		if (src2used) {
+			GC_PRINT(GC_INFO_MSG " src2used\n",
+				__func__, __LINE__);
+
+			res = verify_surface(
+				bltparams->flags & BVBATCH_TILE_SRC2,
+				&bltparams->src2, bltparams->src2geom,
+				&bltparams->src2rect);
+			if (res != -1) {
+				BVSETBLTSURFERROR(res, g_src2surferr);
+				goto exit;
+			}
+
+			/* Same as the destination? */
+			if ((bltparams->src2.desc->virtaddr
+				== bltparams->dstdesc->virtaddr) &&
+				EQ_ORIGIN(bltparams->src2rect,
+						bltparams->dstrect) &&
+				EQ_SIZE(bltparams->src2rect,
+						bltparams->dstrect)) {
+				GC_PRINT(GC_INFO_MSG
+					" src2 is the same as dst\n",
+					__func__, __LINE__);
+			} else {
+				srcdesc[srccount].index = 1;
+				srcdesc[srccount].buf = bltparams->src2;
+				srcdesc[srccount].geom = bltparams->src2geom;
+				srcdesc[srccount].rect = &bltparams->src2rect;
+
+				srccount += 1;
+			}
+		}
+
+		/* Verify the mask parameters structure. */
+		if (maskused) {
+			GC_PRINT(GC_INFO_MSG " maskused\n",
+				__func__, __LINE__);
+			res = verify_surface(
+				bltparams->flags & BVBATCH_TILE_MASK,
+				&bltparams->mask, bltparams->maskgeom,
+				&bltparams->maskrect);
+			if (res != -1) {
+				BVSETBLTSURFERROR(res, g_masksurferr);
+				goto exit;
+			}
+
+			BVSETERROR(BVERR_UNK, "FIXME/TODO");
+			goto exit;
+		}
+
+		GC_PRINT(GC_INFO_MSG " srccount = %d\n",
+			__func__, __LINE__, srccount);
+
+		switch (srccount) {
+		case 0:
+			bverror = do_blit(bltparams, batch, NULL, 0, gca);
+			break;
+
+		case 1:
+			if (EQ_SIZE((*srcdesc[0].rect), bltparams->dstrect))
+				bverror = do_blit(bltparams, batch,
+						srcdesc, 1, gca);
+			else if ((srcdesc[0].rect->width == 1) &&
+				(srcdesc[0].rect->height == 1))
+				bverror = do_fill(bltparams, batch, srcdesc);
+			else
+				bverror = do_filter(bltparams, batch);
+			break;
+
+		case 2:
+			if (EQ_SIZE((*srcdesc[0].rect), bltparams->dstrect))
+				if (EQ_SIZE((*srcdesc[1].rect),
+					bltparams->dstrect))
+					bverror = do_blit(bltparams, batch,
+							srcdesc, 2, gca);
+				else
+					BVSETBLTERROR(
+						BVERR_UNK, "FIXME/TODO");
+			else
+				if (EQ_SIZE((*srcdesc[1].rect),
+					bltparams->dstrect))
+					BVSETBLTERROR(
+						BVERR_UNK, "FIXME/TODO");
+				else
+					BVSETBLTERROR(
+						BVERR_UNK, "FIXME/TODO");
+		}
+	}
+
+	if (batchexec) {
+		/* Finalize the current operation. */
+		bverror = batch->batchend(bltparams, batch);
+		if (bverror != BVERR_NONE)
+			goto exit;
+
+#if GC_DUMP
+		dumpbuffer(batch);
+#endif
+
+		gccommit.gcerror = GCERR_NONE;
+		gccommit.buffer = batch->bufhead;
+
+		gc_commit_wrapper(&gccommit);
+		if (gccommit.gcerror != GCERR_NONE) {
+			BVSETBLTERRORARG(BVERR_UNK,
+					"blit error occured (0x%08X)",
+					gccommit.gcerror);
+			goto exit;
+		}
+	}
 
 exit:
-	return res;
+	if ((batch != NULL) && batchexec) {
+		process_scheduled_unmap(batch);
+		free_batch(batch);
+		bltparams->batch = NULL;
+	}
+
+	return bverror;
 }
+EXPORT_SYMBOL(bv_blt);
diff --git a/gcbv/gcerror.h b/gcbv/gcerror.h
new file mode 100644
index 0000000..88309a8
--- /dev/null
+++ b/gcbv/gcerror.h
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2011, Texas Instruments, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Texas Instruments, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL TEXAS INSTRUMENTS, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef GCERROR_H
+#define GCERROR_H
+
+#define GCERR_SETGRP(error, group) \
+( \
+	(enum gcerror) \
+	((error & GCERR_GENERIC_MASK) | group) \
+)
+
+#define GCERR_GENERIC(error) \
+( \
+	(error & GCERR_GENERIC_MASK) << GCERR_GENERIC_SHIFT \
+)
+
+#define GCERR_GROUP(error) \
+( \
+	(error & GCERR_GROUP_MASK) << GCERR_GROUP_SHIFT \
+)
+
+enum gcerror {
+	/***********************************************************************
+	** No error / success.
+	*/
+	GCERR_NONE = 0,
+
+	/***********************************************************************
+	** Error code zones.
+	*/
+
+	/* Generic error code zone. These errors inform of the low level
+	   reason of the faulure, but don't carry information about which
+	   logical part of the code generated the error. */
+	GCERR_GENERIC_SIZE = 12,
+	GCERR_GENERIC_SHIFT = 0,
+	GCERR_GENERIC_MASK
+		= ((1 << GCERR_GENERIC_SIZE) - 1) << GCERR_GENERIC_SHIFT,
+
+	/* Group error code zone. These errors inform about the logical part
+	   of the code where the error occurred. */
+	GCERR_GROUP_SIZE = (32 - GCERR_GENERIC_SIZE),
+	GCERR_GROUP_SHIFT = GCERR_GENERIC_SIZE,
+	GCERR_GROUP_MASK
+		= ((1 << GCERR_GROUP_SIZE) - 1) << GCERR_GROUP_SHIFT,
+
+	/***********************************************************************
+	** Generic zone errors.
+	*/
+
+	GCERR_OODM			/* Out of dynamic memory. */
+	= GCERR_GENERIC(1),
+
+	GCERR_OOPM			/* Out of paged memory. */
+	= GCERR_GENERIC(2),
+
+	GCERR_PMMAP			/* Paged memory mapping. */
+	= GCERR_GENERIC(3),
+
+	GCERR_USER_READ			/* Reading user input. */
+	= GCERR_GENERIC(4),
+
+	GCERR_USER_WRITE		/* Writing user output. */
+	= GCERR_GENERIC(5),
+
+	GCERR_INTERRUPTED		/* Interrupted by a signal. */
+	= GCERR_GENERIC(6),
+
+	GCERR_TIMEOUT			/* Timeout. */
+	= GCERR_GENERIC(7),
+
+	GCERR_NOT_FOUND			/* Data/entry not found. */
+	= GCERR_GENERIC(8),
+
+	GCERR_IOCTL			/* IOCTL failed. */
+	= GCERR_GENERIC(9),
+
+	/***********************************************************************
+	** Group zone errors.
+	*/
+
+	/**** Context errors. */
+	GCERR_CTX_ALLOC			/* Context allocation. */
+	= GCERR_GROUP(0x01000),
+
+	GCERR_CTX_CHANGE		/* Lock/unlock error. */
+	= GCERR_GROUP(0x01010),
+
+	GCERR_CTX_NULL			/* Context not set. */
+	= GCERR_GROUP(0x01020),
+
+	/**** Command queue errors. */
+	GCERR_CMD_ALLOC			/* Buffer allocation. */
+	= GCERR_GROUP(0x02000),
+
+	/**** MMU errors. */
+	GCERR_MMU_CTXT_BAD		/* Invalid context. */
+	= GCERR_GROUP(0x03000),
+
+	GCERR_MMU_MTLB_ALLOC		/* MTLB allocation. */
+	= GCERR_GROUP(0x03010),
+
+	GCERR_MMU_MTLB_SET		/* MTLB setting. */
+	= GCERR_GROUP(0x03020),
+
+	GCERR_MMU_STLB_ALLOC		/* STLB allocation. */
+	= GCERR_GROUP(0x03030),
+
+	GCERR_MMU_STLBIDX_ALLOC		/* STLB index allocation. */
+	= GCERR_GROUP(0x03040),
+
+	GCERR_MMU_ARENA_ALLOC		/* Vacant arena allocation. */
+	= GCERR_GROUP(0x03050),
+
+	GCERR_MMU_OOM			/* No available arenas to allocate. */
+	= GCERR_GROUP(0x03060),
+
+	GCERR_MMU_SAFE_ALLOC		/* Safe zone allocation. */
+	= GCERR_GROUP(0x03070),
+
+	GCERR_MMU_INIT			/* MMU initialization. */
+	= GCERR_GROUP(0x03080),
+
+	GCERR_MMU_ARG			/* Invalid argument. */
+	= GCERR_GROUP(0x03090),
+
+	GCERR_MMU_CLIENT		/* Client initialization. */
+	= GCERR_GROUP(0x030A0),
+
+	GCERR_MMU_BUFFER_BAD		/* Invalid buffer to map. */
+	= GCERR_GROUP(0x030B0),
+
+	GCERR_MMU_PAGE_BAD		/* Bad page within the buffer. */
+	= GCERR_GROUP(0x030C0),
+
+	GCERR_MMU_DESC_ALLOC		/* Bad page within the buffer. */
+	= GCERR_GROUP(0x030D0),
+
+	GCERR_MMU_PHYS_ALLOC		/* Bad page within the buffer. */
+	= GCERR_GROUP(0x030E0),
+
+	GCERR_MMU_OFFSET		/* Bad buffer offset. */
+	= GCERR_GROUP(0x030F0),
+
+	/**** Power management. */
+	GCERR_POWER_MODE		/* Invlalid power mode requested. */
+	= GCERR_GROUP(0x04000),
+
+	GCERR_POWER_CLOCK_ON		/* Failed to enable clock. */
+	= GCERR_GROUP(0x04010),
+
+	GCERR_POWER_IRQ_ON		/* Failed to install IRQ handler. */
+	= GCERR_GROUP(0x04020),
+
+	/**** GCIOCTL module errors. */
+	GCERR_IOCTL_CTX_ALLOC		/* Context wrapper allocation. */
+	= GCERR_GROUP(0x11000),
+
+	GCERR_IOCTL_BUF_ALLOC		/* Command buffer allocation. */
+	= GCERR_GROUP(0x11010),
+
+	GCERR_IOCTL_FIXUP_ALLOC		/* Fixup buffer allocation. */
+	= GCERR_GROUP(0x11020),
+};
+
+#endif
diff --git a/gcbv/gcioctl.h b/gcbv/gcioctl.h
new file mode 100644
index 0000000..55092a9
--- /dev/null
+++ b/gcbv/gcioctl.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2011, Texas Instruments, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Texas Instruments, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL TEXAS INSTRUMENTS, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef GCIOCTL_H
+#define GCIOCTL_H
+
+#include "gcerror.h"
+#include <bverror.h>
+
+/* IOCTL parameters. */
+#define GCIOCTL_TYPE 0x5D
+#define GCIOCTL_BASE 0x5D
+
+/*******************************************************************************
+ * Commit API entry.
+ */
+
+struct gccommit;
+struct gcbuffer;
+struct gcfixup;
+
+#define GCIOCTL_COMMIT _IOWR(GCIOCTL_TYPE, GCIOCTL_BASE + 0x10, struct gccommit)
+
+/* Commit header; contains pointers to the head and the tail of a linked list
+   of command buffers to execute. */
+struct gccommit {
+	enum gcerror gcerror;		/* Return status code. */
+	struct gcbuffer *buffer;	/* Command buffer list. */
+};
+
+/* Command buffer header. */
+#define GC_BUFFER_SIZE 81920
+struct gcbuffer {
+	struct gcfixup *fixuphead;	/* Address fixup list. */
+	struct gcfixup *fixuptail;
+
+	unsigned int pixelcount;	/* Number of pixels to be rendered. */
+
+	unsigned int *head;		/* Pointers to the head and tail */
+	unsigned int *tail;		/* of the command buffer. */
+
+	unsigned int available;		/* Number of bytes available in the
+					   buffer. */
+	struct gcbuffer *next;		/* Pointer to the next commmand
+					   buffer. */
+};
+
+/* Fixup entry. */
+struct gcfixupentry {
+	unsigned int dataoffset;	/* Offset into the commmand buffer
+					   where fixup is to be performed. */
+	unsigned int surfoffset;	/* Offset to be added to the base
+					   address of the surface. */
+};
+
+/* Address fixup array. */
+#define GC_FIXUP_MAX 1024
+struct gcfixup {
+	struct gcfixup *next;
+	unsigned int count;
+	struct gcfixupentry fixup[GC_FIXUP_MAX];
+};
+
+/*******************************************************************************
+ * Map/unmap API entries.
+ */
+
+struct gcmap;
+
+#define GCIOCTL_MAP   _IOWR(GCIOCTL_TYPE, GCIOCTL_BASE + 0x20, struct gcmap)
+#define GCIOCTL_UNMAP _IOWR(GCIOCTL_TYPE, GCIOCTL_BASE + 0x21, struct gcmap)
+
+struct gcmap {
+	enum gcerror gcerror;		/* Return status code. */
+	unsigned int handle;		/* Mapped handle of the buffer. */
+
+	void *logical;			/* Pointer to the buffer. */
+	unsigned int size;		/* Size of the buffer. */
+};
+
+/*******************************************************************************
+ * BLTsville: blit API entry.
+ */
+
+struct gcbvblt;
+
+#define GCIOCTL_BVBLT _IOWR(GCIOCTL_TYPE, GCIOCTL_BASE + 0x30, struct gcbvblt)
+
+struct gcbvblt {
+	enum bverror bverror;		/* Return status code. */
+	struct bvbltparams *bltparams;	/* Blit parameters. */
+	char *errdesc;			/* Blit error message. */
+	int errdesclen;			/* Maximum length of the error
+					   message. */
+};
+
+/*******************************************************************************
+ * BLTsville: map/unmap API entries.
+ */
+
+struct gcbvmap;
+
+#define GCIOCTL_BVMAP   _IOWR(GCIOCTL_TYPE, GCIOCTL_BASE + 0x40, struct gcbvmap)
+#define GCIOCTL_BVUNMAP _IOWR(GCIOCTL_TYPE, GCIOCTL_BASE + 0x41, struct gcbvmap)
+
+struct gcbvmap {
+	enum bverror bverror;		/* Return status code. */
+	struct bvbuffdesc *buffdesc;	/* Surface descriptor. */
+};
+
+#endif
diff --git a/gcbv/gcmain.c b/gcbv/gcmain.c
new file mode 100644
index 0000000..87dcab5
--- /dev/null
+++ b/gcbv/gcmain.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2011, Texas Instruments, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Texas Instruments, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL TEXAS INSTRUMENTS, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <gcx.h>
+#include <gc2d.h>
+#include "gcmain.h"
+
+#ifndef GC_DUMP
+#	define GC_DUMP 0
+#endif
+
+#if GC_DUMP
+#	define GC_PRINT gcdump
+#else
+#	define GC_PRINT(...)
+#endif
+
+static int g_fd;	/* Open device file descriptor. */
+
+/*******************************************************************************
+ * IOCTL wrappers.
+ */
+
+#if GC_DUMP
+#	define GC_IOCTL(result, id, data) \
+	{ \
+		sleep(1); \
+		result = ioctl(g_fd, id, data); \
+	}
+#else
+#	define GC_IOCTL(result, id, data) \
+	{ \
+		result = ioctl(g_fd, id, data); \
+	}
+#endif
+
+void gc_map_wrapper(struct gcmap *gcmap)
+{
+	int result;
+	GC_IOCTL(result, GCIOCTL_MAP, gcmap);
+	if (result != 0) {
+		GC_PRINT(GC_ERR_MSG "ioctl failed (%d)\n",
+			__func__, __LINE__, result);
+		gcmap->gcerror = GCERR_IOCTL;
+	}
+}
+
+void gc_unmap_wrapper(struct gcmap *gcmap)
+{
+	int result;
+	GC_IOCTL(result, GCIOCTL_UNMAP, gcmap);
+	if (result != 0) {
+		GC_PRINT(GC_ERR_MSG "ioctl failed (%d)\n",
+			__func__, __LINE__, result);
+		gcmap->gcerror = GCERR_IOCTL;
+	}
+}
+
+void gc_commit_wrapper(struct gccommit *gccommit)
+{
+	int result;
+	GC_IOCTL(result, GCIOCTL_COMMIT, gccommit);
+	if (result != 0) {
+		GC_PRINT(GC_ERR_MSG "ioctl failed (%d)\n",
+			__func__, __LINE__, result);
+		gccommit->gcerror = GCERR_IOCTL;
+	}
+}
+
+/*******************************************************************************
+ * Convert floating point in 0..1 range to an 8-bit value in range 0..255.
+ */
+
+union gcfp {
+	struct {
+		unsigned int mantissa:23;
+		unsigned int exponent:8;
+		unsigned int sign:1;
+	} comp;
+
+	float value;
+};
+
+unsigned char gcfp2norm8(float value)
+{
+	union gcfp gcfp;
+	int exponent;
+	unsigned int mantissa;
+	int shift;
+
+	/* Get access to components. */
+	gcfp.value = value;
+
+	/* Clamp negatives. */
+	if (gcfp.comp.sign)
+		return 0;
+
+	/* Get unbiased exponent. */
+	exponent = (int) gcfp.comp.exponent - 127;
+
+	/* Clamp if too large. */
+	if (exponent >= 0)
+		return 255;
+
+	/* Clamp if too small. */
+	if (exponent < -8)
+		return 0;
+
+	/* Determine the shift value. */
+	shift = (23 - 8) - exponent;
+
+	/* Compute the mantissa. */
+	mantissa = (gcfp.comp.mantissa | 0x00800000) >> shift;
+
+	/* Normalize. */
+	mantissa = (mantissa * 255) >> 8;
+
+	return (unsigned char) mantissa;
+}
+
+/*******************************************************************************
+ * Device init/cleanup.
+ */
+
+extern void dev_init(void) __attribute__((constructor));
+extern void dev_init(void)
+{
+	GC_PRINT(GC_INFO_MSG "\n", __func__, __LINE__);
+
+	g_fd = open("/dev/gcioctl", O_RDWR);
+	if (g_fd == -1) {
+		GC_PRINT(GC_ERR_MSG " failed to open device (%d)\n",
+			__func__, __LINE__, errno);
+		goto exit;
+	}
+
+	bv_init();
+
+exit:;
+}
+
+extern void dev_exit(void) __attribute__((destructor));
+extern void dev_exit(void)
+{
+	GC_PRINT(GC_INFO_MSG "\n", __func__, __LINE__);
+
+	bv_exit();
+
+	if (g_fd != 0) {
+		close(g_fd);
+		g_fd = 0;
+	}
+}
diff --git a/gcbv/gcmain.h b/gcbv/gcmain.h
index 14410f1..3c69701 100644
--- a/gcbv/gcmain.h
+++ b/gcbv/gcmain.h
@@ -25,13 +25,51 @@
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef BV_H
-#define BV_H
+#ifndef GCMAIN_H
+#define GCMAIN_H
 
-#include "bltsville.h"
+#include <stdio.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <sys/ioctl.h>
+#include "gcioctl.h"
 
-enum bverror bv_map(struct bvbuffdesc *buffdesc);
-enum bverror bv_blt(struct bvbltparams *bltparams);
-enum bverror bv_unmap(struct bvbuffdesc *buffdesc);
+#define DEV_NAME	"gc2dusr"
+
+/*******************************************************************************
+ * Miscellaneous macros.
+ */
+
+#define gcalloc(type, size) \
+	(type *) malloc(size)
+
+#define gcfree(ptr) \
+	free(ptr)
+
+#define gcdump fprintf
+
+#define EXPORT_SYMBOL(sym)
+
+/*******************************************************************************
+ * IOCTL wrappers.
+ */
+
+void gc_map_wrapper(struct gcmap *gcmap);
+void gc_unmap_wrapper(struct gcmap *gcmap);
+void gc_commit_wrapper(struct gccommit *gccommit);
+
+/*******************************************************************************
+ * Floating point conversions.
+ */
+
+unsigned char gcfp2norm8(float value);
+
+/*******************************************************************************
+ * BLTsville initialization/cleanup.
+ */
+
+void bv_init(void);
+void bv_exit(void);
 
 #endif
diff --git a/gcbv/gcreg.h b/gcbv/gcreg.h
new file mode 100644
index 0000000..803cfb6
--- /dev/null
+++ b/gcbv/gcreg.h
@@ -0,0 +1,8340 @@
+/*
+ * Copyright (c) 2011, Vivante Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Vivante Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL VIVANTE CORPORATON BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __gcreg_h
+#define __gcreg_h
+
+/*******************************************************************************
+** Register access macros.
+*/
+
+#define __GCSTART(reg_field) \
+( \
+	0 ? reg_field \
+)
+
+#define __GCEND(reg_field) \
+( \
+	1 ? reg_field \
+)
+
+#define __GCGETSIZE(reg_field) \
+( \
+	__GCEND(reg_field) - __GCSTART(reg_field) + 1 \
+)
+
+#define __GCALIGN(data, reg_field) \
+( \
+	((unsigned int) (data)) << __GCSTART(reg_field) \
+)
+
+#define __GCMASK(reg_field) \
+	((__GCGETSIZE(reg_field) == 32) \
+		?  ~0U \
+		: (unsigned int) (~(~0UL << __GCGETSIZE(reg_field))))
+
+#define SETFIELDVAL(data, reg, field, value) \
+( \
+	(((unsigned int) (data)) \
+		& ~__GCALIGN(__GCMASK(reg##_##field), reg##_##field)) \
+		|  __GCALIGN(reg##_##field##_##value \
+			&  __GCMASK(reg##_##field), reg##_##field) \
+)
+
+#define SETFIELD(data, reg, field, value) \
+( \
+	(((unsigned int) (data)) \
+		& ~__GCALIGN(__GCMASK(reg##_##field), reg##_##field)) \
+		|  __GCALIGN((unsigned int) (value) \
+			&  __GCMASK(reg##_##field), reg##_##field) \
+)
+
+#define GETFIELD(data, reg, field) \
+( \
+	((((unsigned int) (data)) >> __GCSTART(reg##_##field)) \
+		& __GCMASK(reg##_##field)) \
+)
+
+#define REGVALUE(reg, field, val) \
+( \
+	reg##_##field##_##val \
+)
+
+/*******************************************************************************
+** Register gcregHiClockControl
+*/
+
+#define GCREG_HI_CLOCK_CONTROL_Address                                   0x00000
+#define GCREG_HI_CLOCK_CONTROL_MSB                                            15
+#define GCREG_HI_CLOCK_CONTROL_LSB                                             0
+#define GCREG_HI_CLOCK_CONTROL_BLK                                             0
+#define GCREG_HI_CLOCK_CONTROL_Count                                           1
+#define GCREG_HI_CLOCK_CONTROL_FieldMask                              0x000A17FE
+#define GCREG_HI_CLOCK_CONTROL_ReadMask                               0x000A17FE
+#define GCREG_HI_CLOCK_CONTROL_WriteMask                              0x000817FE
+#define GCREG_HI_CLOCK_CONTROL_ResetValue                             0x00000100
+
+/* Disable 3D clock. */
+#define GCREG_HI_CLOCK_CONTROL_CLK3D_DIS                                   0 : 0
+#define GCREG_HI_CLOCK_CONTROL_CLK3D_DIS_End                                   0
+#define GCREG_HI_CLOCK_CONTROL_CLK3D_DIS_Start                                 0
+#define GCREG_HI_CLOCK_CONTROL_CLK3D_DIS_Type                                U01
+
+/* Disable 2D clock. */
+#define GCREG_HI_CLOCK_CONTROL_CLK2D_DIS                                   1 : 1
+#define GCREG_HI_CLOCK_CONTROL_CLK2D_DIS_End                                   1
+#define GCREG_HI_CLOCK_CONTROL_CLK2D_DIS_Start                                 1
+#define GCREG_HI_CLOCK_CONTROL_CLK2D_DIS_Type                                U01
+
+#define GCREG_HI_CLOCK_CONTROL_FSCALE_VAL                                  8 : 2
+#define GCREG_HI_CLOCK_CONTROL_FSCALE_VAL_End                                  8
+#define GCREG_HI_CLOCK_CONTROL_FSCALE_VAL_Start                                2
+#define GCREG_HI_CLOCK_CONTROL_FSCALE_VAL_Type                               U07
+
+#define GCREG_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD                             9 : 9
+#define GCREG_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD_End                             9
+#define GCREG_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD_Start                           9
+#define GCREG_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD_Type                          U01
+
+/* Disables clock gating for rams. */
+#define GCREG_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING                    10 : 10
+#define GCREG_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING_End                     10
+#define GCREG_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING_Start                   10
+#define GCREG_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING_Type                   U01
+
+/* Disable debug registers. If this bit is 1, debug regs are clock gated. */
+#define GCREG_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS                   11 : 11
+#define GCREG_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS_End                    11
+#define GCREG_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS_Start                  11
+#define GCREG_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS_Type                  U01
+
+/* Soft resets the IP. */
+#define GCREG_HI_CLOCK_CONTROL_SOFT_RESET                                12 : 12
+#define GCREG_HI_CLOCK_CONTROL_SOFT_RESET_End                                 12
+#define GCREG_HI_CLOCK_CONTROL_SOFT_RESET_Start                               12
+#define GCREG_HI_CLOCK_CONTROL_SOFT_RESET_Type                               U01
+
+/* 3D pipe is idle. */
+#define GCREG_HI_CLOCK_CONTROL_IDLE_3D                                   16 : 16
+#define GCREG_HI_CLOCK_CONTROL_IDLE_3D_End                                    16
+#define GCREG_HI_CLOCK_CONTROL_IDLE_3D_Start                                  16
+#define GCREG_HI_CLOCK_CONTROL_IDLE_3D_Type                                  U01
+
+/* 2D pipe is idle. */
+#define GCREG_HI_CLOCK_CONTROL_IDLE_2D                                   17 : 17
+#define GCREG_HI_CLOCK_CONTROL_IDLE_2D_End                                    17
+#define GCREG_HI_CLOCK_CONTROL_IDLE_2D_Start                                  17
+#define GCREG_HI_CLOCK_CONTROL_IDLE_2D_Type                                  U01
+
+/* VG pipe is idle. */
+#define GCREG_HI_CLOCK_CONTROL_IDLE_VG                                   18 : 18
+#define GCREG_HI_CLOCK_CONTROL_IDLE_VG_End                                    18
+#define GCREG_HI_CLOCK_CONTROL_IDLE_VG_Start                                  18
+#define GCREG_HI_CLOCK_CONTROL_IDLE_VG_Type                                  U01
+
+/* Isolate GPU bit */
+#define GCREG_HI_CLOCK_CONTROL_ISOLATE_GPU                               19 : 19
+#define GCREG_HI_CLOCK_CONTROL_ISOLATE_GPU_End                                19
+#define GCREG_HI_CLOCK_CONTROL_ISOLATE_GPU_Start                              19
+#define GCREG_HI_CLOCK_CONTROL_ISOLATE_GPU_Type                              U01
+
+union gcclockcontrol {
+	struct {
+		/* gcregHiClockControl:
+			GCREG_HI_CLOCK_CONTROL_CLK3D_DIS */
+		unsigned int disable3d:1;
+
+		/* gcregHiClockControl:
+			GCREG_HI_CLOCK_CONTROL_CLK2D_DIS */
+		unsigned int disable2d:1;
+
+		/* gcregHiClockControl:
+			GCREG_HI_CLOCK_CONTROL_FSCALE_VAL */
+		unsigned int pulsecount:7;
+
+		/* gcregHiClockControl:
+			GCREG_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD */
+		unsigned int pulseset:1;
+
+		/* gcregHiClockControl:
+			GCREG_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING */
+		unsigned int ramgate:1;
+
+		/* gcregHiClockControl:
+			GCREG_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS */
+		unsigned int disabledbg:1;
+
+		/* gcregHiClockControl:
+			GCREG_HI_CLOCK_CONTROL_SOFT_RESET */
+		unsigned int reset:1;
+
+		/* gcregHiClockControl:
+			reserved */
+		unsigned int _reserved_13_15:3;
+
+		/* gcregHiClockControl:
+			GCREG_HI_CLOCK_CONTROL_IDLE_3D */
+		unsigned int idle3d:1;
+
+		/* gcregHiClockControl:
+			GCREG_HI_CLOCK_CONTROL_IDLE_2D */
+		unsigned int idle2d:1;
+
+		/* gcregHiClockControl:
+			GCREG_HI_CLOCK_CONTROL_IDLE_VG */
+		unsigned int idlevg:1;
+
+		/* gcregHiClockControl:
+			GCREG_HI_CLOCK_CONTROL_ISOLATE_GPU */
+		unsigned int isolate:1;
+
+		/* gcregHiClockControl:
+			reserved */
+		unsigned int _reserved_20_31:12;
+	} reg;
+
+	unsigned int raw;
+};
+
+/*******************************************************************************
+** Register gcregHiIdle
+*/
+
+#define GCREG_HI_IDLE_Address                                            0x00004
+#define GCREG_HI_IDLE_MSB                                                     15
+#define GCREG_HI_IDLE_LSB                                                      0
+#define GCREG_HI_IDLE_BLK                                                      0
+#define GCREG_HI_IDLE_Count                                                    1
+#define GCREG_HI_IDLE_FieldMask                                       0x80000007
+#define GCREG_HI_IDLE_ReadMask                                        0x80000007
+#define GCREG_HI_IDLE_WriteMask                                       0x00000000
+#define GCREG_HI_IDLE_ResetValue                                      0x00000007
+
+/* FE is idle. */
+#define GCREG_HI_IDLE_IDLE_FE                                              0 : 0
+#define GCREG_HI_IDLE_IDLE_FE_End                                              0
+#define GCREG_HI_IDLE_IDLE_FE_Start                                            0
+#define GCREG_HI_IDLE_IDLE_FE_Type                                           U01
+
+/* DE is idle. */
+#define GCREG_HI_IDLE_IDLE_DE                                              1 : 1
+#define GCREG_HI_IDLE_IDLE_DE_End                                              1
+#define GCREG_HI_IDLE_IDLE_DE_Start                                            1
+#define GCREG_HI_IDLE_IDLE_DE_Type                                           U01
+
+/* PE is idle. */
+#define GCREG_HI_IDLE_IDLE_PE                                              2 : 2
+#define GCREG_HI_IDLE_IDLE_PE_End                                              2
+#define GCREG_HI_IDLE_IDLE_PE_Start                                            2
+#define GCREG_HI_IDLE_IDLE_PE_Type                                           U01
+
+/* AXI is in low power mode. */
+#define GCREG_HI_IDLE_AXI_LP                                             31 : 31
+#define GCREG_HI_IDLE_AXI_LP_End                                              31
+#define GCREG_HI_IDLE_AXI_LP_Start                                            31
+#define GCREG_HI_IDLE_AXI_LP_Type                                            U01
+
+union gcidle {
+	struct {
+		/* gcregHiIdle: GCREG_HI_IDLE_IDLE_FE */
+		unsigned int fe:1;
+
+		/* gcregHiIdle: GCREG_HI_IDLE_IDLE_DE */
+		unsigned int de:1;
+
+		/* gcregHiIdle: GCREG_HI_IDLE_IDLE_PE */
+		unsigned int pe:1;
+
+		/* gcregHiIdle: reserved */
+		unsigned int _reserved_3_30:28;
+
+		/* gcregHiIdle: GCREG_HI_IDLE_AXI_LP */
+		unsigned int axilp:1;
+	} reg;
+
+	unsigned int raw;
+};
+
+/*******************************************************************************
+** Register gcregAxiConfig
+*/
+
+#define GCREG_AXI_CONFIG_Address                                         0x00008
+#define GCREG_AXI_CONFIG_MSB                                                  15
+#define GCREG_AXI_CONFIG_LSB                                                   0
+#define GCREG_AXI_CONFIG_BLK                                                   0
+#define GCREG_AXI_CONFIG_Count                                                 1
+#define GCREG_AXI_CONFIG_FieldMask                                    0x0000FFFF
+#define GCREG_AXI_CONFIG_ReadMask                                     0x0000FFFF
+#define GCREG_AXI_CONFIG_WriteMask                                    0x0000FFFF
+#define GCREG_AXI_CONFIG_ResetValue                                   0x00000000
+
+#define GCREG_AXI_CONFIG_AWID                                              3 : 0
+#define GCREG_AXI_CONFIG_AWID_End                                              3
+#define GCREG_AXI_CONFIG_AWID_Start                                            0
+#define GCREG_AXI_CONFIG_AWID_Type                                           U04
+
+#define GCREG_AXI_CONFIG_ARID                                              7 : 4
+#define GCREG_AXI_CONFIG_ARID_End                                              7
+#define GCREG_AXI_CONFIG_ARID_Start                                            4
+#define GCREG_AXI_CONFIG_ARID_Type                                           U04
+
+#define GCREG_AXI_CONFIG_AWCACHE                                          11 : 8
+#define GCREG_AXI_CONFIG_AWCACHE_End                                          11
+#define GCREG_AXI_CONFIG_AWCACHE_Start                                         8
+#define GCREG_AXI_CONFIG_AWCACHE_Type                                        U04
+
+#define GCREG_AXI_CONFIG_ARCACHE                                         15 : 12
+#define GCREG_AXI_CONFIG_ARCACHE_End                                          15
+#define GCREG_AXI_CONFIG_ARCACHE_Start                                        12
+#define GCREG_AXI_CONFIG_ARCACHE_Type                                        U04
+
+/*******************************************************************************
+** Register gcregAxiStatus
+*/
+
+#define GCREG_AXI_STATUS_Address                                         0x0000C
+#define GCREG_AXI_STATUS_MSB                                                  15
+#define GCREG_AXI_STATUS_LSB                                                   0
+#define GCREG_AXI_STATUS_BLK                                                   0
+#define GCREG_AXI_STATUS_Count                                                 1
+#define GCREG_AXI_STATUS_FieldMask                                    0x000003FF
+#define GCREG_AXI_STATUS_ReadMask                                     0x000003FF
+#define GCREG_AXI_STATUS_WriteMask                                    0x00000000
+#define GCREG_AXI_STATUS_ResetValue                                   0x00000000
+
+#define GCREG_AXI_STATUS_DET_RD_ERR                                        9 : 9
+#define GCREG_AXI_STATUS_DET_RD_ERR_End                                        9
+#define GCREG_AXI_STATUS_DET_RD_ERR_Start                                      9
+#define GCREG_AXI_STATUS_DET_RD_ERR_Type                                     U01
+
+#define GCREG_AXI_STATUS_DET_WR_ERR                                        8 : 8
+#define GCREG_AXI_STATUS_DET_WR_ERR_End                                        8
+#define GCREG_AXI_STATUS_DET_WR_ERR_Start                                      8
+#define GCREG_AXI_STATUS_DET_WR_ERR_Type                                     U01
+
+#define GCREG_AXI_STATUS_RD_ERR_ID                                         7 : 4
+#define GCREG_AXI_STATUS_RD_ERR_ID_End                                         7
+#define GCREG_AXI_STATUS_RD_ERR_ID_Start                                       4
+#define GCREG_AXI_STATUS_RD_ERR_ID_Type                                      U04
+
+#define GCREG_AXI_STATUS_WR_ERR_ID                                         3 : 0
+#define GCREG_AXI_STATUS_WR_ERR_ID_End                                         3
+#define GCREG_AXI_STATUS_WR_ERR_ID_Start                                       0
+#define GCREG_AXI_STATUS_WR_ERR_ID_Type                                      U04
+
+/*******************************************************************************
+** Register gcregIntrAcknowledge
+*/
+
+/* Interrupt acknowledge register. Each bit represents a corresponding event
+** being triggered. Reading from this register clears the outstanding interrupt.
+*/
+
+#define GCREG_INTR_ACKNOWLEDGE_Address                                   0x00010
+#define GCREG_INTR_ACKNOWLEDGE_MSB                                            15
+#define GCREG_INTR_ACKNOWLEDGE_LSB                                             0
+#define GCREG_INTR_ACKNOWLEDGE_BLK                                             0
+#define GCREG_INTR_ACKNOWLEDGE_Count                                           1
+#define GCREG_INTR_ACKNOWLEDGE_FieldMask                              0xFFFFFFFF
+#define GCREG_INTR_ACKNOWLEDGE_ReadMask                               0xFFFFFFFF
+#define GCREG_INTR_ACKNOWLEDGE_WriteMask                              0x00000000
+#define GCREG_INTR_ACKNOWLEDGE_ResetValue                             0x00000000
+
+#define GCREG_INTR_ACKNOWLEDGE_INTR_VEC                                   31 : 0
+#define GCREG_INTR_ACKNOWLEDGE_INTR_VEC_End                                   31
+#define GCREG_INTR_ACKNOWLEDGE_INTR_VEC_Start                                  0
+#define GCREG_INTR_ACKNOWLEDGE_INTR_VEC_Type                                 U32
+
+/*******************************************************************************
+** Register gcregIntrEnbl
+*/
+
+/* Interrupt enable register. Each bit enables a corresponding event. */
+
+#define GCREG_INTR_ENBL_Address                                          0x00014
+#define GCREG_INTR_ENBL_MSB                                                   15
+#define GCREG_INTR_ENBL_LSB                                                    0
+#define GCREG_INTR_ENBL_BLK                                                    0
+#define GCREG_INTR_ENBL_Count                                                  1
+#define GCREG_INTR_ENBL_FieldMask                                     0xFFFFFFFF
+#define GCREG_INTR_ENBL_ReadMask                                      0xFFFFFFFF
+#define GCREG_INTR_ENBL_WriteMask                                     0xFFFFFFFF
+#define GCREG_INTR_ENBL_ResetValue                                    0x00000000
+
+#define GCREG_INTR_ENBL_INTR_ENBL_VEC                                     31 : 0
+#define GCREG_INTR_ENBL_INTR_ENBL_VEC_End                                     31
+#define GCREG_INTR_ENBL_INTR_ENBL_VEC_Start                                    0
+#define GCREG_INTR_ENBL_INTR_ENBL_VEC_Type                                   U32
+
+/*******************************************************************************
+** Register GCFeatures
+*/
+
+/* Shows which features are enabled in this chip.  This register has no set
+** reset value.  It varies with the implementation.
+*/
+
+#define GC_FEATURES_Address                                              0x0001C
+#define GC_FEATURES_MSB                                                       15
+#define GC_FEATURES_LSB                                                        0
+#define GC_FEATURES_BLK                                                        0
+#define GC_FEATURES_Count                                                      1
+#define GC_FEATURES_FieldMask                                         0xFFFFFFFF
+#define GC_FEATURES_ReadMask                                          0xFFFFFFFF
+#define GC_FEATURES_WriteMask                                         0x00000000
+#define GC_FEATURES_ResetValue                                        0x00000000
+
+/* Fast clear. */
+#define GC_FEATURES_FAST_CLEAR                                             0 : 0
+#define GC_FEATURES_FAST_CLEAR_End                                             0
+#define GC_FEATURES_FAST_CLEAR_Start                                           0
+#define GC_FEATURES_FAST_CLEAR_Type                                          U01
+#define   GC_FEATURES_FAST_CLEAR_NONE                                        0x0
+#define   GC_FEATURES_FAST_CLEAR_AVAILABLE                                   0x1
+
+/* Full-screen anti-aliasing. */
+#define GC_FEATURES_SPECIAL_ANTI_ALIASING                                  1 : 1
+#define GC_FEATURES_SPECIAL_ANTI_ALIASING_End                                  1
+#define GC_FEATURES_SPECIAL_ANTI_ALIASING_Start                                1
+#define GC_FEATURES_SPECIAL_ANTI_ALIASING_Type                               U01
+#define   GC_FEATURES_SPECIAL_ANTI_ALIASING_NONE                             0x0
+#define   GC_FEATURES_SPECIAL_ANTI_ALIASING_AVAILABLE                        0x1
+
+/* 3D pipe. */
+#define GC_FEATURES_PIPE_3D                                                2 : 2
+#define GC_FEATURES_PIPE_3D_End                                                2
+#define GC_FEATURES_PIPE_3D_Start                                              2
+#define GC_FEATURES_PIPE_3D_Type                                             U01
+#define   GC_FEATURES_PIPE_3D_NONE                                           0x0
+#define   GC_FEATURES_PIPE_3D_AVAILABLE                                      0x1
+
+/* DXT texture compression. */
+#define GC_FEATURES_DXT_TEXTURE_COMPRESSION                                3 : 3
+#define GC_FEATURES_DXT_TEXTURE_COMPRESSION_End                                3
+#define GC_FEATURES_DXT_TEXTURE_COMPRESSION_Start                              3
+#define GC_FEATURES_DXT_TEXTURE_COMPRESSION_Type                             U01
+#define   GC_FEATURES_DXT_TEXTURE_COMPRESSION_NONE                           0x0
+#define   GC_FEATURES_DXT_TEXTURE_COMPRESSION_AVAILABLE                      0x1
+
+/* Debug registers. */
+#define GC_FEATURES_DEBUG_MODE                                             4 : 4
+#define GC_FEATURES_DEBUG_MODE_End                                             4
+#define GC_FEATURES_DEBUG_MODE_Start                                           4
+#define GC_FEATURES_DEBUG_MODE_Type                                          U01
+#define   GC_FEATURES_DEBUG_MODE_NONE                                        0x0
+#define   GC_FEATURES_DEBUG_MODE_AVAILABLE                                   0x1
+
+/* Depth and color compression. */
+#define GC_FEATURES_ZCOMPRESSION                                           5 : 5
+#define GC_FEATURES_ZCOMPRESSION_End                                           5
+#define GC_FEATURES_ZCOMPRESSION_Start                                         5
+#define GC_FEATURES_ZCOMPRESSION_Type                                        U01
+#define   GC_FEATURES_ZCOMPRESSION_NONE                                      0x0
+#define   GC_FEATURES_ZCOMPRESSION_AVAILABLE                                 0x1
+
+/* YUV 4:2:0 support in filter blit. */
+#define GC_FEATURES_YUV420_FILTER                                          6 : 6
+#define GC_FEATURES_YUV420_FILTER_End                                          6
+#define GC_FEATURES_YUV420_FILTER_Start                                        6
+#define GC_FEATURES_YUV420_FILTER_Type                                       U01
+#define   GC_FEATURES_YUV420_FILTER_NONE                                     0x0
+#define   GC_FEATURES_YUV420_FILTER_AVAILABLE                                0x1
+
+/* MSAA support. */
+#define GC_FEATURES_MSAA                                                   7 : 7
+#define GC_FEATURES_MSAA_End                                                   7
+#define GC_FEATURES_MSAA_Start                                                 7
+#define GC_FEATURES_MSAA_Type                                                U01
+#define   GC_FEATURES_MSAA_NONE                                              0x0
+#define   GC_FEATURES_MSAA_AVAILABLE                                         0x1
+
+/* Shows if there is a display controller in the IP. */
+#define GC_FEATURES_DC                                                     8 : 8
+#define GC_FEATURES_DC_End                                                     8
+#define GC_FEATURES_DC_Start                                                   8
+#define GC_FEATURES_DC_Type                                                  U01
+#define   GC_FEATURES_DC_NONE                                                0x0
+#define   GC_FEATURES_DC_AVAILABLE                                           0x1
+
+/* Shows if there is 2D engine. */
+#define GC_FEATURES_PIPE_2D                                                9 : 9
+#define GC_FEATURES_PIPE_2D_End                                                9
+#define GC_FEATURES_PIPE_2D_Start                                              9
+#define GC_FEATURES_PIPE_2D_Type                                             U01
+#define   GC_FEATURES_PIPE_2D_NONE                                           0x0
+#define   GC_FEATURES_PIPE_2D_AVAILABLE                                      0x1
+
+/* ETC1 texture compression. */
+#define GC_FEATURES_ETC1_TEXTURE_COMPRESSION                             10 : 10
+#define GC_FEATURES_ETC1_TEXTURE_COMPRESSION_End                              10
+#define GC_FEATURES_ETC1_TEXTURE_COMPRESSION_Start                            10
+#define GC_FEATURES_ETC1_TEXTURE_COMPRESSION_Type                            U01
+#define   GC_FEATURES_ETC1_TEXTURE_COMPRESSION_NONE                          0x0
+#define   GC_FEATURES_ETC1_TEXTURE_COMPRESSION_AVAILABLE                     0x1
+
+/* Shows if the IP has HD scaler. */
+#define GC_FEATURES_FAST_SCALER                                          11 : 11
+#define GC_FEATURES_FAST_SCALER_End                                           11
+#define GC_FEATURES_FAST_SCALER_Start                                         11
+#define GC_FEATURES_FAST_SCALER_Type                                         U01
+#define   GC_FEATURES_FAST_SCALER_NONE                                       0x0
+#define   GC_FEATURES_FAST_SCALER_AVAILABLE                                  0x1
+
+/* Shows if the IP has HDR support. */
+#define GC_FEATURES_HIGH_DYNAMIC_RANGE                                   12 : 12
+#define GC_FEATURES_HIGH_DYNAMIC_RANGE_End                                    12
+#define GC_FEATURES_HIGH_DYNAMIC_RANGE_Start                                  12
+#define GC_FEATURES_HIGH_DYNAMIC_RANGE_Type                                  U01
+#define   GC_FEATURES_HIGH_DYNAMIC_RANGE_NONE                                0x0
+#define   GC_FEATURES_HIGH_DYNAMIC_RANGE_AVAILABLE                           0x1
+
+/* YUV 4:2:0 tiler is available. */
+#define GC_FEATURES_YUV420_TILER                                         13 : 13
+#define GC_FEATURES_YUV420_TILER_End                                          13
+#define GC_FEATURES_YUV420_TILER_Start                                        13
+#define GC_FEATURES_YUV420_TILER_Type                                        U01
+#define   GC_FEATURES_YUV420_TILER_NONE                                      0x0
+#define   GC_FEATURES_YUV420_TILER_AVAILABLE                                 0x1
+
+/* Second level clock gating is available. */
+#define GC_FEATURES_MODULE_CG                                            14 : 14
+#define GC_FEATURES_MODULE_CG_End                                             14
+#define GC_FEATURES_MODULE_CG_Start                                           14
+#define GC_FEATURES_MODULE_CG_Type                                           U01
+#define   GC_FEATURES_MODULE_CG_NONE                                         0x0
+#define   GC_FEATURES_MODULE_CG_AVAILABLE                                    0x1
+
+/* IP is configured to have minimum area. */
+#define GC_FEATURES_MIN_AREA                                             15 : 15
+#define GC_FEATURES_MIN_AREA_End                                              15
+#define GC_FEATURES_MIN_AREA_Start                                            15
+#define GC_FEATURES_MIN_AREA_Type                                            U01
+#define   GC_FEATURES_MIN_AREA_NONE                                          0x0
+#define   GC_FEATURES_MIN_AREA_AVAILABLE                                     0x1
+
+/* IP does not have early-Z. */
+#define GC_FEATURES_NO_EZ                                                16 : 16
+#define GC_FEATURES_NO_EZ_End                                                 16
+#define GC_FEATURES_NO_EZ_Start                                               16
+#define GC_FEATURES_NO_EZ_Type                                               U01
+#define   GC_FEATURES_NO_EZ_NONE                                             0x0
+#define   GC_FEATURES_NO_EZ_AVAILABLE                                        0x1
+
+/* IP does not have 422 texture input format. */
+#define GC_FEATURES_NO422_TEXTURE                                        17 : 17
+#define GC_FEATURES_NO422_TEXTURE_End                                         17
+#define GC_FEATURES_NO422_TEXTURE_Start                                       17
+#define GC_FEATURES_NO422_TEXTURE_Type                                       U01
+#define   GC_FEATURES_NO422_TEXTURE_NONE                                     0x0
+#define   GC_FEATURES_NO422_TEXTURE_AVAILABLE                                0x1
+
+/* IP supports interleaving depth and color buffers. */
+#define GC_FEATURES_BUFFER_INTERLEAVING                                  18 : 18
+#define GC_FEATURES_BUFFER_INTERLEAVING_End                                   18
+#define GC_FEATURES_BUFFER_INTERLEAVING_Start                                 18
+#define GC_FEATURES_BUFFER_INTERLEAVING_Type                                 U01
+#define   GC_FEATURES_BUFFER_INTERLEAVING_NONE                               0x0
+#define   GC_FEATURES_BUFFER_INTERLEAVING_AVAILABLE                          0x1
+
+/* Supports byte write in 2D. */
+#define GC_FEATURES_BYTE_WRITE_2D                                        19 : 19
+#define GC_FEATURES_BYTE_WRITE_2D_End                                         19
+#define GC_FEATURES_BYTE_WRITE_2D_Start                                       19
+#define GC_FEATURES_BYTE_WRITE_2D_Type                                       U01
+#define   GC_FEATURES_BYTE_WRITE_2D_NONE                                     0x0
+#define   GC_FEATURES_BYTE_WRITE_2D_AVAILABLE                                0x1
+
+/* IP does not have 2D scaler. */
+#define GC_FEATURES_NO_SCALER                                            20 : 20
+#define GC_FEATURES_NO_SCALER_End                                             20
+#define GC_FEATURES_NO_SCALER_Start                                           20
+#define GC_FEATURES_NO_SCALER_Type                                           U01
+#define   GC_FEATURES_NO_SCALER_NONE                                         0x0
+#define   GC_FEATURES_NO_SCALER_AVAILABLE                                    0x1
+
+/* YUY2 averaging support in resolve. */
+#define GC_FEATURES_YUY2_AVERAGING                                       21 : 21
+#define GC_FEATURES_YUY2_AVERAGING_End                                        21
+#define GC_FEATURES_YUY2_AVERAGING_Start                                      21
+#define GC_FEATURES_YUY2_AVERAGING_Type                                      U01
+#define   GC_FEATURES_YUY2_AVERAGING_NONE                                    0x0
+#define   GC_FEATURES_YUY2_AVERAGING_AVAILABLE                               0x1
+
+/* PE cache is half. */
+#define GC_FEATURES_HALF_PE_CACHE                                        22 : 22
+#define GC_FEATURES_HALF_PE_CACHE_End                                         22
+#define GC_FEATURES_HALF_PE_CACHE_Start                                       22
+#define GC_FEATURES_HALF_PE_CACHE_Type                                       U01
+#define   GC_FEATURES_HALF_PE_CACHE_NONE                                     0x0
+#define   GC_FEATURES_HALF_PE_CACHE_AVAILABLE                                0x1
+
+/* TX cache is half. */
+#define GC_FEATURES_HALF_TX_CACHE                                        23 : 23
+#define GC_FEATURES_HALF_TX_CACHE_End                                         23
+#define GC_FEATURES_HALF_TX_CACHE_Start                                       23
+#define GC_FEATURES_HALF_TX_CACHE_Type                                       U01
+#define   GC_FEATURES_HALF_TX_CACHE_NONE                                     0x0
+#define   GC_FEATURES_HALF_TX_CACHE_AVAILABLE                                0x1
+
+/* YUY2 support in PE and YUY2 to RGB conversion in resolve. */
+#define GC_FEATURES_YUY2_RENDER_TARGET                                   24 : 24
+#define GC_FEATURES_YUY2_RENDER_TARGET_End                                    24
+#define GC_FEATURES_YUY2_RENDER_TARGET_Start                                  24
+#define GC_FEATURES_YUY2_RENDER_TARGET_Type                                  U01
+#define   GC_FEATURES_YUY2_RENDER_TARGET_NONE                                0x0
+#define   GC_FEATURES_YUY2_RENDER_TARGET_AVAILABLE                           0x1
+
+/* 32 bit memory address support. */
+#define GC_FEATURES_MEM32_BIT_SUPPORT                                    25 : 25
+#define GC_FEATURES_MEM32_BIT_SUPPORT_End                                     25
+#define GC_FEATURES_MEM32_BIT_SUPPORT_Start                                   25
+#define GC_FEATURES_MEM32_BIT_SUPPORT_Type                                   U01
+#define   GC_FEATURES_MEM32_BIT_SUPPORT_NONE                                 0x0
+#define   GC_FEATURES_MEM32_BIT_SUPPORT_AVAILABLE                            0x1
+
+/* VG pipe is present. */
+#define GC_FEATURES_PIPE_VG                                              26 : 26
+#define GC_FEATURES_PIPE_VG_End                                               26
+#define GC_FEATURES_PIPE_VG_Start                                             26
+#define GC_FEATURES_PIPE_VG_Type                                             U01
+#define   GC_FEATURES_PIPE_VG_NONE                                           0x0
+#define   GC_FEATURES_PIPE_VG_AVAILABLE                                      0x1
+
+/* VG tesselator is present. */
+#define GC_FEATURES_VGTS                                                 27 : 27
+#define GC_FEATURES_VGTS_End                                                  27
+#define GC_FEATURES_VGTS_Start                                                27
+#define GC_FEATURES_VGTS_Type                                                U01
+#define   GC_FEATURES_VGTS_NONE                                              0x0
+#define   GC_FEATURES_VGTS_AVAILABLE                                         0x1
+
+/* FE 2.0 is present. */
+#define GC_FEATURES_FE20                                                 28 : 28
+#define GC_FEATURES_FE20_End                                                  28
+#define GC_FEATURES_FE20_Start                                                28
+#define GC_FEATURES_FE20_Type                                                U01
+#define   GC_FEATURES_FE20_NONE                                              0x0
+#define   GC_FEATURES_FE20_AVAILABLE                                         0x1
+
+/* 3D PE has byte write capability. */
+#define GC_FEATURES_BYTE_WRITE_3D                                        29 : 29
+#define GC_FEATURES_BYTE_WRITE_3D_End                                         29
+#define GC_FEATURES_BYTE_WRITE_3D_Start                                       29
+#define GC_FEATURES_BYTE_WRITE_3D_Type                                       U01
+#define   GC_FEATURES_BYTE_WRITE_3D_NONE                                     0x0
+#define   GC_FEATURES_BYTE_WRITE_3D_AVAILABLE                                0x1
+
+/* Supports resolveing into YUV target. */
+#define GC_FEATURES_RS_YUV_TARGET                                        30 : 30
+#define GC_FEATURES_RS_YUV_TARGET_End                                         30
+#define GC_FEATURES_RS_YUV_TARGET_Start                                       30
+#define GC_FEATURES_RS_YUV_TARGET_Type                                       U01
+#define   GC_FEATURES_RS_YUV_TARGET_NONE                                     0x0
+#define   GC_FEATURES_RS_YUV_TARGET_AVAILABLE                                0x1
+
+/* Supports 20 bit index. */
+#define GC_FEATURES_FE20_BIT_INDEX                                       31 : 31
+#define GC_FEATURES_FE20_BIT_INDEX_End                                        31
+#define GC_FEATURES_FE20_BIT_INDEX_Start                                      31
+#define GC_FEATURES_FE20_BIT_INDEX_Type                                      U01
+#define   GC_FEATURES_FE20_BIT_INDEX_NONE                                    0x0
+#define   GC_FEATURES_FE20_BIT_INDEX_AVAILABLE                               0x1
+
+/*******************************************************************************
+** Register GCChipId
+*/
+
+/* Shows the ID for the chip in BCD.  This register has no set reset value.
+** It varies with the implementation.
+*/
+
+#define GC_CHIP_ID_Address                                               0x00020
+#define GC_CHIP_ID_MSB                                                        15
+#define GC_CHIP_ID_LSB                                                         0
+#define GC_CHIP_ID_BLK                                                         0
+#define GC_CHIP_ID_Count                                                       1
+#define GC_CHIP_ID_FieldMask                                          0xFFFFFFFF
+#define GC_CHIP_ID_ReadMask                                           0xFFFFFFFF
+#define GC_CHIP_ID_WriteMask                                          0x00000000
+#define GC_CHIP_ID_ResetValue                                         0x00000000
+
+/* Id. */
+#define GC_CHIP_ID_ID                                                     31 : 0
+#define GC_CHIP_ID_ID_End                                                     31
+#define GC_CHIP_ID_ID_Start                                                    0
+#define GC_CHIP_ID_ID_Type                                                   U32
+
+/*******************************************************************************
+** Register GCChipRev
+*/
+
+/* Shows the revision for the chip in BCD.  This register has no set reset
+** value.  It varies with the implementation.
+*/
+
+#define GC_CHIP_REV_Address                                              0x00024
+#define GC_CHIP_REV_MSB                                                       15
+#define GC_CHIP_REV_LSB                                                        0
+#define GC_CHIP_REV_BLK                                                        0
+#define GC_CHIP_REV_Count                                                      1
+#define GC_CHIP_REV_FieldMask                                         0xFFFFFFFF
+#define GC_CHIP_REV_ReadMask                                          0xFFFFFFFF
+#define GC_CHIP_REV_WriteMask                                         0x00000000
+#define GC_CHIP_REV_ResetValue                                        0x00000000
+
+/* Revision. */
+#define GC_CHIP_REV_REV                                                   31 : 0
+#define GC_CHIP_REV_REV_End                                                   31
+#define GC_CHIP_REV_REV_Start                                                  0
+#define GC_CHIP_REV_REV_Type                                                 U32
+
+/*******************************************************************************
+** Register GCChipDate
+*/
+
+/* Shows the release date for the IP.  This register has no set reset value.
+** It varies with the implementation.
+*/
+
+#define GC_CHIP_DATE_Address                                             0x00028
+#define GC_CHIP_DATE_MSB                                                      15
+#define GC_CHIP_DATE_LSB                                                       0
+#define GC_CHIP_DATE_BLK                                                       0
+#define GC_CHIP_DATE_Count                                                     1
+#define GC_CHIP_DATE_FieldMask                                        0xFFFFFFFF
+#define GC_CHIP_DATE_ReadMask                                         0xFFFFFFFF
+#define GC_CHIP_DATE_WriteMask                                        0x00000000
+#define GC_CHIP_DATE_ResetValue                                       0x00000000
+
+/* Date. */
+#define GC_CHIP_DATE_DATE                                                 31 : 0
+#define GC_CHIP_DATE_DATE_End                                                 31
+#define GC_CHIP_DATE_DATE_Start                                                0
+#define GC_CHIP_DATE_DATE_Type                                               U32
+
+/*******************************************************************************
+** Register GCChipTime
+*/
+
+/* Shows the release time for the IP.  This register has no set reset value.
+** It varies with the implementation.
+*/
+
+#define GC_CHIP_TIME_Address                                             0x0002C
+#define GC_CHIP_TIME_MSB                                                      15
+#define GC_CHIP_TIME_LSB                                                       0
+#define GC_CHIP_TIME_BLK                                                       0
+#define GC_CHIP_TIME_Count                                                     1
+#define GC_CHIP_TIME_FieldMask                                        0xFFFFFFFF
+#define GC_CHIP_TIME_ReadMask                                         0xFFFFFFFF
+#define GC_CHIP_TIME_WriteMask                                        0x00000000
+#define GC_CHIP_TIME_ResetValue                                       0x00000000
+
+/* Time. */
+#define GC_CHIP_TIME_TIME                                                 31 : 0
+#define GC_CHIP_TIME_TIME_End                                                 31
+#define GC_CHIP_TIME_TIME_Start                                                0
+#define GC_CHIP_TIME_TIME_Type                                               U32
+
+/*******************************************************************************
+** Register GCMinorFeatures0
+*/
+
+/* Shows which minor features are enabled in this chip.  This register has no
+** set reset value.  It varies with the implementation.
+*/
+
+#define GC_MINOR_FEATURES0_Address                                       0x00034
+#define GC_MINOR_FEATURES0_MSB                                                15
+#define GC_MINOR_FEATURES0_LSB                                                 0
+#define GC_MINOR_FEATURES0_BLK                                                 0
+#define GC_MINOR_FEATURES0_Count                                               1
+#define GC_MINOR_FEATURES0_FieldMask                                  0xFFFFFFFF
+#define GC_MINOR_FEATURES0_ReadMask                                   0xFFFFFFFF
+#define GC_MINOR_FEATURES0_WriteMask                                  0x00000000
+#define GC_MINOR_FEATURES0_ResetValue                                 0x00000000
+
+/* Y flipping capability is added to resolve. */
+#define GC_MINOR_FEATURES0_FLIP_Y                                          0 : 0
+#define GC_MINOR_FEATURES0_FLIP_Y_End                                          0
+#define GC_MINOR_FEATURES0_FLIP_Y_Start                                        0
+#define GC_MINOR_FEATURES0_FLIP_Y_Type                                       U01
+#define   GC_MINOR_FEATURES0_FLIP_Y_NONE                                     0x0
+#define   GC_MINOR_FEATURES0_FLIP_Y_AVAILABLE                                0x1
+
+/* Dual Return Bus from HI to clients. */
+#define GC_MINOR_FEATURES0_DUAL_RETURN_BUS                                 1 : 1
+#define GC_MINOR_FEATURES0_DUAL_RETURN_BUS_End                                 1
+#define GC_MINOR_FEATURES0_DUAL_RETURN_BUS_Start                               1
+#define GC_MINOR_FEATURES0_DUAL_RETURN_BUS_Type                              U01
+#define   GC_MINOR_FEATURES0_DUAL_RETURN_BUS_NONE                            0x0
+#define   GC_MINOR_FEATURES0_DUAL_RETURN_BUS_AVAILABLE                       0x1
+
+/* Configurable endianness support. */
+#define GC_MINOR_FEATURES0_ENDIANNESS_CONFIG                               2 : 2
+#define GC_MINOR_FEATURES0_ENDIANNESS_CONFIG_End                               2
+#define GC_MINOR_FEATURES0_ENDIANNESS_CONFIG_Start                             2
+#define GC_MINOR_FEATURES0_ENDIANNESS_CONFIG_Type                            U01
+#define   GC_MINOR_FEATURES0_ENDIANNESS_CONFIG_NONE                          0x0
+#define   GC_MINOR_FEATURES0_ENDIANNESS_CONFIG_AVAILABLE                     0x1
+
+/* Supports 8Kx8K textures. */
+#define GC_MINOR_FEATURES0_TEXTURE8_K                                      3 : 3
+#define GC_MINOR_FEATURES0_TEXTURE8_K_End                                      3
+#define GC_MINOR_FEATURES0_TEXTURE8_K_Start                                    3
+#define GC_MINOR_FEATURES0_TEXTURE8_K_Type                                   U01
+#define   GC_MINOR_FEATURES0_TEXTURE8_K_NONE                                 0x0
+#define   GC_MINOR_FEATURES0_TEXTURE8_K_AVAILABLE                            0x1
+
+/* Driver hack is not needed. */
+#define GC_MINOR_FEATURES0_CORRECT_TEXTURE_CONVERTER                       4 : 4
+#define GC_MINOR_FEATURES0_CORRECT_TEXTURE_CONVERTER_End                       4
+#define GC_MINOR_FEATURES0_CORRECT_TEXTURE_CONVERTER_Start                     4
+#define GC_MINOR_FEATURES0_CORRECT_TEXTURE_CONVERTER_Type                    U01
+#define   GC_MINOR_FEATURES0_CORRECT_TEXTURE_CONVERTER_NONE                  0x0
+#define   GC_MINOR_FEATURES0_CORRECT_TEXTURE_CONVERTER_AVAILABLE             0x1
+
+/* Special LOD calculation when MSAA is on. */
+#define GC_MINOR_FEATURES0_SPECIAL_MSAA_LOD                                5 : 5
+#define GC_MINOR_FEATURES0_SPECIAL_MSAA_LOD_End                                5
+#define GC_MINOR_FEATURES0_SPECIAL_MSAA_LOD_Start                              5
+#define GC_MINOR_FEATURES0_SPECIAL_MSAA_LOD_Type                             U01
+#define   GC_MINOR_FEATURES0_SPECIAL_MSAA_LOD_NONE                           0x0
+#define   GC_MINOR_FEATURES0_SPECIAL_MSAA_LOD_AVAILABLE                      0x1
+
+/* Proper flush is done in fast clear cache. */
+#define GC_MINOR_FEATURES0_FAST_CLEAR_FLUSH                                6 : 6
+#define GC_MINOR_FEATURES0_FAST_CLEAR_FLUSH_End                                6
+#define GC_MINOR_FEATURES0_FAST_CLEAR_FLUSH_Start                              6
+#define GC_MINOR_FEATURES0_FAST_CLEAR_FLUSH_Type                             U01
+#define   GC_MINOR_FEATURES0_FAST_CLEAR_FLUSH_NONE                           0x0
+#define   GC_MINOR_FEATURES0_FAST_CLEAR_FLUSH_AVAILABLE                      0x1
+
+/* 2D PE 2.0 is present. */
+#define GC_MINOR_FEATURES0_2DPE20                                          7 : 7
+#define GC_MINOR_FEATURES0_2DPE20_End                                          7
+#define GC_MINOR_FEATURES0_2DPE20_Start                                        7
+#define GC_MINOR_FEATURES0_2DPE20_Type                                       U01
+#define   GC_MINOR_FEATURES0_2DPE20_NONE                                     0x0
+#define   GC_MINOR_FEATURES0_2DPE20_AVAILABLE                                0x1
+
+/* Reserved. */
+#define GC_MINOR_FEATURES0_CORRECT_AUTO_DISABLE                            8 : 8
+#define GC_MINOR_FEATURES0_CORRECT_AUTO_DISABLE_End                            8
+#define GC_MINOR_FEATURES0_CORRECT_AUTO_DISABLE_Start                          8
+#define GC_MINOR_FEATURES0_CORRECT_AUTO_DISABLE_Type                         U01
+#define   GC_MINOR_FEATURES0_CORRECT_AUTO_DISABLE_NONE                       0x0
+#define   GC_MINOR_FEATURES0_CORRECT_AUTO_DISABLE_AVAILABLE                  0x1
+
+/* Supports 8K render target. */
+#define GC_MINOR_FEATURES0_RENDER_8K                                       9 : 9
+#define GC_MINOR_FEATURES0_RENDER_8K_End                                       9
+#define GC_MINOR_FEATURES0_RENDER_8K_Start                                     9
+#define GC_MINOR_FEATURES0_RENDER_8K_Type                                    U01
+#define   GC_MINOR_FEATURES0_RENDER_8K_NONE                                  0x0
+#define   GC_MINOR_FEATURES0_RENDER_8K_AVAILABLE                             0x1
+
+/* 2 bits are used instead of 4 bits for tile status. */
+#define GC_MINOR_FEATURES0_TILE_STATUS_2BITS                             10 : 10
+#define GC_MINOR_FEATURES0_TILE_STATUS_2BITS_End                              10
+#define GC_MINOR_FEATURES0_TILE_STATUS_2BITS_Start                            10
+#define GC_MINOR_FEATURES0_TILE_STATUS_2BITS_Type                            U01
+#define   GC_MINOR_FEATURES0_TILE_STATUS_2BITS_NONE                          0x0
+#define   GC_MINOR_FEATURES0_TILE_STATUS_2BITS_AVAILABLE                     0x1
+
+/* Use 2 separate tile status buffers in interleaved mode. */
+#define GC_MINOR_FEATURES0_SEPARATE_TILE_STATUS_WHEN_INTERLEAVED         11 : 11
+#define GC_MINOR_FEATURES0_SEPARATE_TILE_STATUS_WHEN_INTERLEAVED_End          11
+#define GC_MINOR_FEATURES0_SEPARATE_TILE_STATUS_WHEN_INTERLEAVED_Start        11
+#define GC_MINOR_FEATURES0_SEPARATE_TILE_STATUS_WHEN_INTERLEAVED_Type        U01
+#define   GC_MINOR_FEATURES0_SEPARATE_TILE_STATUS_WHEN_INTERLEAVED_NONE      0x0
+#define   GC_MINOR_FEATURES0_SEPARATE_TILE_STATUS_WHEN_INTERLEAVED_AVAILABLE 0x1
+
+/* 32x32 super tile is available. */
+#define GC_MINOR_FEATURES0_SUPER_TILED_32X32                             12 : 12
+#define GC_MINOR_FEATURES0_SUPER_TILED_32X32_End                              12
+#define GC_MINOR_FEATURES0_SUPER_TILED_32X32_Start                            12
+#define GC_MINOR_FEATURES0_SUPER_TILED_32X32_Type                            U01
+#define   GC_MINOR_FEATURES0_SUPER_TILED_32X32_NONE                          0x0
+#define   GC_MINOR_FEATURES0_SUPER_TILED_32X32_AVAILABLE                     0x1
+
+/* Major updates to VG pipe (TS buffer tiling. State masking.). */
+#define GC_MINOR_FEATURES0_VG_20                                         13 : 13
+#define GC_MINOR_FEATURES0_VG_20_End                                          13
+#define GC_MINOR_FEATURES0_VG_20_Start                                        13
+#define GC_MINOR_FEATURES0_VG_20_Type                                        U01
+#define   GC_MINOR_FEATURES0_VG_20_NONE                                      0x0
+#define   GC_MINOR_FEATURES0_VG_20_AVAILABLE                                 0x1
+
+/* New commands added to the tessellator. */
+#define GC_MINOR_FEATURES0_TS_EXTENDED_COMMANDS                          14 : 14
+#define GC_MINOR_FEATURES0_TS_EXTENDED_COMMANDS_End                           14
+#define GC_MINOR_FEATURES0_TS_EXTENDED_COMMANDS_Start                         14
+#define GC_MINOR_FEATURES0_TS_EXTENDED_COMMANDS_Type                         U01
+#define   GC_MINOR_FEATURES0_TS_EXTENDED_COMMANDS_NONE                       0x0
+#define   GC_MINOR_FEATURES0_TS_EXTENDED_COMMANDS_AVAILABLE                  0x1
+
+/* If this bit is not set, the FIFO counter should be set to 50.  Else, the   **
+** default should remain.                                                     */
+#define GC_MINOR_FEATURES0_COMPRESSION_FIFO_FIXED                        15 : 15
+#define GC_MINOR_FEATURES0_COMPRESSION_FIFO_FIXED_End                         15
+#define GC_MINOR_FEATURES0_COMPRESSION_FIFO_FIXED_Start                       15
+#define GC_MINOR_FEATURES0_COMPRESSION_FIFO_FIXED_Type                       U01
+#define   GC_MINOR_FEATURES0_COMPRESSION_FIFO_FIXED_NONE                     0x0
+#define   GC_MINOR_FEATURES0_COMPRESSION_FIFO_FIXED_AVAILABLE                0x1
+
+/* Floor, ceil, and sign instructions are available.  */
+#define GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS0                    16 : 16
+#define GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS0_End                     16
+#define GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS0_Start                   16
+#define GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS0_Type                   U01
+#define   GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS0_NONE                 0x0
+#define   GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS0_AVAILABLE            0x1
+
+/* VG filter is available.  */
+#define GC_MINOR_FEATURES0_VG_FILTER                                     17 : 17
+#define GC_MINOR_FEATURES0_VG_FILTER_End                                      17
+#define GC_MINOR_FEATURES0_VG_FILTER_Start                                    17
+#define GC_MINOR_FEATURES0_VG_FILTER_Type                                    U01
+#define   GC_MINOR_FEATURES0_VG_FILTER_NONE                                  0x0
+#define   GC_MINOR_FEATURES0_VG_FILTER_AVAILABLE                             0x1
+
+/* Minor updates to VG pipe (Event generation from VG, TS, PE). Tiled image   **
+** support.                                                                   */
+#define GC_MINOR_FEATURES0_VG_21                                         18 : 18
+#define GC_MINOR_FEATURES0_VG_21_End                                          18
+#define GC_MINOR_FEATURES0_VG_21_Start                                        18
+#define GC_MINOR_FEATURES0_VG_21_Type                                        U01
+#define   GC_MINOR_FEATURES0_VG_21_NONE                                      0x0
+#define   GC_MINOR_FEATURES0_VG_21_AVAILABLE                                 0x1
+
+/* W is sent to SH from RA. */
+#define GC_MINOR_FEATURES0_SHADER_GETS_W                                 19 : 19
+#define GC_MINOR_FEATURES0_SHADER_GETS_W_End                                  19
+#define GC_MINOR_FEATURES0_SHADER_GETS_W_Start                                19
+#define GC_MINOR_FEATURES0_SHADER_GETS_W_Type                                U01
+#define   GC_MINOR_FEATURES0_SHADER_GETS_W_NONE                              0x0
+#define   GC_MINOR_FEATURES0_SHADER_GETS_W_AVAILABLE                         0x1
+
+/* Sqrt, sin, cos instructions are available.  */
+#define GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS1                    20 : 20
+#define GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS1_End                     20
+#define GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS1_Start                   20
+#define GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS1_Type                   U01
+#define   GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS1_NONE                 0x0
+#define   GC_MINOR_FEATURES0_EXTRA_SHADER_INSTRUCTIONS1_AVAILABLE            0x1
+
+/* Unavailable registers will return 0. */
+#define GC_MINOR_FEATURES0_DEFAULT_REG0                                  21 : 21
+#define GC_MINOR_FEATURES0_DEFAULT_REG0_End                                   21
+#define GC_MINOR_FEATURES0_DEFAULT_REG0_Start                                 21
+#define GC_MINOR_FEATURES0_DEFAULT_REG0_Type                                 U01
+#define   GC_MINOR_FEATURES0_DEFAULT_REG0_NONE                               0x0
+#define   GC_MINOR_FEATURES0_DEFAULT_REG0_AVAILABLE                          0x1
+
+/* New style MC with separate paths for color and depth. */
+#define GC_MINOR_FEATURES0_MC_20                                         22 : 22
+#define GC_MINOR_FEATURES0_MC_20_End                                          22
+#define GC_MINOR_FEATURES0_MC_20_Start                                        22
+#define GC_MINOR_FEATURES0_MC_20_Type                                        U01
+#define   GC_MINOR_FEATURES0_MC_20_NONE                                      0x0
+#define   GC_MINOR_FEATURES0_MC_20_AVAILABLE                                 0x1
+
+/* Put the MSAA data into sideband fifo. */
+#define GC_MINOR_FEATURES0_SHADER_MSAA_SIDEBAND                          23 : 23
+#define GC_MINOR_FEATURES0_SHADER_MSAA_SIDEBAND_End                           23
+#define GC_MINOR_FEATURES0_SHADER_MSAA_SIDEBAND_Start                         23
+#define GC_MINOR_FEATURES0_SHADER_MSAA_SIDEBAND_Type                         U01
+#define   GC_MINOR_FEATURES0_SHADER_MSAA_SIDEBAND_NONE                       0x0
+#define   GC_MINOR_FEATURES0_SHADER_MSAA_SIDEBAND_AVAILABLE                  0x1
+
+#define GC_MINOR_FEATURES0_BUG_FIXES0                                    24 : 24
+#define GC_MINOR_FEATURES0_BUG_FIXES0_End                                     24
+#define GC_MINOR_FEATURES0_BUG_FIXES0_Start                                   24
+#define GC_MINOR_FEATURES0_BUG_FIXES0_Type                                   U01
+#define   GC_MINOR_FEATURES0_BUG_FIXES0_NONE                                 0x0
+#define   GC_MINOR_FEATURES0_BUG_FIXES0_AVAILABLE                            0x1
+
+/* VAA is available or not. */
+#define GC_MINOR_FEATURES0_VAA                                           25 : 25
+#define GC_MINOR_FEATURES0_VAA_End                                            25
+#define GC_MINOR_FEATURES0_VAA_Start                                          25
+#define GC_MINOR_FEATURES0_VAA_Type                                          U01
+#define   GC_MINOR_FEATURES0_VAA_NONE                                        0x0
+#define   GC_MINOR_FEATURES0_VAA_AVAILABLE                                   0x1
+
+/* Shader supports bypass mode when MSAA is enabled. */
+#define GC_MINOR_FEATURES0_BYPASS_IN_MSAA                                26 : 26
+#define GC_MINOR_FEATURES0_BYPASS_IN_MSAA_End                                 26
+#define GC_MINOR_FEATURES0_BYPASS_IN_MSAA_Start                               26
+#define GC_MINOR_FEATURES0_BYPASS_IN_MSAA_Type                               U01
+#define   GC_MINOR_FEATURES0_BYPASS_IN_MSAA_NONE                             0x0
+#define   GC_MINOR_FEATURES0_BYPASS_IN_MSAA_AVAILABLE                        0x1
+
+/* Hierarchiccal Z is supported. */
+#define GC_MINOR_FEATURES0_HIERARCHICAL_Z                                27 : 27
+#define GC_MINOR_FEATURES0_HIERARCHICAL_Z_End                                 27
+#define GC_MINOR_FEATURES0_HIERARCHICAL_Z_Start                               27
+#define GC_MINOR_FEATURES0_HIERARCHICAL_Z_Type                               U01
+#define   GC_MINOR_FEATURES0_HIERARCHICAL_Z_NONE                             0x0
+#define   GC_MINOR_FEATURES0_HIERARCHICAL_Z_AVAILABLE                        0x1
+
+/* New texture unit is available. */
+#define GC_MINOR_FEATURES0_NEW_TEXTURE                                   28 : 28
+#define GC_MINOR_FEATURES0_NEW_TEXTURE_End                                    28
+#define GC_MINOR_FEATURES0_NEW_TEXTURE_Start                                  28
+#define GC_MINOR_FEATURES0_NEW_TEXTURE_Type                                  U01
+#define   GC_MINOR_FEATURES0_NEW_TEXTURE_NONE                                0x0
+#define   GC_MINOR_FEATURES0_NEW_TEXTURE_AVAILABLE                           0x1
+
+/* 2D engine supports A8 target.  */
+#define GC_MINOR_FEATURES0_A8_TARGET_SUPPORT                             29 : 29
+#define GC_MINOR_FEATURES0_A8_TARGET_SUPPORT_End                              29
+#define GC_MINOR_FEATURES0_A8_TARGET_SUPPORT_Start                            29
+#define GC_MINOR_FEATURES0_A8_TARGET_SUPPORT_Type                            U01
+#define   GC_MINOR_FEATURES0_A8_TARGET_SUPPORT_NONE                          0x0
+#define   GC_MINOR_FEATURES0_A8_TARGET_SUPPORT_AVAILABLE                     0x1
+
+/* Correct stencil behavior in depth only. */
+#define GC_MINOR_FEATURES0_CORRECT_STENCIL                               30 : 30
+#define GC_MINOR_FEATURES0_CORRECT_STENCIL_End                                30
+#define GC_MINOR_FEATURES0_CORRECT_STENCIL_Start                              30
+#define GC_MINOR_FEATURES0_CORRECT_STENCIL_Type                              U01
+#define   GC_MINOR_FEATURES0_CORRECT_STENCIL_NONE                            0x0
+#define   GC_MINOR_FEATURES0_CORRECT_STENCIL_AVAILABLE                       0x1
+
+/* Enhance VR and add a mode to walk 16 pixels in 16-bit mode in Vertical     **
+** pass to improve $ hit rate when rotating 90/270.                           */
+#define GC_MINOR_FEATURES0_ENHANCE_VR                                    31 : 31
+#define GC_MINOR_FEATURES0_ENHANCE_VR_End                                     31
+#define GC_MINOR_FEATURES0_ENHANCE_VR_Start                                   31
+#define GC_MINOR_FEATURES0_ENHANCE_VR_Type                                   U01
+#define   GC_MINOR_FEATURES0_ENHANCE_VR_NONE                                 0x0
+#define   GC_MINOR_FEATURES0_ENHANCE_VR_AVAILABLE                            0x1
+
+/*******************************************************************************
+** Register GCMinorFeatures1
+*/
+
+/* Shows which features are enabled in this chip. This register has no set
+** reset value. It varies with the implementation.
+*/
+
+#define GC_MINOR_FEATURES1_Address                                       0x00074
+#define GC_MINOR_FEATURES1_MSB                                                15
+#define GC_MINOR_FEATURES1_LSB                                                 0
+#define GC_MINOR_FEATURES1_BLK                                                 0
+#define GC_MINOR_FEATURES1_Count                                               1
+#define GC_MINOR_FEATURES1_FieldMask                                  0xFFFFFFFF
+#define GC_MINOR_FEATURES1_ReadMask                                   0xFFFFFFFF
+#define GC_MINOR_FEATURES1_WriteMask                                  0x00000000
+#define GC_MINOR_FEATURES1_ResetValue                                 0x00000000
+
+/* Resolve UV swizzle. */
+#define GC_MINOR_FEATURES1_RSUV_SWIZZLE                                    0 : 0
+#define GC_MINOR_FEATURES1_RSUV_SWIZZLE_End                                    0
+#define GC_MINOR_FEATURES1_RSUV_SWIZZLE_Start                                  0
+#define GC_MINOR_FEATURES1_RSUV_SWIZZLE_Type                                 U01
+#define   GC_MINOR_FEATURES1_RSUV_SWIZZLE_NONE                               0x0
+#define   GC_MINOR_FEATURES1_RSUV_SWIZZLE_AVAILABLE                          0x1
+
+/* V2 compression. */
+#define GC_MINOR_FEATURES1_V2_COMPRESSION                                  1 : 1
+#define GC_MINOR_FEATURES1_V2_COMPRESSION_End                                  1
+#define GC_MINOR_FEATURES1_V2_COMPRESSION_Start                                1
+#define GC_MINOR_FEATURES1_V2_COMPRESSION_Type                               U01
+#define   GC_MINOR_FEATURES1_V2_COMPRESSION_NONE                             0x0
+#define   GC_MINOR_FEATURES1_V2_COMPRESSION_AVAILABLE                        0x1
+
+/* Double buffering support for VG (second TS-->VG semaphore is present). */
+#define GC_MINOR_FEATURES1_VG_DOUBLE_BUFFER                                2 : 2
+#define GC_MINOR_FEATURES1_VG_DOUBLE_BUFFER_End                                2
+#define GC_MINOR_FEATURES1_VG_DOUBLE_BUFFER_Start                              2
+#define GC_MINOR_FEATURES1_VG_DOUBLE_BUFFER_Type                             U01
+#define   GC_MINOR_FEATURES1_VG_DOUBLE_BUFFER_NONE                           0x0
+#define   GC_MINOR_FEATURES1_VG_DOUBLE_BUFFER_AVAILABLE                      0x1
+
+#define GC_MINOR_FEATURES1_BUG_FIXES1                                      3 : 3
+#define GC_MINOR_FEATURES1_BUG_FIXES1_End                                      3
+#define GC_MINOR_FEATURES1_BUG_FIXES1_Start                                    3
+#define GC_MINOR_FEATURES1_BUG_FIXES1_Type                                   U01
+#define   GC_MINOR_FEATURES1_BUG_FIXES1_NONE                                 0x0
+#define   GC_MINOR_FEATURES1_BUG_FIXES1_AVAILABLE                            0x1
+
+#define GC_MINOR_FEATURES1_BUG_FIXES2                                      4 : 4
+#define GC_MINOR_FEATURES1_BUG_FIXES2_End                                      4
+#define GC_MINOR_FEATURES1_BUG_FIXES2_Start                                    4
+#define GC_MINOR_FEATURES1_BUG_FIXES2_Type                                   U01
+#define   GC_MINOR_FEATURES1_BUG_FIXES2_NONE                                 0x0
+#define   GC_MINOR_FEATURES1_BUG_FIXES2_AVAILABLE                            0x1
+
+/* Texture has stride and memory addressing. */
+#define GC_MINOR_FEATURES1_TEXTURE_STRIDE                                  5 : 5
+#define GC_MINOR_FEATURES1_TEXTURE_STRIDE_End                                  5
+#define GC_MINOR_FEATURES1_TEXTURE_STRIDE_Start                                5
+#define GC_MINOR_FEATURES1_TEXTURE_STRIDE_Type                               U01
+#define   GC_MINOR_FEATURES1_TEXTURE_STRIDE_NONE                             0x0
+#define   GC_MINOR_FEATURES1_TEXTURE_STRIDE_AVAILABLE                        0x1
+
+#define GC_MINOR_FEATURES1_BUG_FIXES3                                      6 : 6
+#define GC_MINOR_FEATURES1_BUG_FIXES3_End                                      6
+#define GC_MINOR_FEATURES1_BUG_FIXES3_Start                                    6
+#define GC_MINOR_FEATURES1_BUG_FIXES3_Type                                   U01
+#define   GC_MINOR_FEATURES1_BUG_FIXES3_NONE                                 0x0
+#define   GC_MINOR_FEATURES1_BUG_FIXES3_AVAILABLE                            0x1
+
+#define GC_MINOR_FEATURES1_CORRECT_AUTO_DISABLE                            7 : 7
+#define GC_MINOR_FEATURES1_CORRECT_AUTO_DISABLE_End                            7
+#define GC_MINOR_FEATURES1_CORRECT_AUTO_DISABLE_Start                          7
+#define GC_MINOR_FEATURES1_CORRECT_AUTO_DISABLE_Type                         U01
+#define   GC_MINOR_FEATURES1_CORRECT_AUTO_DISABLE_NONE                       0x0
+#define   GC_MINOR_FEATURES1_CORRECT_AUTO_DISABLE_AVAILABLE                  0x1
+
+#define GC_MINOR_FEATURES1_AUTO_RESTART_TS                                 8 : 8
+#define GC_MINOR_FEATURES1_AUTO_RESTART_TS_End                                 8
+#define GC_MINOR_FEATURES1_AUTO_RESTART_TS_Start                               8
+#define GC_MINOR_FEATURES1_AUTO_RESTART_TS_Type                              U01
+#define   GC_MINOR_FEATURES1_AUTO_RESTART_TS_NONE                            0x0
+#define   GC_MINOR_FEATURES1_AUTO_RESTART_TS_AVAILABLE                       0x1
+
+#define GC_MINOR_FEATURES1_BUG_FIXES4                                      9 : 9
+#define GC_MINOR_FEATURES1_BUG_FIXES4_End                                      9
+#define GC_MINOR_FEATURES1_BUG_FIXES4_Start                                    9
+#define GC_MINOR_FEATURES1_BUG_FIXES4_Type                                   U01
+#define   GC_MINOR_FEATURES1_BUG_FIXES4_NONE                                 0x0
+#define   GC_MINOR_FEATURES1_BUG_FIXES4_AVAILABLE                            0x1
+
+#define GC_MINOR_FEATURES1_L2_WINDOWING                                  10 : 10
+#define GC_MINOR_FEATURES1_L2_WINDOWING_End                                   10
+#define GC_MINOR_FEATURES1_L2_WINDOWING_Start                                 10
+#define GC_MINOR_FEATURES1_L2_WINDOWING_Type                                 U01
+#define   GC_MINOR_FEATURES1_L2_WINDOWING_NONE                               0x0
+#define   GC_MINOR_FEATURES1_L2_WINDOWING_AVAILABLE                          0x1
+
+#define GC_MINOR_FEATURES1_HALF_FLOAT_PIPE                               11 : 11
+#define GC_MINOR_FEATURES1_HALF_FLOAT_PIPE_End                                11
+#define GC_MINOR_FEATURES1_HALF_FLOAT_PIPE_Start                              11
+#define GC_MINOR_FEATURES1_HALF_FLOAT_PIPE_Type                              U01
+#define   GC_MINOR_FEATURES1_HALF_FLOAT_PIPE_NONE                            0x0
+#define   GC_MINOR_FEATURES1_HALF_FLOAT_PIPE_AVAILABLE                       0x1
+
+#define GC_MINOR_FEATURES1_PIXEL_DITHER                                  12 : 12
+#define GC_MINOR_FEATURES1_PIXEL_DITHER_End                                   12
+#define GC_MINOR_FEATURES1_PIXEL_DITHER_Start                                 12
+#define GC_MINOR_FEATURES1_PIXEL_DITHER_Type                                 U01
+#define   GC_MINOR_FEATURES1_PIXEL_DITHER_NONE                               0x0
+#define   GC_MINOR_FEATURES1_PIXEL_DITHER_AVAILABLE                          0x1
+
+#define GC_MINOR_FEATURES1_TWO_STENCIL_REFERENCE                         13 : 13
+#define GC_MINOR_FEATURES1_TWO_STENCIL_REFERENCE_End                          13
+#define GC_MINOR_FEATURES1_TWO_STENCIL_REFERENCE_Start                        13
+#define GC_MINOR_FEATURES1_TWO_STENCIL_REFERENCE_Type                        U01
+#define   GC_MINOR_FEATURES1_TWO_STENCIL_REFERENCE_NONE                      0x0
+#define   GC_MINOR_FEATURES1_TWO_STENCIL_REFERENCE_AVAILABLE                 0x1
+
+#define GC_MINOR_FEATURES1_EXTENDED_PIXEL_FORMAT                         14 : 14
+#define GC_MINOR_FEATURES1_EXTENDED_PIXEL_FORMAT_End                          14
+#define GC_MINOR_FEATURES1_EXTENDED_PIXEL_FORMAT_Start                        14
+#define GC_MINOR_FEATURES1_EXTENDED_PIXEL_FORMAT_Type                        U01
+#define   GC_MINOR_FEATURES1_EXTENDED_PIXEL_FORMAT_NONE                      0x0
+#define   GC_MINOR_FEATURES1_EXTENDED_PIXEL_FORMAT_AVAILABLE                 0x1
+
+/* EEZ and HZ are correct. */
+#define GC_MINOR_FEATURES1_CORRECT_MIN_MAX_DEPTH                         15 : 15
+#define GC_MINOR_FEATURES1_CORRECT_MIN_MAX_DEPTH_End                          15
+#define GC_MINOR_FEATURES1_CORRECT_MIN_MAX_DEPTH_Start                        15
+#define GC_MINOR_FEATURES1_CORRECT_MIN_MAX_DEPTH_Type                        U01
+#define   GC_MINOR_FEATURES1_CORRECT_MIN_MAX_DEPTH_NONE                      0x0
+#define   GC_MINOR_FEATURES1_CORRECT_MIN_MAX_DEPTH_AVAILABLE                 0x1
+
+/* Dither and filter+alpha available. */
+#define GC_MINOR_FEATURES1_DITHER_AND_FILTER_PLUS_ALPHA_2D               16 : 16
+#define GC_MINOR_FEATURES1_DITHER_AND_FILTER_PLUS_ALPHA_2D_End                16
+#define GC_MINOR_FEATURES1_DITHER_AND_FILTER_PLUS_ALPHA_2D_Start              16
+#define GC_MINOR_FEATURES1_DITHER_AND_FILTER_PLUS_ALPHA_2D_Type              U01
+#define   GC_MINOR_FEATURES1_DITHER_AND_FILTER_PLUS_ALPHA_2D_NONE            0x0
+#define   GC_MINOR_FEATURES1_DITHER_AND_FILTER_PLUS_ALPHA_2D_AVAILABLE       0x1
+
+#define GC_MINOR_FEATURES1_BUG_FIXES5                                    17 : 17
+#define GC_MINOR_FEATURES1_BUG_FIXES5_End                                     17
+#define GC_MINOR_FEATURES1_BUG_FIXES5_Start                                   17
+#define GC_MINOR_FEATURES1_BUG_FIXES5_Type                                   U01
+#define   GC_MINOR_FEATURES1_BUG_FIXES5_NONE                                 0x0
+#define   GC_MINOR_FEATURES1_BUG_FIXES5_AVAILABLE                            0x1
+
+#define GC_MINOR_FEATURES1_NEW_2D                                        18 : 18
+#define GC_MINOR_FEATURES1_NEW_2D_End                                         18
+#define GC_MINOR_FEATURES1_NEW_2D_Start                                       18
+#define GC_MINOR_FEATURES1_NEW_2D_Type                                       U01
+#define   GC_MINOR_FEATURES1_NEW_2D_NONE                                     0x0
+#define   GC_MINOR_FEATURES1_NEW_2D_AVAILABLE                                0x1
+
+#define GC_MINOR_FEATURES1_NEW_FLOATING_POINT_ARITHMETIC                 19 : 19
+#define GC_MINOR_FEATURES1_NEW_FLOATING_POINT_ARITHMETIC_End                  19
+#define GC_MINOR_FEATURES1_NEW_FLOATING_POINT_ARITHMETIC_Start                19
+#define GC_MINOR_FEATURES1_NEW_FLOATING_POINT_ARITHMETIC_Type                U01
+#define   GC_MINOR_FEATURES1_NEW_FLOATING_POINT_ARITHMETIC_NONE              0x0
+#define   GC_MINOR_FEATURES1_NEW_FLOATING_POINT_ARITHMETIC_AVAILABLE         0x1
+
+#define GC_MINOR_FEATURES1_TEXTURE_HORIZONTAL_ALIGNMENT_SELECT           20 : 20
+#define GC_MINOR_FEATURES1_TEXTURE_HORIZONTAL_ALIGNMENT_SELECT_End            20
+#define GC_MINOR_FEATURES1_TEXTURE_HORIZONTAL_ALIGNMENT_SELECT_Start          20
+#define GC_MINOR_FEATURES1_TEXTURE_HORIZONTAL_ALIGNMENT_SELECT_Type          U01
+#define   GC_MINOR_FEATURES1_TEXTURE_HORIZONTAL_ALIGNMENT_SELECT_NONE        0x0
+#define   GC_MINOR_FEATURES1_TEXTURE_HORIZONTAL_ALIGNMENT_SELECT_AVAILABLE   0x1
+
+#define GC_MINOR_FEATURES1_NON_POWER_OF_TWO                              21 : 21
+#define GC_MINOR_FEATURES1_NON_POWER_OF_TWO_End                               21
+#define GC_MINOR_FEATURES1_NON_POWER_OF_TWO_Start                             21
+#define GC_MINOR_FEATURES1_NON_POWER_OF_TWO_Type                             U01
+#define   GC_MINOR_FEATURES1_NON_POWER_OF_TWO_NONE                           0x0
+#define   GC_MINOR_FEATURES1_NON_POWER_OF_TWO_AVAILABLE                      0x1
+
+#define GC_MINOR_FEATURES1_LINEAR_TEXTURE_SUPPORT                        22 : 22
+#define GC_MINOR_FEATURES1_LINEAR_TEXTURE_SUPPORT_End                         22
+#define GC_MINOR_FEATURES1_LINEAR_TEXTURE_SUPPORT_Start                       22
+#define GC_MINOR_FEATURES1_LINEAR_TEXTURE_SUPPORT_Type                       U01
+#define   GC_MINOR_FEATURES1_LINEAR_TEXTURE_SUPPORT_NONE                     0x0
+#define   GC_MINOR_FEATURES1_LINEAR_TEXTURE_SUPPORT_AVAILABLE                0x1
+
+#define GC_MINOR_FEATURES1_HALTI0                                        23 : 23
+#define GC_MINOR_FEATURES1_HALTI0_End                                         23
+#define GC_MINOR_FEATURES1_HALTI0_Start                                       23
+#define GC_MINOR_FEATURES1_HALTI0_Type                                       U01
+#define   GC_MINOR_FEATURES1_HALTI0_NONE                                     0x0
+#define   GC_MINOR_FEATURES1_HALTI0_AVAILABLE                                0x1
+
+#define GC_MINOR_FEATURES1_CORRECT_OVERFLOW_VG                           24 : 24
+#define GC_MINOR_FEATURES1_CORRECT_OVERFLOW_VG_End                            24
+#define GC_MINOR_FEATURES1_CORRECT_OVERFLOW_VG_Start                          24
+#define GC_MINOR_FEATURES1_CORRECT_OVERFLOW_VG_Type                          U01
+#define   GC_MINOR_FEATURES1_CORRECT_OVERFLOW_VG_NONE                        0x0
+#define   GC_MINOR_FEATURES1_CORRECT_OVERFLOW_VG_AVAILABLE                   0x1
+
+#define GC_MINOR_FEATURES1_NEGATIVE_LOG_FIX                              25 : 25
+#define GC_MINOR_FEATURES1_NEGATIVE_LOG_FIX_End                               25
+#define GC_MINOR_FEATURES1_NEGATIVE_LOG_FIX_Start                             25
+#define GC_MINOR_FEATURES1_NEGATIVE_LOG_FIX_Type                             U01
+#define   GC_MINOR_FEATURES1_NEGATIVE_LOG_FIX_NONE                           0x0
+#define   GC_MINOR_FEATURES1_NEGATIVE_LOG_FIX_AVAILABLE                      0x1
+
+#define GC_MINOR_FEATURES1_RESOLVE_OFFSET                                26 : 26
+#define GC_MINOR_FEATURES1_RESOLVE_OFFSET_End                                 26
+#define GC_MINOR_FEATURES1_RESOLVE_OFFSET_Start                               26
+#define GC_MINOR_FEATURES1_RESOLVE_OFFSET_Type                               U01
+#define   GC_MINOR_FEATURES1_RESOLVE_OFFSET_NONE                             0x0
+#define   GC_MINOR_FEATURES1_RESOLVE_OFFSET_AVAILABLE                        0x1
+
+#define GC_MINOR_FEATURES1_OK_TO_GATE_AXI_CLOCK                          27 : 27
+#define GC_MINOR_FEATURES1_OK_TO_GATE_AXI_CLOCK_End                           27
+#define GC_MINOR_FEATURES1_OK_TO_GATE_AXI_CLOCK_Start                         27
+#define GC_MINOR_FEATURES1_OK_TO_GATE_AXI_CLOCK_Type                         U01
+#define   GC_MINOR_FEATURES1_OK_TO_GATE_AXI_CLOCK_NONE                       0x0
+#define   GC_MINOR_FEATURES1_OK_TO_GATE_AXI_CLOCK_AVAILABLE                  0x1
+
+#define GC_MINOR_FEATURES1_MMU                                           28 : 28
+#define GC_MINOR_FEATURES1_MMU_End                                            28
+#define GC_MINOR_FEATURES1_MMU_Start                                          28
+#define GC_MINOR_FEATURES1_MMU_Type                                          U01
+#define   GC_MINOR_FEATURES1_MMU_NONE                                        0x0
+#define   GC_MINOR_FEATURES1_MMU_AVAILABLE                                   0x1
+
+#define GC_MINOR_FEATURES1_WIDE_LINE                                     29 : 29
+#define GC_MINOR_FEATURES1_WIDE_LINE_End                                      29
+#define GC_MINOR_FEATURES1_WIDE_LINE_Start                                    29
+#define GC_MINOR_FEATURES1_WIDE_LINE_Type                                    U01
+#define   GC_MINOR_FEATURES1_WIDE_LINE_NONE                                  0x0
+#define   GC_MINOR_FEATURES1_WIDE_LINE_AVAILABLE                             0x1
+
+#define GC_MINOR_FEATURES1_BUG_FIXES6                                    30 : 30
+#define GC_MINOR_FEATURES1_BUG_FIXES6_End                                     30
+#define GC_MINOR_FEATURES1_BUG_FIXES6_Start                                   30
+#define GC_MINOR_FEATURES1_BUG_FIXES6_Type                                   U01
+#define   GC_MINOR_FEATURES1_BUG_FIXES6_NONE                                 0x0
+#define   GC_MINOR_FEATURES1_BUG_FIXES6_AVAILABLE                            0x1
+
+#define GC_MINOR_FEATURES1_FC_FLUSH_STALL                                31 : 31
+#define GC_MINOR_FEATURES1_FC_FLUSH_STALL_End                                 31
+#define GC_MINOR_FEATURES1_FC_FLUSH_STALL_Start                               31
+#define GC_MINOR_FEATURES1_FC_FLUSH_STALL_Type                               U01
+#define   GC_MINOR_FEATURES1_FC_FLUSH_STALL_NONE                             0x0
+#define   GC_MINOR_FEATURES1_FC_FLUSH_STALL_AVAILABLE                        0x1
+
+/*******************************************************************************
+** Register GCResetMemCounters
+*/
+
+/* Writing 1 will reset the counters and stop counting. Write 0 to start
+** counting again.  This register is write only so it has no reset value.
+*/
+
+#define GC_RESET_MEM_COUNTERS_Address                                    0x0003C
+#define GC_RESET_MEM_COUNTERS_MSB                                             15
+#define GC_RESET_MEM_COUNTERS_LSB                                              0
+#define GC_RESET_MEM_COUNTERS_BLK                                              0
+#define GC_RESET_MEM_COUNTERS_Count                                            1
+#define GC_RESET_MEM_COUNTERS_FieldMask                               0x00000001
+#define GC_RESET_MEM_COUNTERS_ReadMask                                0x00000000
+#define GC_RESET_MEM_COUNTERS_WriteMask                               0x00000001
+#define GC_RESET_MEM_COUNTERS_ResetValue                              0x00000000
+
+#define GC_RESET_MEM_COUNTERS_RESET                                        0 : 0
+#define GC_RESET_MEM_COUNTERS_RESET_End                                        0
+#define GC_RESET_MEM_COUNTERS_RESET_Start                                      0
+#define GC_RESET_MEM_COUNTERS_RESET_Type                                     U01
+
+/*******************************************************************************
+** Register gcTotalReads
+*/
+
+/* Total reads in terms of 64bits. */
+
+#define GC_TOTAL_READS_Address                                           0x00040
+#define GC_TOTAL_READS_MSB                                                    15
+#define GC_TOTAL_READS_LSB                                                     0
+#define GC_TOTAL_READS_BLK                                                     0
+#define GC_TOTAL_READS_Count                                                   1
+#define GC_TOTAL_READS_FieldMask                                      0xFFFFFFFF
+#define GC_TOTAL_READS_ReadMask                                       0xFFFFFFFF
+#define GC_TOTAL_READS_WriteMask                                      0x00000000
+#define GC_TOTAL_READS_ResetValue                                     0x00000000
+
+#define GC_TOTAL_READS_COUNT                                              31 : 0
+#define GC_TOTAL_READS_COUNT_End                                              31
+#define GC_TOTAL_READS_COUNT_Start                                             0
+#define GC_TOTAL_READS_COUNT_Type                                            U32
+
+/*******************************************************************************
+** Register gcTotalWrites
+*/
+
+/* Total writes in terms of 64bits. */
+
+#define GC_TOTAL_WRITES_Address                                          0x00044
+#define GC_TOTAL_WRITES_MSB                                                   15
+#define GC_TOTAL_WRITES_LSB                                                    0
+#define GC_TOTAL_WRITES_BLK                                                    0
+#define GC_TOTAL_WRITES_Count                                                  1
+#define GC_TOTAL_WRITES_FieldMask                                     0xFFFFFFFF
+#define GC_TOTAL_WRITES_ReadMask                                      0xFFFFFFFF
+#define GC_TOTAL_WRITES_WriteMask                                     0x00000000
+#define GC_TOTAL_WRITES_ResetValue                                    0x00000000
+
+#define GC_TOTAL_WRITES_COUNT                                             31 : 0
+#define GC_TOTAL_WRITES_COUNT_End                                             31
+#define GC_TOTAL_WRITES_COUNT_Start                                            0
+#define GC_TOTAL_WRITES_COUNT_Type                                           U32
+
+/*******************************************************************************
+** Register gcTotalWriteBursts
+*/
+
+/* Total write Data Count in terms of 64bits value. */
+
+#define GC_TOTAL_WRITE_BURSTS_Address                                    0x0004C
+#define GC_TOTAL_WRITE_BURSTS_MSB                                             15
+#define GC_TOTAL_WRITE_BURSTS_LSB                                              0
+#define GC_TOTAL_WRITE_BURSTS_BLK                                              0
+#define GC_TOTAL_WRITE_BURSTS_Count                                            1
+#define GC_TOTAL_WRITE_BURSTS_FieldMask                               0xFFFFFFFF
+#define GC_TOTAL_WRITE_BURSTS_ReadMask                                0xFFFFFFFF
+#define GC_TOTAL_WRITE_BURSTS_WriteMask                               0x00000000
+#define GC_TOTAL_WRITE_BURSTS_ResetValue                              0x00000000
+
+#define GC_TOTAL_WRITE_BURSTS_COUNT                                       31 : 0
+#define GC_TOTAL_WRITE_BURSTS_COUNT_End                                       31
+#define GC_TOTAL_WRITE_BURSTS_COUNT_Start                                      0
+#define GC_TOTAL_WRITE_BURSTS_COUNT_Type                                     U32
+
+/*******************************************************************************
+** Register gcTotalWriteReqs
+*/
+
+/* Total write Request Count. */
+
+#define GC_TOTAL_WRITE_REQS_Address                                      0x00050
+#define GC_TOTAL_WRITE_REQS_MSB                                               15
+#define GC_TOTAL_WRITE_REQS_LSB                                                0
+#define GC_TOTAL_WRITE_REQS_BLK                                                0
+#define GC_TOTAL_WRITE_REQS_Count                                              1
+#define GC_TOTAL_WRITE_REQS_FieldMask                                 0xFFFFFFFF
+#define GC_TOTAL_WRITE_REQS_ReadMask                                  0xFFFFFFFF
+#define GC_TOTAL_WRITE_REQS_WriteMask                                 0x00000000
+#define GC_TOTAL_WRITE_REQS_ResetValue                                0x00000000
+
+#define GC_TOTAL_WRITE_REQS_COUNT                                         31 : 0
+#define GC_TOTAL_WRITE_REQS_COUNT_End                                         31
+#define GC_TOTAL_WRITE_REQS_COUNT_Start                                        0
+#define GC_TOTAL_WRITE_REQS_COUNT_Type                                       U32
+
+/*******************************************************************************
+** Register gcTotalReadBursts
+*/
+
+/* Total Read Data Count in terms of 64bits. */
+
+#define GC_TOTAL_READ_BURSTS_Address                                     0x00058
+#define GC_TOTAL_READ_BURSTS_MSB                                              15
+#define GC_TOTAL_READ_BURSTS_LSB                                               0
+#define GC_TOTAL_READ_BURSTS_BLK                                               0
+#define GC_TOTAL_READ_BURSTS_Count                                             1
+#define GC_TOTAL_READ_BURSTS_FieldMask                                0xFFFFFFFF
+#define GC_TOTAL_READ_BURSTS_ReadMask                                 0xFFFFFFFF
+#define GC_TOTAL_READ_BURSTS_WriteMask                                0x00000000
+#define GC_TOTAL_READ_BURSTS_ResetValue                               0x00000000
+
+#define GC_TOTAL_READ_BURSTS_COUNT                                        31 : 0
+#define GC_TOTAL_READ_BURSTS_COUNT_End                                        31
+#define GC_TOTAL_READ_BURSTS_COUNT_Start                                       0
+#define GC_TOTAL_READ_BURSTS_COUNT_Type                                      U32
+
+/*******************************************************************************
+** Register gcTotalReadReqs
+*/
+
+/* Total Read Request Count. */
+
+#define GC_TOTAL_READ_REQS_Address                                       0x0005C
+#define GC_TOTAL_READ_REQS_MSB                                                15
+#define GC_TOTAL_READ_REQS_LSB                                                 0
+#define GC_TOTAL_READ_REQS_BLK                                                 0
+#define GC_TOTAL_READ_REQS_Count                                               1
+#define GC_TOTAL_READ_REQS_FieldMask                                  0xFFFFFFFF
+#define GC_TOTAL_READ_REQS_ReadMask                                   0xFFFFFFFF
+#define GC_TOTAL_READ_REQS_WriteMask                                  0x00000000
+#define GC_TOTAL_READ_REQS_ResetValue                                 0x00000000
+
+#define GC_TOTAL_READ_REQS_COUNT                                          31 : 0
+#define GC_TOTAL_READ_REQS_COUNT_End                                          31
+#define GC_TOTAL_READ_REQS_COUNT_Start                                         0
+#define GC_TOTAL_READ_REQS_COUNT_Type                                        U32
+
+/*******************************************************************************
+** Register gcTotalReadLasts
+*/
+
+/* Total RLAST Count. This is used to match with GCTotalReadReqs. */
+
+#define GC_TOTAL_READ_LASTS_Address                                      0x00060
+#define GC_TOTAL_READ_LASTS_MSB                                               15
+#define GC_TOTAL_READ_LASTS_LSB                                                0
+#define GC_TOTAL_READ_LASTS_BLK                                                0
+#define GC_TOTAL_READ_LASTS_Count                                              1
+#define GC_TOTAL_READ_LASTS_FieldMask                                 0xFFFFFFFF
+#define GC_TOTAL_READ_LASTS_ReadMask                                  0xFFFFFFFF
+#define GC_TOTAL_READ_LASTS_WriteMask                                 0x00000000
+#define GC_TOTAL_READ_LASTS_ResetValue                                0x00000000
+
+#define GC_TOTAL_READ_LASTS_COUNT                                         31 : 0
+#define GC_TOTAL_READ_LASTS_COUNT_End                                         31
+#define GC_TOTAL_READ_LASTS_COUNT_Start                                        0
+#define GC_TOTAL_READ_LASTS_COUNT_Type                                       U32
+
+/*******************************************************************************
+** Register gcTotalCycles
+*/
+
+/* Total cycles. This register is a free running counter.  It can be reset by
+** writing 0 to it.
+*/
+
+#define GC_TOTAL_CYCLES_Address                                          0x00078
+#define GC_TOTAL_CYCLES_MSB                                                   15
+#define GC_TOTAL_CYCLES_LSB                                                    0
+#define GC_TOTAL_CYCLES_BLK                                                    0
+#define GC_TOTAL_CYCLES_Count                                                  1
+#define GC_TOTAL_CYCLES_FieldMask                                     0xFFFFFFFF
+#define GC_TOTAL_CYCLES_ReadMask                                      0xFFFFFFFF
+#define GC_TOTAL_CYCLES_WriteMask                                     0xFFFFFFFF
+#define GC_TOTAL_CYCLES_ResetValue                                    0x00000000
+
+#define GC_TOTAL_CYCLES_CYCLES                                            31 : 0
+#define GC_TOTAL_CYCLES_CYCLES_End                                            31
+#define GC_TOTAL_CYCLES_CYCLES_Start                                           0
+#define GC_TOTAL_CYCLES_CYCLES_Type                                          U32
+
+/*******************************************************************************
+** Register gcTotalIdleCycles
+*/
+
+/* Total cycles where the GPU is idle. It is reset when  gcTotalCycles register
+** is written to. It looks at all the blocks but FE when determining the IP is
+** idle.
+*/
+
+#define GC_TOTAL_IDLE_CYCLES_Address                                     0x0007C
+#define GC_TOTAL_IDLE_CYCLES_MSB                                              15
+#define GC_TOTAL_IDLE_CYCLES_LSB                                               0
+#define GC_TOTAL_IDLE_CYCLES_BLK                                               0
+#define GC_TOTAL_IDLE_CYCLES_Count                                             1
+#define GC_TOTAL_IDLE_CYCLES_FieldMask                                0xFFFFFFFF
+#define GC_TOTAL_IDLE_CYCLES_ReadMask                                 0xFFFFFFFF
+#define GC_TOTAL_IDLE_CYCLES_WriteMask                                0xFFFFFFFF
+#define GC_TOTAL_IDLE_CYCLES_ResetValue                               0x00000000
+
+#define GC_TOTAL_IDLE_CYCLES_CYCLES                                       31 : 0
+#define GC_TOTAL_IDLE_CYCLES_CYCLES_End                                       31
+#define GC_TOTAL_IDLE_CYCLES_CYCLES_Start                                      0
+#define GC_TOTAL_IDLE_CYCLES_CYCLES_Type                                     U32
+
+/*******************************************************************************
+** Command gcregCommandLoadState
+*/
+
+/* When enabled, convert 16.16 fixed point into 32-bit floating point. */
+#define GCREG_COMMAND_LOAD_STATE_COMMAND_FLOAT                           26 : 26
+#define GCREG_COMMAND_LOAD_STATE_COMMAND_FLOAT_End                            26
+#define GCREG_COMMAND_LOAD_STATE_COMMAND_FLOAT_Start                          26
+#define GCREG_COMMAND_LOAD_STATE_COMMAND_FLOAT_Type                          U01
+#define   GCREG_COMMAND_LOAD_STATE_COMMAND_FLOAT_NORMAL                      0x0
+#define   GCREG_COMMAND_LOAD_STATE_COMMAND_FLOAT_FIXED16_DOT16               0x1
+
+/* Number of states. 0 = 1024. */
+#define GCREG_COMMAND_LOAD_STATE_COMMAND_COUNT                           25 : 16
+#define GCREG_COMMAND_LOAD_STATE_COMMAND_COUNT_End                            25
+#define GCREG_COMMAND_LOAD_STATE_COMMAND_COUNT_Start                          16
+#define GCREG_COMMAND_LOAD_STATE_COMMAND_COUNT_Type                          U10
+
+/* Starting state address. */
+#define GCREG_COMMAND_LOAD_STATE_COMMAND_ADDRESS                          15 : 0
+#define GCREG_COMMAND_LOAD_STATE_COMMAND_ADDRESS_End                          15
+#define GCREG_COMMAND_LOAD_STATE_COMMAND_ADDRESS_Start                         0
+#define GCREG_COMMAND_LOAD_STATE_COMMAND_ADDRESS_Type                        U16
+
+#define GCREG_COMMAND_LOAD_STATE_COMMAND_OPCODE                          31 : 27
+#define GCREG_COMMAND_LOAD_STATE_COMMAND_OPCODE_End                           31
+#define GCREG_COMMAND_LOAD_STATE_COMMAND_OPCODE_Start                         27
+#define GCREG_COMMAND_LOAD_STATE_COMMAND_OPCODE_Type                         U05
+#define   GCREG_COMMAND_LOAD_STATE_COMMAND_OPCODE_LOAD_STATE                0x01
+
+struct gccmdldstate {
+	/* gcregCommandLoadState:GCREG_COMMAND_LOAD_STATE_COMMAND_ADDRESS */
+	unsigned int address:16;
+
+	/* gcregCommandLoadState:GCREG_COMMAND_LOAD_STATE_COMMAND_COUNT */
+	unsigned int count:10;
+
+	/* gcregCommandLoadState:GCREG_COMMAND_LOAD_STATE_COMMAND_FLOAT */
+	unsigned int fixed:1;
+
+	/* gcregCommandLoadState:GCREG_COMMAND_LOAD_STATE_COMMAND_OPCODE */
+	unsigned int opcode:5;
+};
+
+#define GCLDSTATE(Address, Count) \
+{ \
+	/* gcregCommandLoadState:GCREG_COMMAND_LOAD_STATE_COMMAND_ADDRESS */ \
+	Address, \
+	\
+	/* gcregCommandLoadState:GCREG_COMMAND_LOAD_STATE_COMMAND_COUNT */ \
+	Count, \
+	\
+	/* gcregCommandLoadState:GCREG_COMMAND_LOAD_STATE_COMMAND_FLOAT */ \
+	GCREG_COMMAND_LOAD_STATE_COMMAND_FLOAT_NORMAL, \
+	\
+	/* gcregCommandLoadState:GCREG_COMMAND_LOAD_STATE_COMMAND_OPCODE */ \
+	GCREG_COMMAND_LOAD_STATE_COMMAND_OPCODE_LOAD_STATE \
+}
+
+/*******************************************************************************
+** Command gcregCommandEnd
+*/
+
+/* Send event when END is completed. */
+#define GCREG_COMMAND_END_COMMAND_EVENT_ENABLE                             8 : 8
+#define GCREG_COMMAND_END_COMMAND_EVENT_ENABLE_End                             8
+#define GCREG_COMMAND_END_COMMAND_EVENT_ENABLE_Start                           8
+#define GCREG_COMMAND_END_COMMAND_EVENT_ENABLE_Type                          U01
+
+/* Event ID to be send. */
+#define GCREG_COMMAND_END_COMMAND_EVENT_ID                                 4 : 0
+#define GCREG_COMMAND_END_COMMAND_EVENT_ID_End                                 4
+#define GCREG_COMMAND_END_COMMAND_EVENT_ID_Start                               0
+#define GCREG_COMMAND_END_COMMAND_EVENT_ID_Type                              U05
+
+#define GCREG_COMMAND_END_COMMAND_OPCODE                                 31 : 27
+#define GCREG_COMMAND_END_COMMAND_OPCODE_End                                  31
+#define GCREG_COMMAND_END_COMMAND_OPCODE_Start                                27
+#define GCREG_COMMAND_END_COMMAND_OPCODE_Type                                U05
+#define   GCREG_COMMAND_END_COMMAND_OPCODE_END                              0x02
+
+struct gcfldend {
+	/* gcregCommandEnd:GCREG_COMMAND_END_COMMAND_EVENT_ID */
+	unsigned int signalid:5;
+
+	/* gcregCommandEnd:reserved */
+	unsigned int _reserved_5_7:3;
+
+	/* gcregCommandEnd:GCREG_COMMAND_END_COMMAND_EVENT_ENABLE */
+	unsigned int signal:1;
+
+	/* gcregCommandEnd:reserved */
+	unsigned int _reserved_9_26:18;
+
+	/* gcregCommandEnd:GCREG_COMMAND_END_COMMAND_OPCODE */
+	unsigned int opcode:5;
+};
+
+struct gccmdend {
+	union {
+		struct gcfldend fld;
+		unsigned int raw;
+	}
+	cmd;
+
+	/* Alignment filler. */
+	unsigned int _filler;
+};
+
+static const struct gcfldend gcfldend = {
+	/* gcregCommandEnd:GCREG_COMMAND_END_COMMAND_EVENT_ID */
+	0,
+
+	/* gcregCommandEnd:reserved */
+	0,
+
+	/* gcregCommandEnd:GCREG_COMMAND_END_COMMAND_EVENT_ENABLE */
+	0,
+
+	/* gcregCommandEnd:reserved */
+	0,
+
+	/* gcregCommandEnd:GCREG_COMMAND_END_COMMAND_OPCODE */
+	GCREG_COMMAND_END_COMMAND_OPCODE_END
+};
+
+/*******************************************************************************
+** Command gcregCommandNop
+*/
+
+#define GCREG_COMMAND_NOP_COMMAND_OPCODE                                 31 : 27
+#define GCREG_COMMAND_NOP_COMMAND_OPCODE_End                                  31
+#define GCREG_COMMAND_NOP_COMMAND_OPCODE_Start                                27
+#define GCREG_COMMAND_NOP_COMMAND_OPCODE_Type                                U05
+#define   GCREG_COMMAND_NOP_COMMAND_OPCODE_NOP                              0x03
+
+struct gcfldnop {
+	/* gcregCommandNop:reserve */
+	unsigned int _reserved_0_26:27;
+
+	/* gcregCommandNop:GCREG_COMMAND_NOP_COMMAND_OPCODE */
+	unsigned int opcode:5;
+};
+
+struct gccmdnop {
+	union {
+		struct gcfldnop fld;
+		unsigned int raw;
+	}
+	cmd;
+
+	/* Alignment filler. */
+	unsigned int _filler;
+};
+
+static const struct gcfldnop gcfldnop = {
+	/* gcregCommandNop:reserve */
+	0,
+
+	/* gcregCommandNop:GCREG_COMMAND_NOP_COMMAND_OPCODE */
+	GCREG_COMMAND_NOP_COMMAND_OPCODE_NOP
+};
+
+/*******************************************************************************
+** Command gcregCommandStartDE
+*/
+
+/* Offset Command
+** ~~~~~~~~~~~~~~ */
+
+/* Number of 32-bit data words to send.
+** The data follows the rectangles, aligned at 64-bit.
+*/
+#define GCREG_COMMAND_START_DE_COMMAND_DATA_COUNT                        26 : 16
+#define GCREG_COMMAND_START_DE_COMMAND_DATA_COUNT_End                         26
+#define GCREG_COMMAND_START_DE_COMMAND_DATA_COUNT_Start                       16
+#define GCREG_COMMAND_START_DE_COMMAND_DATA_COUNT_Type                       U11
+
+/* Number of rectangles to send.
+** The rectangles follow the command, aligned at 64-bit.
+*/
+#define GCREG_COMMAND_START_DE_COMMAND_COUNT                              15 : 8
+#define GCREG_COMMAND_START_DE_COMMAND_COUNT_End                              15
+#define GCREG_COMMAND_START_DE_COMMAND_COUNT_Start                             8
+#define GCREG_COMMAND_START_DE_COMMAND_COUNT_Type                            U08
+
+#define GCREG_COMMAND_START_DE_COMMAND_OPCODE                            31 : 27
+#define GCREG_COMMAND_START_DE_COMMAND_OPCODE_End                             31
+#define GCREG_COMMAND_START_DE_COMMAND_OPCODE_Start                           27
+#define GCREG_COMMAND_START_DE_COMMAND_OPCODE_Type                           U05
+#define   GCREG_COMMAND_START_DE_COMMAND_OPCODE_START_DE                    0x04
+
+struct gcfldstartde {
+	/* gcregCommandStartDE:reserved */
+	unsigned int _reserved_0_7:8;
+
+	/* gcregCommandStartDE:GCREG_COMMAND_START_DE_COMMAND_COUNT */
+	unsigned int rectcount:8;
+
+	/* gcregCommandStartDE:GCREG_COMMAND_START_DE_COMMAND_DATA_COUNT */
+	unsigned int datacount:11;
+
+	/* gcregCommandStartDE:GCREG_COMMAND_START_DE_COMMAND_OPCODE */
+	unsigned int opcode:5;
+};
+
+struct gccmdstartde {
+	union {
+		struct gcfldstartde fld;
+		unsigned int raw;
+	} cmd;
+
+	/* Alignment filler. */
+	unsigned int _filler;
+};
+
+static const struct gcfldstartde gcfldstartde = {
+	/* gcregCommandStartDE:reserved */
+	0,
+
+	/* gcregCommandStartDE:GCREG_COMMAND_START_DE_COMMAND_COUNT */
+	1,
+
+	/* gcregCommandStartDE:GCREG_COMMAND_START_DE_COMMAND_DATA_COUNT */
+	0,
+
+	/* gcregCommandStartDE:GCREG_COMMAND_START_DE_COMMAND_OPCODE */
+	GCREG_COMMAND_START_DE_COMMAND_OPCODE_START_DE
+};
+
+/* Offset TopLeft
+** ~~~~~~~~~~~~~~ */
+
+#define GCREG_COMMAND_TOP_LEFT_Y                                         31 : 16
+#define GCREG_COMMAND_TOP_LEFT_Y_End                                          31
+#define GCREG_COMMAND_TOP_LEFT_Y_Start                                        16
+#define GCREG_COMMAND_TOP_LEFT_Y_Type                                        U16
+
+#define GCREG_COMMAND_TOP_LEFT_X                                          15 : 0
+#define GCREG_COMMAND_TOP_LEFT_X_End                                          15
+#define GCREG_COMMAND_TOP_LEFT_X_Start                                         0
+#define GCREG_COMMAND_TOP_LEFT_X_Type                                        U16
+
+/* Offset BottomRight
+** ~~~~~~~~~~~~~~~~~~ */
+
+#define GCREG_COMMAND_BOTTOM_RIGHT_Y                                     31 : 16
+#define GCREG_COMMAND_BOTTOM_RIGHT_Y_End                                      31
+#define GCREG_COMMAND_BOTTOM_RIGHT_Y_Start                                    16
+#define GCREG_COMMAND_BOTTOM_RIGHT_Y_Type                                    U16
+
+#define GCREG_COMMAND_BOTTOM_RIGHT_X                                      15 : 0
+#define GCREG_COMMAND_BOTTOM_RIGHT_X_End                                      15
+#define GCREG_COMMAND_BOTTOM_RIGHT_X_Start                                     0
+#define GCREG_COMMAND_BOTTOM_RIGHT_X_Type                                    U16
+
+struct gccmdstartderect {
+	/* GCREG_COMMAND_TOP_LEFT_X */
+	unsigned int left:16;
+
+	/* GCREG_COMMAND_TOP_LEFT_Y */
+	unsigned int top:16;
+
+	/* GCREG_COMMAND_BOTTOM_RIGHT_X */
+	unsigned int right:16;
+
+	/* GCREG_COMMAND_BOTTOM_RIGHT_Y */
+	unsigned int bottom:16;
+};
+
+/*******************************************************************************
+** Command gcregCommandWait
+*/
+
+/* Number of cycles to wait until the next command gets fetched. */
+#define GCREG_COMMAND_WAIT_COMMAND_DELAY                                  15 : 0
+#define GCREG_COMMAND_WAIT_COMMAND_DELAY_End                                  15
+#define GCREG_COMMAND_WAIT_COMMAND_DELAY_Start                                 0
+#define GCREG_COMMAND_WAIT_COMMAND_DELAY_Type                                U16
+
+#define GCREG_COMMAND_WAIT_COMMAND_OPCODE                                31 : 27
+#define GCREG_COMMAND_WAIT_COMMAND_OPCODE_End                                 31
+#define GCREG_COMMAND_WAIT_COMMAND_OPCODE_Start                               27
+#define GCREG_COMMAND_WAIT_COMMAND_OPCODE_Type                               U05
+#define   GCREG_COMMAND_WAIT_COMMAND_OPCODE_WAIT                            0x07
+
+struct gcfldwait {
+	/* gcregCommandWait:GCREG_COMMAND_WAIT_COMMAND_DELAY */
+	unsigned int delay:16;
+
+	/* gcregCommandWait:reserved */
+	unsigned int _reserved_16_26:11;
+
+	/* gcregCommandWait:GCREG_COMMAND_WAIT_COMMAND_OPCODE */
+	unsigned int opcode:5;
+};
+
+struct gccmdwait {
+	union {
+		struct gcfldwait fld;
+		unsigned int raw;
+	} cmd;
+
+	/* Alignment filler. */
+	unsigned int _filler;
+};
+
+static const struct gcfldwait gcfldwait200 = {
+	/* gcregCommandWait:GCREG_COMMAND_WAIT_COMMAND_DELAY */
+	200,
+
+	/* gcregCommandWait:reserved */
+	0,
+
+	/* gcregCommandWait:GCREG_COMMAND_WAIT_COMMAND_OPCODE */
+	GCREG_COMMAND_WAIT_COMMAND_OPCODE_WAIT
+};
+
+/*******************************************************************************
+** Command gcregCommandLink
+*/
+
+/* Number of 64-bit words to fetch.  Make sure this number is not too low,
+** nothing else will be fetched.  So, make sure that the last command in the
+** new command buffer is either an END, a LINK, a CALL, or a RETURN.
+*/
+#define GCREG_COMMAND_LINK_COMMAND_PREFETCH                               15 : 0
+#define GCREG_COMMAND_LINK_COMMAND_PREFETCH_End                               15
+#define GCREG_COMMAND_LINK_COMMAND_PREFETCH_Start                              0
+#define GCREG_COMMAND_LINK_COMMAND_PREFETCH_Type                             U16
+
+#define GCREG_COMMAND_LINK_COMMAND_OPCODE                                31 : 27
+#define GCREG_COMMAND_LINK_COMMAND_OPCODE_End                                 31
+#define GCREG_COMMAND_LINK_COMMAND_OPCODE_Start                               27
+#define GCREG_COMMAND_LINK_COMMAND_OPCODE_Type                               U05
+#define   GCREG_COMMAND_LINK_COMMAND_OPCODE_LINK                            0x08
+
+/* Offset Address
+** ~~~~~~~~~~~~~~ */
+#define GCREG_COMMAND_LINK_ADDRESS_Index                                       1
+#define GCREG_COMMAND_LINK_ADDRESS_CmdAddrs                               0x0F0D
+
+#define GCREG_COMMAND_LINK_ADDRESS_ADDRESS                                31 : 0
+#define GCREG_COMMAND_LINK_ADDRESS_ADDRESS_End                                30
+#define GCREG_COMMAND_LINK_ADDRESS_ADDRESS_Start                               0
+#define GCREG_COMMAND_LINK_ADDRESS_ADDRESS_Type                              U31
+
+struct gcfldlink {
+	/* gcregCommandLink:GCREG_COMMAND_LINK_COMMAND_PREFETCH */
+	unsigned int count:16;
+
+	/* gcregCommandLink:reserved */
+	unsigned int _reserved_16_26:11;
+
+	/* gcregCommandLink:GCREG_COMMAND_LINK_COMMAND_OPCODE */
+	unsigned int opcode:5;
+};
+
+struct gccmdlink {
+	union {
+		struct gcfldlink fld;
+		unsigned int raw;
+	} cmd;
+
+	/* gcregCommandLink:GCREG_COMMAND_LINK_ADDRESS_ADDRESS */
+	unsigned int address;
+};
+
+static const struct gcfldlink gcfldlink4 = {
+	/* gcregCommandLink:GCREG_COMMAND_LINK_COMMAND_PREFETCH */
+	4,
+
+	/* gcregCommandLink:reserved */
+	0,
+
+	/* gcregCommandLink:GCREG_COMMAND_LINK_COMMAND_OPCODE */
+	GCREG_COMMAND_LINK_COMMAND_OPCODE_LINK
+};
+
+/*******************************************************************************
+** Command gcregCommandStall
+*/
+
+/* Offset Command
+** ~~~~~~~~~~~~~~ */
+#define GCREG_COMMAND_STALL_COMMAND_OPCODE                               31 : 27
+#define GCREG_COMMAND_STALL_COMMAND_OPCODE_End                                31
+#define GCREG_COMMAND_STALL_COMMAND_OPCODE_Start                              27
+#define GCREG_COMMAND_STALL_COMMAND_OPCODE_Type                              U05
+#define   GCREG_COMMAND_STALL_COMMAND_OPCODE_STALL                          0x09
+
+/* Offset Stall
+** ~~~~~~~~~~~~ */
+#define GCREG_COMMAND_STALL_STALL_SOURCE                                   4 : 0
+#define GCREG_COMMAND_STALL_STALL_SOURCE_End                                   4
+#define GCREG_COMMAND_STALL_STALL_SOURCE_Start                                 0
+#define GCREG_COMMAND_STALL_STALL_SOURCE_Type                                U05
+#define   GCREG_COMMAND_STALL_STALL_SOURCE_FRONT_END                        0x01
+#define   GCREG_COMMAND_STALL_STALL_SOURCE_PIXEL_ENGINE                     0x07
+#define   GCREG_COMMAND_STALL_STALL_SOURCE_DRAWING_ENGINE                   0x0B
+
+#define GCREG_COMMAND_STALL_STALL_DESTINATION                             12 : 8
+#define GCREG_COMMAND_STALL_STALL_DESTINATION_End                             12
+#define GCREG_COMMAND_STALL_STALL_DESTINATION_Start                            8
+#define GCREG_COMMAND_STALL_STALL_DESTINATION_Type                           U05
+#define   GCREG_COMMAND_STALL_STALL_DESTINATION_FRONT_END                   0x01
+#define   GCREG_COMMAND_STALL_STALL_DESTINATION_PIXEL_ENGINE                0x07
+#define   GCREG_COMMAND_STALL_STALL_DESTINATION_DRAWING_ENGINE              0x0B
+
+struct gcfldstall {
+	/* gcregCommandStall:reserved */
+	unsigned int _reserved_0_26:27;
+
+	/* gcregCommandStall:GCREG_COMMAND_STALL_COMMAND_OPCODE */
+	unsigned int opcode:5;
+};
+
+struct gcfldstallarg {
+	/* gcregCommandStall:GCREG_COMMAND_STALL_STALL_SOURCE */
+	unsigned int src:5;
+
+	/* gcregCommandStall:reserved */
+	unsigned int _reserved_5_7:3;
+
+	/* gcregCommandStall:GCREG_COMMAND_STALL_STALL_DESTINATION */
+	unsigned int dst:5;
+
+	/* gcregCommandStall:reserved */
+	unsigned int _reserved_13_31:19;
+};
+
+struct gccmdstall {
+	union {
+		struct gcfldstall fld;
+		unsigned int raw;
+	} cmd;
+
+	union {
+		struct gcfldstallarg fld;
+		unsigned int raw;
+	} arg;
+};
+
+static const struct gcfldstall gcfldstall = {
+	/* gcregCommandStall:reserved */
+	0,
+
+	/* gcregCommandStall:GCREG_COMMAND_STALL_COMMAND_OPCODE */
+	GCREG_COMMAND_STALL_COMMAND_OPCODE_STALL
+};
+
+static const struct gcfldstallarg gcfldstall_fe_pe = {
+	/* gcregCommandStall:GCREG_COMMAND_STALL_STALL_SOURCE */
+	GCREG_COMMAND_STALL_STALL_SOURCE_FRONT_END,
+
+	/* gcregCommandStall:reserved */
+	0,
+
+	/* gcregCommandStall:GCREG_COMMAND_STALL_STALL_DESTINATION */
+	GCREG_COMMAND_STALL_STALL_DESTINATION_PIXEL_ENGINE,
+
+	/* gcregCommandStall:reserved */
+	0
+};
+
+/*******************************************************************************
+** Command gcregCommandCall
+*/
+
+/* Offset Command
+** ~~~~~~~~~~~~~~ */
+
+/* Number of 64-bit words to fetch.  Make sure this number is not too low,
+** nothing else will be fetched.  So, make sure that the last command in the
+** new command buffer is either an END, a LINK, a CALL, or a RETURN.
+*/
+#define GCREG_COMMAND_CALL_COMMAND_PREFETCH                               15 : 0
+#define GCREG_COMMAND_CALL_COMMAND_PREFETCH_End                               15
+#define GCREG_COMMAND_CALL_COMMAND_PREFETCH_Start                              0
+#define GCREG_COMMAND_CALL_COMMAND_PREFETCH_Type                             U16
+
+#define GCREG_COMMAND_CALL_COMMAND_OPCODE                                31 : 27
+#define GCREG_COMMAND_CALL_COMMAND_OPCODE_End                                 31
+#define GCREG_COMMAND_CALL_COMMAND_OPCODE_Start                               27
+#define GCREG_COMMAND_CALL_COMMAND_OPCODE_Type                               U05
+#define   GCREG_COMMAND_CALL_COMMAND_OPCODE_CALL                            0x0A
+
+/* Offset Address
+** ~~~~~~~~~~~~~~ */
+
+#define GCREG_COMMAND_CALL_ADDRESS_ADDRESS                                31 : 0
+#define GCREG_COMMAND_CALL_ADDRESS_ADDRESS_End                                30
+#define GCREG_COMMAND_CALL_ADDRESS_ADDRESS_Start                               0
+#define GCREG_COMMAND_CALL_ADDRESS_ADDRESS_Type                              U31
+
+/* Offset ReturnPrefetch
+** ~~~~~~~~~~~~~~~~~~~~~ */
+
+/* Number of 64-bit words to fetch after a Return has been issued.  Make sure **
+** this number if not too low nothing else will be fetched.  So, make sure    **
+** the last command in this prefetch block is either an END, a LINK, a CALL,  **
+** or a RETURN.                                                               */
+#define GCREG_COMMAND_CALL_RETURN_PREFETCH_PREFETCH                       15 : 0
+#define GCREG_COMMAND_CALL_RETURN_PREFETCH_PREFETCH_End                       15
+#define GCREG_COMMAND_CALL_RETURN_PREFETCH_PREFETCH_Start                      0
+#define GCREG_COMMAND_CALL_RETURN_PREFETCH_PREFETCH_Type                     U16
+
+/* Offset ReturnAddress
+** ~~~~~~~~~~~~~~~~~~~~ */
+
+#define GCREG_COMMAND_CALL_RETURN_ADDRESS_ADDRESS                         31 : 0
+#define GCREG_COMMAND_CALL_RETURN_ADDRESS_ADDRESS_End                         30
+#define GCREG_COMMAND_CALL_RETURN_ADDRESS_ADDRESS_Start                        0
+#define GCREG_COMMAND_CALL_RETURN_ADDRESS_ADDRESS_Type                       U31
+
+struct gccmdcall {
+	/* gcregCommandCall:GCREG_COMMAND_CALL_COMMAND_PREFETCH */
+	unsigned int count:16;
+
+	/* gcregCommandCall:reserved */
+	unsigned int _reserved_16_26:11;
+
+	/* gcregCommandCall:GCREG_COMMAND_CALL_COMMAND_OPCODE */
+	unsigned int opcode:5;
+
+	/* gcregCommandCall:GCREG_COMMAND_CALL_ADDRESS_ADDRESS */
+	unsigned int address;
+
+	/* gcregCommandCall:GCREG_COMMAND_CALL_RETURN_PREFETCH_PREFETCH */
+	unsigned int retcount;
+
+	/* gcregCommandCall:GCREG_COMMAND_CALL_RETURN_ADDRESS_ADDRESS */
+	unsigned int retaddress;
+};
+
+/*******************************************************************************
+** Command gccmdCommandReturn
+*/
+
+#define GCREG_COMMAND_RETURN_COMMAND_OPCODE                              31 : 27
+#define GCREG_COMMAND_RETURN_COMMAND_OPCODE_End                               31
+#define GCREG_COMMAND_RETURN_COMMAND_OPCODE_Start                             27
+#define GCREG_COMMAND_RETURN_COMMAND_OPCODE_Type                             U05
+#define   GCREG_COMMAND_RETURN_COMMAND_OPCODE_RETURN                        0x0B
+
+struct gcfldret {
+	/* gccmdCommandReturn:reserve */
+	unsigned int _reserved_0_26:27;
+
+	/* gccmdCommandReturn:GCREG_COMMAND_RETURN_COMMAND_OPCODE */
+	unsigned int opcode:5;
+};
+
+struct gccmdret {
+	union {
+		struct gcfldret fld;
+		unsigned int raw;
+	}
+	cmd;
+
+	/* Alignment filler. */
+	unsigned int _filler;
+};
+
+static const struct gcfldret gcfldret = {
+	/* gccmdCommandReturn:reserve */
+	0,
+
+	/* gccmdCommandReturn:GCREG_COMMAND_RETURN_COMMAND_OPCODE */
+	GCREG_COMMAND_RETURN_COMMAND_OPCODE_RETURN
+};
+
+/*******************************************************************************
+** State gcregStall
+*/
+
+#define gcregStallRegAddrs                                                0x0F00
+#define GCREG_STALL_Count                                                      1
+#define GCREG_STALL_ResetValue                                        0x00000000
+
+#define GCREG_STALL_FLIP0                                                30 : 30
+#define GCREG_STALL_FLIP0_End                                                 30
+#define GCREG_STALL_FLIP0_Start                                               30
+#define GCREG_STALL_FLIP0_Type                                               U01
+
+#define GCREG_STALL_FLIP1                                                31 : 31
+#define GCREG_STALL_FLIP1_End                                                 31
+#define GCREG_STALL_FLIP1_Start                                               31
+#define GCREG_STALL_FLIP1_Type                                               U01
+
+#define GCREG_STALL_SOURCE                                                 4 : 0
+#define GCREG_STALL_SOURCE_End                                                 4
+#define GCREG_STALL_SOURCE_Start                                               0
+#define GCREG_STALL_SOURCE_Type                                              U05
+#define   GCREG_STALL_SOURCE_FRONT_END                                      0x01
+#define   GCREG_STALL_SOURCE_PIXEL_ENGINE                                   0x07
+#define   GCREG_STALL_SOURCE_DRAWING_ENGINE                                 0x0B
+
+#define GCREG_STALL_DESTINATION                                           12 : 8
+#define GCREG_STALL_DESTINATION_End                                           12
+#define GCREG_STALL_DESTINATION_Start                                          8
+#define GCREG_STALL_DESTINATION_Type                                         U05
+#define   GCREG_STALL_DESTINATION_FRONT_END                                 0x01
+#define   GCREG_STALL_DESTINATION_PIXEL_ENGINE                              0x07
+#define   GCREG_STALL_DESTINATION_DRAWING_ENGINE                            0x0B
+
+/*******************************************************************************
+** State gcregPipeSelect
+*/
+
+/* Select the current graphics pipe. */
+
+#define gcregPipeSelectRegAddrs                                           0x0E00
+#define GCREG_PIPE_SELECT_MSB                                                 15
+#define GCREG_PIPE_SELECT_LSB                                                  0
+#define GCREG_PIPE_SELECT_BLK                                                  0
+#define GCREG_PIPE_SELECT_Count                                                1
+#define GCREG_PIPE_SELECT_FieldMask                                   0x00000001
+#define GCREG_PIPE_SELECT_ReadMask                                    0x00000001
+#define GCREG_PIPE_SELECT_WriteMask                                   0x00000001
+#define GCREG_PIPE_SELECT_ResetValue                                  0x00000000
+
+/* Selects the pipe to send states and data to.  Make  sure the PE is idle    **
+** before you switch pipes.                                                   */
+#define GCREG_PIPE_SELECT_PIPE                                             0 : 0
+#define GCREG_PIPE_SELECT_PIPE_End                                             0
+#define GCREG_PIPE_SELECT_PIPE_Start                                           0
+#define GCREG_PIPE_SELECT_PIPE_Type                                          U01
+#define   GCREG_PIPE_SELECT_PIPE_PIPE3D                                      0x0
+#define   GCREG_PIPE_SELECT_PIPE_PIPE2D                                      0x1
+
+struct gcregpipeselect {
+	/* gcregPipeSelectRegAddrs:GCREG_PIPE_SELECT_PIPE */
+	unsigned int pipe:1;
+
+	/* gcregPipeSelectRegAddrs:reserved */
+	unsigned int _reserved_1_31:31;
+};
+
+static const struct gcregpipeselect gcregpipeselect_2D = {
+	/* gcregPipeSelectRegAddrs:GCREG_PIPE_SELECT_PIPE */
+	GCREG_PIPE_SELECT_PIPE_PIPE2D,
+
+	/* gcregPipeSelectRegAddrs:reserved */
+	0
+};
+
+/*******************************************************************************
+** State gcregEvent
+*/
+
+/* Send an event. */
+
+#define gcregEventRegAddrs                                                0x0E01
+#define GCREG_EVENT_MSB                                                       15
+#define GCREG_EVENT_LSB                                                        0
+#define GCREG_EVENT_BLK                                                        0
+#define GCREG_EVENT_Count                                                      1
+#define GCREG_EVENT_FieldMask                                         0x0000007F
+#define GCREG_EVENT_ReadMask                                          0x0000007F
+#define GCREG_EVENT_WriteMask                                         0x0000007F
+#define GCREG_EVENT_ResetValue                                        0x00000000
+
+/* 5-bit event ID to send. */
+#define GCREG_EVENT_EVENT_ID                                               4 : 0
+#define GCREG_EVENT_EVENT_ID_End                                               4
+#define GCREG_EVENT_EVENT_ID_Start                                             0
+#define GCREG_EVENT_EVENT_ID_Type                                            U05
+
+/* The event is sent by the FE. */
+#define GCREG_EVENT_FE_SRC                                                 5 : 5
+#define GCREG_EVENT_FE_SRC_End                                                 5
+#define GCREG_EVENT_FE_SRC_Start                                               5
+#define GCREG_EVENT_FE_SRC_Type                                              U01
+#define   GCREG_EVENT_FE_SRC_DISABLE                                         0x0
+#define   GCREG_EVENT_FE_SRC_ENABLE                                          0x1
+
+/* The event is sent by the PE. */
+#define GCREG_EVENT_PE_SRC                                                 6 : 6
+#define GCREG_EVENT_PE_SRC_End                                                 6
+#define GCREG_EVENT_PE_SRC_Start                                               6
+#define GCREG_EVENT_PE_SRC_Type                                              U01
+#define   GCREG_EVENT_PE_SRC_DISABLE                                         0x0
+#define   GCREG_EVENT_PE_SRC_ENABLE                                          0x1
+
+struct gcregevent {
+	/* gcregEventRegAddrs:GCREG_EVENT_EVENT_ID */
+	unsigned int id:5;
+
+	/* gcregEventRegAddrs:GCREG_EVENT_FE_SRC */
+	unsigned int fe:1;
+
+	/* gcregEventRegAddrs:GCREG_EVENT_PE_SRC */
+	unsigned int pe:1;
+
+	/* gcregEventRegAddrs:reserved */
+	unsigned int _reserved_7_31:25;
+};
+
+/*******************************************************************************
+** State gcregSemaphore
+*/
+
+/* A sempahore state arms the semaphore in the destination. */
+
+#define gcregSemaphoreRegAddrs                                            0x0E02
+#define GCREG_SEMAPHORE_MSB                                                   15
+#define GCREG_SEMAPHORE_LSB                                                    0
+#define GCREG_SEMAPHORE_BLK                                                    0
+#define GCREG_SEMAPHORE_Count                                                  1
+#define GCREG_SEMAPHORE_FieldMask                                     0x00001F1F
+#define GCREG_SEMAPHORE_ReadMask                                      0x00001F1F
+#define GCREG_SEMAPHORE_WriteMask                                     0x00001F1F
+#define GCREG_SEMAPHORE_ResetValue                                    0x00000000
+
+#define GCREG_SEMAPHORE_SOURCE                                             4 : 0
+#define GCREG_SEMAPHORE_SOURCE_End                                             4
+#define GCREG_SEMAPHORE_SOURCE_Start                                           0
+#define GCREG_SEMAPHORE_SOURCE_Type                                          U05
+#define   GCREG_SEMAPHORE_SOURCE_FRONT_END                                  0x01
+#define   GCREG_SEMAPHORE_SOURCE_PIXEL_ENGINE                               0x07
+#define   GCREG_SEMAPHORE_SOURCE_DRAWING_ENGINE                             0x0B
+
+#define GCREG_SEMAPHORE_DESTINATION                                       12 : 8
+#define GCREG_SEMAPHORE_DESTINATION_End                                       12
+#define GCREG_SEMAPHORE_DESTINATION_Start                                      8
+#define GCREG_SEMAPHORE_DESTINATION_Type                                     U05
+#define   GCREG_SEMAPHORE_DESTINATION_FRONT_END                             0x01
+#define   GCREG_SEMAPHORE_DESTINATION_PIXEL_ENGINE                          0x07
+#define   GCREG_SEMAPHORE_DESTINATION_DRAWING_ENGINE                        0x0B
+
+struct gcregsemaphore {
+	/* gcregSemaphoreRegAddrs:GCREG_SEMAPHORE_SOURCE */
+	unsigned int src:5;
+
+	/* gcregSemaphoreRegAddrs:reserved */
+	unsigned int _reserved_5_7:3;
+
+	/* gcregSemaphoreRegAddrs:GCREG_SEMAPHORE_DESTINATION */
+	unsigned int dst:5;
+
+	/* gcregSemaphoreRegAddrs:reserved */
+	unsigned int _reserved_13_31:19;
+};
+
+static const struct gcregsemaphore gcregsema_fe_pe = {
+	/* gcregSemaphoreRegAddrs:GCREG_SEMAPHORE_SOURCE */
+	GCREG_SEMAPHORE_SOURCE_FRONT_END,
+
+	/* gcregSemaphoreRegAddrs:reserved */
+	0,
+
+	/* gcregSemaphoreRegAddrs:GCREG_SEMAPHORE_DESTINATION */
+	GCREG_SEMAPHORE_DESTINATION_PIXEL_ENGINE,
+
+	/* gcregSemaphoreRegAddrs:reserved */
+	0
+};
+
+
+/*******************************************************************************
+** State gcregFlush
+*/
+
+/* Flush the current pipe. */
+
+#define gcregFlushRegAddrs                                                0x0E03
+#define GCREG_FLUSH_MSB                                                       15
+#define GCREG_FLUSH_LSB                                                        0
+#define GCREG_FLUSH_BLK                                                        0
+#define GCREG_FLUSH_Count                                                      1
+#define GCREG_FLUSH_FieldMask                                         0x00000008
+#define GCREG_FLUSH_ReadMask                                          0x00000008
+#define GCREG_FLUSH_WriteMask                                         0x00000008
+#define GCREG_FLUSH_ResetValue                                        0x00000000
+
+/* Flush the 2D pixel cache. */
+#define GCREG_FLUSH_PE2D_CACHE                                             3 : 3
+#define GCREG_FLUSH_PE2D_CACHE_End                                             3
+#define GCREG_FLUSH_PE2D_CACHE_Start                                           3
+#define GCREG_FLUSH_PE2D_CACHE_Type                                          U01
+#define   GCREG_FLUSH_PE2D_CACHE_DISABLE                                     0x0
+#define   GCREG_FLUSH_PE2D_CACHE_ENABLE                                      0x1
+
+struct gcregflush {
+	/* gcregFlushRegAddrs:reserved */
+	unsigned int _reserved_0_2:3;
+
+	/* gcregFlushRegAddrs:GCREG_FLUSH_PE2D_CACHE */
+	unsigned int enable:1;
+
+	/* gcregFlushRegAddrs:reserved */
+	unsigned int _reserved_4_31:28;
+};
+
+static const struct gcregflush gcregflush_pe2D = {
+	/* gcregFlushRegAddrs:reserved */
+	0,
+
+	/* gcregFlushRegAddrs:GCREG_FLUSH_PE2D_CACHE */
+	GCREG_FLUSH_PE2D_CACHE_ENABLE,
+
+	/* gcregFlushRegAddrs:reserved */
+	0
+};
+
+/*******************************************************************************
+** State gcregMMUFlush
+*/
+
+/* Flush the virtual addrses lookup cache inside the MC. */
+
+#define gcregMMUFlushRegAddrs                                             0x0E04
+#define gcregMMU_FLUSH_MSB                                                    15
+#define gcregMMU_FLUSH_LSB                                                     0
+#define gcregMMU_FLUSH_BLK                                                     0
+#define gcregMMU_FLUSH_Count                                                   1
+#define gcregMMU_FLUSH_FieldMask                                      0x00000009
+#define gcregMMU_FLUSH_ReadMask                                       0x00000009
+#define gcregMMU_FLUSH_WriteMask                                      0x00000009
+#define gcregMMU_FLUSH_ResetValue                                     0x00000000
+
+/* Flush the FE address translation caches. */
+#define gcregMMU_FLUSH_FEMMU                                               0 : 0
+#define gcregMMU_FLUSH_FEMMU_End                                               0
+#define gcregMMU_FLUSH_FEMMU_Start                                             0
+#define gcregMMU_FLUSH_FEMMU_Type                                            U01
+#define   gcregMMU_FLUSH_FEMMU_DISABLE                                       0x0
+#define   gcregMMU_FLUSH_FEMMU_ENABLE                                        0x1
+
+/* Flush the PE render target address translation caches. */
+#define gcregMMU_FLUSH_PEMMU                                               3 : 3
+#define gcregMMU_FLUSH_PEMMU_End                                               3
+#define gcregMMU_FLUSH_PEMMU_Start                                             3
+#define gcregMMU_FLUSH_PEMMU_Type                                            U01
+#define   gcregMMU_FLUSH_PEMMU_DISABLE                                       0x0
+#define   gcregMMU_FLUSH_PEMMU_ENABLE                                        0x1
+
+/*******************************************************************************
+** Register gcregCmdBufferAddr
+*/
+
+/* Base address for the command buffer.  The address must be 64-bit aligned
+** and it is always physical. This register cannot be read. To check the value
+** of the current fetch address use gcregFEDebugCurCmdAdr. Since this is a write
+** only register is has no reset value.
+*/
+
+#define GCREG_CMD_BUFFER_ADDR_Address                                    0x00654
+#define GCREG_CMD_BUFFER_ADDR_MSB                                             15
+#define GCREG_CMD_BUFFER_ADDR_LSB                                              0
+#define GCREG_CMD_BUFFER_ADDR_BLK                                              0
+#define GCREG_CMD_BUFFER_ADDR_Count                                            1
+#define GCREG_CMD_BUFFER_ADDR_FieldMask                               0xFFFFFFFF
+#define GCREG_CMD_BUFFER_ADDR_ReadMask                                0x00000000
+#define GCREG_CMD_BUFFER_ADDR_WriteMask                               0xFFFFFFFC
+#define GCREG_CMD_BUFFER_ADDR_ResetValue                              0x00000000
+
+#define GCREG_CMD_BUFFER_ADDR_ADDRESS                                     31 : 0
+#define GCREG_CMD_BUFFER_ADDR_ADDRESS_End                                     30
+#define GCREG_CMD_BUFFER_ADDR_ADDRESS_Start                                    0
+#define GCREG_CMD_BUFFER_ADDR_ADDRESS_Type                                   U31
+
+/*******************************************************************************
+** Register gcregCmdBufferCtrl
+*/
+
+/* Since this is a write only register is has no reset value. */
+
+#define GCREG_CMD_BUFFER_CTRL_Address                                    0x00658
+#define GCREG_CMD_BUFFER_CTRL_MSB                                             15
+#define GCREG_CMD_BUFFER_CTRL_LSB                                              0
+#define GCREG_CMD_BUFFER_CTRL_BLK                                              0
+#define GCREG_CMD_BUFFER_CTRL_Count                                            1
+#define GCREG_CMD_BUFFER_CTRL_FieldMask                               0x0001FFFF
+#define GCREG_CMD_BUFFER_CTRL_ReadMask                                0x00010000
+#define GCREG_CMD_BUFFER_CTRL_WriteMask                               0x0001FFFF
+#define GCREG_CMD_BUFFER_CTRL_ResetValue                              0x00000000
+
+/* Number of 64-bit words to fetch from the command buffer. */
+#define GCREG_CMD_BUFFER_CTRL_PREFETCH                                    15 : 0
+#define GCREG_CMD_BUFFER_CTRL_PREFETCH_End                                    15
+#define GCREG_CMD_BUFFER_CTRL_PREFETCH_Start                                   0
+#define GCREG_CMD_BUFFER_CTRL_PREFETCH_Type                                  U16
+
+/* Enable the command parser. */
+#define GCREG_CMD_BUFFER_CTRL_ENABLE                                     16 : 16
+#define GCREG_CMD_BUFFER_CTRL_ENABLE_End                                      16
+#define GCREG_CMD_BUFFER_CTRL_ENABLE_Start                                    16
+#define GCREG_CMD_BUFFER_CTRL_ENABLE_Type                                    U01
+#define   GCREG_CMD_BUFFER_CTRL_ENABLE_DISABLE                               0x0
+#define   GCREG_CMD_BUFFER_CTRL_ENABLE_ENABLE                                0x1
+
+/*******************************************************************************
+** Register gcregFEDebugState
+*/
+
+#define GCREG_FE_DEBUG_STATE_Address                                     0x00660
+#define GCREG_FE_DEBUG_STATE_MSB                                              15
+#define GCREG_FE_DEBUG_STATE_LSB                                               0
+#define GCREG_FE_DEBUG_STATE_BLK                                               0
+#define GCREG_FE_DEBUG_STATE_Count                                             1
+#define GCREG_FE_DEBUG_STATE_FieldMask                                0x0003FF1F
+#define GCREG_FE_DEBUG_STATE_ReadMask                                 0x0003FF1F
+#define GCREG_FE_DEBUG_STATE_WriteMask                                0x00000000
+#define GCREG_FE_DEBUG_STATE_ResetValue                               0x00000000
+
+#define GCREG_FE_DEBUG_STATE_CMD_STATE                                     4 : 0
+#define GCREG_FE_DEBUG_STATE_CMD_STATE_End                                     4
+#define GCREG_FE_DEBUG_STATE_CMD_STATE_Start                                   0
+#define GCREG_FE_DEBUG_STATE_CMD_STATE_Type                                  U05
+
+#define GCREG_FE_DEBUG_STATE_CMD_DMA_STATE                                 9 : 8
+#define GCREG_FE_DEBUG_STATE_CMD_DMA_STATE_End                                 9
+#define GCREG_FE_DEBUG_STATE_CMD_DMA_STATE_Start                               8
+#define GCREG_FE_DEBUG_STATE_CMD_DMA_STATE_Type                              U02
+
+#define GCREG_FE_DEBUG_STATE_CMD_FETCH_STATE                             11 : 10
+#define GCREG_FE_DEBUG_STATE_CMD_FETCH_STATE_End                              11
+#define GCREG_FE_DEBUG_STATE_CMD_FETCH_STATE_Start                            10
+#define GCREG_FE_DEBUG_STATE_CMD_FETCH_STATE_Type                            U02
+
+#define GCREG_FE_DEBUG_STATE_REQ_DMA_STATE                               13 : 12
+#define GCREG_FE_DEBUG_STATE_REQ_DMA_STATE_End                                13
+#define GCREG_FE_DEBUG_STATE_REQ_DMA_STATE_Start                              12
+#define GCREG_FE_DEBUG_STATE_REQ_DMA_STATE_Type                              U02
+
+#define GCREG_FE_DEBUG_STATE_CAL_STATE                                   15 : 14
+#define GCREG_FE_DEBUG_STATE_CAL_STATE_End                                    15
+#define GCREG_FE_DEBUG_STATE_CAL_STATE_Start                                  14
+#define GCREG_FE_DEBUG_STATE_CAL_STATE_Type                                  U02
+
+#define GCREG_FE_DEBUG_STATE_VE_REQ_STATE                                17 : 16
+#define GCREG_FE_DEBUG_STATE_VE_REQ_STATE_End                                 17
+#define GCREG_FE_DEBUG_STATE_VE_REQ_STATE_Start                               16
+#define GCREG_FE_DEBUG_STATE_VE_REQ_STATE_Type                               U02
+
+/*******************************************************************************
+** Register gcregFEDebugCurCmdAdr
+*/
+
+/* This is the command decoder address.  The address is always physical so
+** the MSB should always be 0.  It has no reset value.
+*/
+
+#define GCREG_FE_DEBUG_CUR_CMD_ADR_Address                               0x00664
+#define GCREG_FE_DEBUG_CUR_CMD_ADR_MSB                                        15
+#define GCREG_FE_DEBUG_CUR_CMD_ADR_LSB                                         0
+#define GCREG_FE_DEBUG_CUR_CMD_ADR_BLK                                         0
+#define GCREG_FE_DEBUG_CUR_CMD_ADR_Count                                       1
+#define GCREG_FE_DEBUG_CUR_CMD_ADR_FieldMask                          0xFFFFFFF8
+#define GCREG_FE_DEBUG_CUR_CMD_ADR_ReadMask                           0xFFFFFFF8
+#define GCREG_FE_DEBUG_CUR_CMD_ADR_WriteMask                          0x00000000
+#define GCREG_FE_DEBUG_CUR_CMD_ADR_ResetValue                         0x00000000
+
+#define GCREG_FE_DEBUG_CUR_CMD_ADR_CUR_CMD_ADR                            31 : 3
+#define GCREG_FE_DEBUG_CUR_CMD_ADR_CUR_CMD_ADR_End                            31
+#define GCREG_FE_DEBUG_CUR_CMD_ADR_CUR_CMD_ADR_Start                           3
+#define GCREG_FE_DEBUG_CUR_CMD_ADR_CUR_CMD_ADR_Type                          U29
+
+/*******************************************************************************
+** Register gcregFEDebugCmdLowReg
+*/
+
+#define GCREG_FE_DEBUG_CMD_LOW_REG_Address                               0x00668
+#define GCREG_FE_DEBUG_CMD_LOW_REG_MSB                                        15
+#define GCREG_FE_DEBUG_CMD_LOW_REG_LSB                                         0
+#define GCREG_FE_DEBUG_CMD_LOW_REG_BLK                                         0
+#define GCREG_FE_DEBUG_CMD_LOW_REG_Count                                       1
+#define GCREG_FE_DEBUG_CMD_LOW_REG_FieldMask                          0xFFFFFFFF
+#define GCREG_FE_DEBUG_CMD_LOW_REG_ReadMask                           0xFFFFFFFF
+#define GCREG_FE_DEBUG_CMD_LOW_REG_WriteMask                          0x00000000
+#define GCREG_FE_DEBUG_CMD_LOW_REG_ResetValue                         0x00000000
+
+/* Command register used by CmdState. */
+#define GCREG_FE_DEBUG_CMD_LOW_REG_CMD_LOW_REG                            31 : 0
+#define GCREG_FE_DEBUG_CMD_LOW_REG_CMD_LOW_REG_End                            31
+#define GCREG_FE_DEBUG_CMD_LOW_REG_CMD_LOW_REG_Start                           0
+#define GCREG_FE_DEBUG_CMD_LOW_REG_CMD_LOW_REG_Type                          U32
+
+/*******************************************************************************
+** Register gcregFEDebugCmdHiReg
+*/
+
+#define GCREG_FE_DEBUG_CMD_HI_REG_Address                                0x0066C
+#define GCREG_FE_DEBUG_CMD_HI_REG_MSB                                         15
+#define GCREG_FE_DEBUG_CMD_HI_REG_LSB                                          0
+#define GCREG_FE_DEBUG_CMD_HI_REG_BLK                                          0
+#define GCREG_FE_DEBUG_CMD_HI_REG_Count                                        1
+#define GCREG_FE_DEBUG_CMD_HI_REG_FieldMask                           0xFFFFFFFF
+#define GCREG_FE_DEBUG_CMD_HI_REG_ReadMask                            0xFFFFFFFF
+#define GCREG_FE_DEBUG_CMD_HI_REG_WriteMask                           0x00000000
+#define GCREG_FE_DEBUG_CMD_HI_REG_ResetValue                          0x00000000
+
+/* Command register used by CmdState. */
+#define GCREG_FE_DEBUG_CMD_HI_REG_CMD_HI_REG                              31 : 0
+#define GCREG_FE_DEBUG_CMD_HI_REG_CMD_HI_REG_End                              31
+#define GCREG_FE_DEBUG_CMD_HI_REG_CMD_HI_REG_Start                             0
+#define GCREG_FE_DEBUG_CMD_HI_REG_CMD_HI_REG_Type                            U32
+
+/*******************************************************************************
+** State gcregMMUSafeAddress
+*/
+
+/* A 64-byte address that will acts as a 'safe' zone.  Any address that would
+** cause an exception is routed to this safe zone.  Reads will happend and
+** writes will go to this address, but with a write-enable of 0. This
+** register can only be programmed once after a reset - any attempt to write
+** to this register after the initial write-after-reset will be ignored.
+*/
+
+#define gcregMMUSafeAddressRegAddrs                                       0x0060
+#define GCREG_MMU_SAFE_ADDRESS_MSB                                            15
+#define GCREG_MMU_SAFE_ADDRESS_LSB                                             0
+#define GCREG_MMU_SAFE_ADDRESS_BLK                                             0
+#define GCREG_MMU_SAFE_ADDRESS_Count                                           1
+#define GCREG_MMU_SAFE_ADDRESS_FieldMask                              0xFFFFFFFF
+#define GCREG_MMU_SAFE_ADDRESS_ReadMask                               0xFFFFFFC0
+#define GCREG_MMU_SAFE_ADDRESS_WriteMask                              0xFFFFFFC0
+#define GCREG_MMU_SAFE_ADDRESS_ResetValue                             0x00000000
+
+#define GCREG_MMU_SAFE_ADDRESS_ADDRESS                                    31 : 0
+#define GCREG_MMU_SAFE_ADDRESS_ADDRESS_End                                    31
+#define GCREG_MMU_SAFE_ADDRESS_ADDRESS_Start                                   0
+#define GCREG_MMU_SAFE_ADDRESS_ADDRESS_Type                                  U32
+
+/*******************************************************************************
+** State gcregMMUConfiguration
+*/
+
+/* This register controls the master TLB of the MMU. */
+
+#define gcregMMUConfigurationRegAddrs                                     0x0061
+#define GCREG_MMU_CONFIGURATION_MSB                                           15
+#define GCREG_MMU_CONFIGURATION_LSB                                            0
+#define GCREG_MMU_CONFIGURATION_BLK                                            0
+#define GCREG_MMU_CONFIGURATION_Count                                          1
+#define GCREG_MMU_CONFIGURATION_FieldMask                             0xFFFFFD99
+#define GCREG_MMU_CONFIGURATION_ReadMask                              0xFFFFFD99
+#define GCREG_MMU_CONFIGURATION_WriteMask                             0xFFFFFD99
+#define GCREG_MMU_CONFIGURATION_ResetValue                            0x00000000
+
+/* Upper bits of the page aligned (depending on the mode) master TLB. */
+#define GCREG_MMU_CONFIGURATION_ADDRESS                                  31 : 10
+#define GCREG_MMU_CONFIGURATION_ADDRESS_End                                   31
+#define GCREG_MMU_CONFIGURATION_ADDRESS_Start                                 10
+#define GCREG_MMU_CONFIGURATION_ADDRESS_Type                                 U22
+
+/* Mask for Address field. */
+#define GCREG_MMU_CONFIGURATION_MASK_ADDRESS                               8 : 8
+#define GCREG_MMU_CONFIGURATION_MASK_ADDRESS_End                               8
+#define GCREG_MMU_CONFIGURATION_MASK_ADDRESS_Start                             8
+#define GCREG_MMU_CONFIGURATION_MASK_ADDRESS_Type                            U01
+#define   GCREG_MMU_CONFIGURATION_MASK_ADDRESS_ENABLED                       0x0
+#define   GCREG_MMU_CONFIGURATION_MASK_ADDRESS_MASKED                        0x1
+
+/* Mask Flush field. */
+#define GCREG_MMU_CONFIGURATION_MASK_FLUSH                                 7 : 7
+#define GCREG_MMU_CONFIGURATION_MASK_FLUSH_End                                 7
+#define GCREG_MMU_CONFIGURATION_MASK_FLUSH_Start                               7
+#define GCREG_MMU_CONFIGURATION_MASK_FLUSH_Type                              U01
+#define   GCREG_MMU_CONFIGURATION_MASK_FLUSH_ENABLED                         0x0
+#define   GCREG_MMU_CONFIGURATION_MASK_FLUSH_MASKED                          0x1
+
+/* Flush the MMU caches. */
+#define GCREG_MMU_CONFIGURATION_FLUSH                                      4 : 4
+#define GCREG_MMU_CONFIGURATION_FLUSH_End                                      4
+#define GCREG_MMU_CONFIGURATION_FLUSH_Start                                    4
+#define GCREG_MMU_CONFIGURATION_FLUSH_Type                                   U01
+#define   GCREG_MMU_CONFIGURATION_FLUSH_FLUSH                                0x1
+
+/* Mask Mode field. */
+#define GCREG_MMU_CONFIGURATION_MASK_MODE                                  3 : 3
+#define GCREG_MMU_CONFIGURATION_MASK_MODE_End                                  3
+#define GCREG_MMU_CONFIGURATION_MASK_MODE_Start                                3
+#define GCREG_MMU_CONFIGURATION_MASK_MODE_Type                               U01
+#define   GCREG_MMU_CONFIGURATION_MASK_MODE_ENABLED                          0x0
+#define   GCREG_MMU_CONFIGURATION_MASK_MODE_MASKED                           0x1
+
+/* Set the mode for the Master TLB. */
+#define GCREG_MMU_CONFIGURATION_MODE                                       0 : 0
+#define GCREG_MMU_CONFIGURATION_MODE_End                                       0
+#define GCREG_MMU_CONFIGURATION_MODE_Start                                     0
+#define GCREG_MMU_CONFIGURATION_MODE_Type                                    U01
+/* The Master TLB is 4kB in size and contains 1024 entries. Each page can be  **
+** 4kB or 64kB in size.                                                       */
+#define   GCREG_MMU_CONFIGURATION_MODE_MODE4_K                               0x0
+/* The Master TLB is 1kB in size and contains 256 entries. Each page can be   **
+** 4kB, 64kB, 1MB or 16MB in size.                                            */
+#define   GCREG_MMU_CONFIGURATION_MODE_MODE1_K                               0x1
+
+struct gcregmmuconfiguration {
+	/* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_MODE */
+	unsigned int master:1;
+
+	/* gcregMMUConfiguration:reserved */
+	unsigned int _reserved_1_2:2;
+
+	/* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_MASK_MODE */
+	unsigned int master_mask:1;
+
+	/* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_FLUSH */
+	unsigned int flush:1;
+
+	/* gcregMMUConfiguration:reserved */
+	unsigned int _reserved_5_6:2;
+
+	/* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_MASK_FLUSH */
+	unsigned int flush_mask:1;
+
+	/* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_MASK_ADDRESS */
+	unsigned int address_mask:1;
+
+	/* gcregMMUConfiguration:reserved */
+	unsigned int _reserved_9:1;
+
+	/* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_ADDRESS */
+	unsigned int address:22;
+};
+
+static const struct gcregmmuconfiguration gcregmmu_flush = {
+	/* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_MODE */
+	0,
+
+	/* gcregMMUConfiguration:reserved */
+	0,
+
+	/* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_MASK_MODE */
+	GCREG_MMU_CONFIGURATION_MASK_MODE_MASKED,
+
+	/* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_FLUSH */
+	GCREG_MMU_CONFIGURATION_FLUSH_FLUSH,
+
+	/* gcregMMUConfiguration:reserved */
+	0,
+
+	/* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_MASK_FLUSH */
+	GCREG_MMU_CONFIGURATION_MASK_FLUSH_ENABLED,
+
+	/* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_MASK_ADDRESS */
+	GCREG_MMU_CONFIGURATION_MASK_ADDRESS_MASKED,
+
+	/* gcregMMUConfiguration:reserved */
+	0,
+
+	/* gcregMMUConfiguration:GCREG_MMU_CONFIGURATION_ADDRESS */
+	0
+};
+
+/*******************************************************************************
+** Register gcregMMUStatus
+*/
+
+/* Status register that holds which MMU generated an exception. */
+
+#define GCREG_MMU_STATUS_Address                                         0x00188
+#define GCREG_MMU_STATUS_MSB                                                  15
+#define GCREG_MMU_STATUS_LSB                                                   0
+#define GCREG_MMU_STATUS_BLK                                                   0
+#define GCREG_MMU_STATUS_Count                                                 1
+#define GCREG_MMU_STATUS_FieldMask                                    0x00003333
+#define GCREG_MMU_STATUS_ReadMask                                     0x00003333
+#define GCREG_MMU_STATUS_WriteMask                                    0x00000000
+#define GCREG_MMU_STATUS_ResetValue                                   0x00000000
+
+/* MMU 3 caused an exception and the fourth gcregMMUException register holds  **
+** the offending address.                                                     */
+#define GCREG_MMU_STATUS_EXCEPTION3                                      13 : 12
+#define GCREG_MMU_STATUS_EXCEPTION3_End                                       13
+#define GCREG_MMU_STATUS_EXCEPTION3_Start                                     12
+#define GCREG_MMU_STATUS_EXCEPTION3_Type                                     U02
+#define   GCREG_MMU_STATUS_EXCEPTION3_SLAVE_NOT_PRESENT                      0x1
+#define   GCREG_MMU_STATUS_EXCEPTION3_PAGE_NOT_PRESENT                       0x2
+#define   GCREG_MMU_STATUS_EXCEPTION3_WRITE_VIOLATION                        0x3
+
+/* MMU 2 caused an exception and the third gcregMMUException register holds   **
+** the offending address.                                                     */
+#define GCREG_MMU_STATUS_EXCEPTION2                                        9 : 8
+#define GCREG_MMU_STATUS_EXCEPTION2_End                                        9
+#define GCREG_MMU_STATUS_EXCEPTION2_Start                                      8
+#define GCREG_MMU_STATUS_EXCEPTION2_Type                                     U02
+#define   GCREG_MMU_STATUS_EXCEPTION2_SLAVE_NOT_PRESENT                      0x1
+#define   GCREG_MMU_STATUS_EXCEPTION2_PAGE_NOT_PRESENT                       0x2
+#define   GCREG_MMU_STATUS_EXCEPTION2_WRITE_VIOLATION                        0x3
+
+/* MMU 1 caused an exception and the second gcregMMUException register holds  **
+** the offending address.                                                     */
+#define GCREG_MMU_STATUS_EXCEPTION1                                        5 : 4
+#define GCREG_MMU_STATUS_EXCEPTION1_End                                        5
+#define GCREG_MMU_STATUS_EXCEPTION1_Start                                      4
+#define GCREG_MMU_STATUS_EXCEPTION1_Type                                     U02
+#define   GCREG_MMU_STATUS_EXCEPTION1_SLAVE_NOT_PRESENT                      0x1
+#define   GCREG_MMU_STATUS_EXCEPTION1_PAGE_NOT_PRESENT                       0x2
+#define   GCREG_MMU_STATUS_EXCEPTION1_WRITE_VIOLATION                        0x3
+
+/* MMU 0 caused an exception and the first gcregMMUException register holds   **
+** the offending address.                                                     */
+#define GCREG_MMU_STATUS_EXCEPTION0                                        1 : 0
+#define GCREG_MMU_STATUS_EXCEPTION0_End                                        1
+#define GCREG_MMU_STATUS_EXCEPTION0_Start                                      0
+#define GCREG_MMU_STATUS_EXCEPTION0_Type                                     U02
+#define   GCREG_MMU_STATUS_EXCEPTION0_SLAVE_NOT_PRESENT                      0x1
+#define   GCREG_MMU_STATUS_EXCEPTION0_PAGE_NOT_PRESENT                       0x2
+#define   GCREG_MMU_STATUS_EXCEPTION0_WRITE_VIOLATION                        0x3
+
+/*******************************************************************************
+** Register gcregMMUControl
+*/
+
+/* Control register that enables the MMU (only time shot). */
+
+#define GCREG_MMU_CONTROL_Address                                        0x0018C
+#define GCREG_MMU_CONTROL_MSB                                                 15
+#define GCREG_MMU_CONTROL_LSB                                                  0
+#define GCREG_MMU_CONTROL_BLK                                                  0
+#define GCREG_MMU_CONTROL_Count                                                1
+#define GCREG_MMU_CONTROL_FieldMask                                   0x00000001
+#define GCREG_MMU_CONTROL_ReadMask                                    0x00000000
+#define GCREG_MMU_CONTROL_WriteMask                                   0x00000001
+#define GCREG_MMU_CONTROL_ResetValue                                  0x00000000
+
+/* Enable the MMU. For security reasons, once the MMU is  enabled it cannot   **
+** be disabled anymore.                                                       */
+#define GCREG_MMU_CONTROL_ENABLE                                           0 : 0
+#define GCREG_MMU_CONTROL_ENABLE_End                                           0
+#define GCREG_MMU_CONTROL_ENABLE_Start                                         0
+#define GCREG_MMU_CONTROL_ENABLE_Type                                        U01
+#define   GCREG_MMU_CONTROL_ENABLE_ENABLE                                    0x1
+
+/*******************************************************************************
+** State/Register gcregMMUException (4 in total)
+*/
+
+/* Up to 4 registers that will hold the original address that generated an
+** exception. Use load state form for exception resolution.
+*/
+
+#define gcregMMUExceptionRegAddrs                                         0x0064
+#define GCREG_MMU_EXCEPTION_Address                                      0x00190
+#define GCREG_MMU_EXCEPTION_MSB                                               15
+#define GCREG_MMU_EXCEPTION_LSB                                                2
+#define GCREG_MMU_EXCEPTION_BLK                                                2
+#define GCREG_MMU_EXCEPTION_Count                                              4
+#define GCREG_MMU_EXCEPTION_FieldMask                                 0xFFFFFFFF
+#define GCREG_MMU_EXCEPTION_ReadMask                                  0xFFFFFFFF
+#define GCREG_MMU_EXCEPTION_WriteMask                                 0xFFFFFFFF
+#define GCREG_MMU_EXCEPTION_ResetValue                                0x00000000
+
+#define GCREG_MMU_EXCEPTION_ADDRESS                                       31 : 0
+#define GCREG_MMU_EXCEPTION_ADDRESS_End                                       31
+#define GCREG_MMU_EXCEPTION_ADDRESS_Start                                      0
+#define GCREG_MMU_EXCEPTION_ADDRESS_Type                                     U32
+
+/*******************************************************************************
+** Register gcModulePowerControls
+*/
+
+/* Control register for module level power controls. */
+
+#define GC_MODULE_POWER_CONTROLS_Address                                 0x00100
+#define GC_MODULE_POWER_CONTROLS_MSB                                          15
+#define GC_MODULE_POWER_CONTROLS_LSB                                           0
+#define GC_MODULE_POWER_CONTROLS_BLK                                           0
+#define GC_MODULE_POWER_CONTROLS_Count                                         1
+#define GC_MODULE_POWER_CONTROLS_FieldMask                            0xFFFF00F7
+#define GC_MODULE_POWER_CONTROLS_ReadMask                             0xFFFF00F7
+#define GC_MODULE_POWER_CONTROLS_WriteMask                            0xFFFF00F7
+#define GC_MODULE_POWER_CONTROLS_ResetValue                           0x00140020
+
+/* Enables module level clock gating. */
+#define GC_MODULE_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING                0 : 0
+#define GC_MODULE_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING_End                0
+#define GC_MODULE_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING_Start              0
+#define GC_MODULE_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING_Type             U01
+
+/* Disables module level clock gating for stall condition. */
+#define GC_MODULE_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING         1 : 1
+#define GC_MODULE_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_End         1
+#define GC_MODULE_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_Start       1
+#define GC_MODULE_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_Type      U01
+
+/* Disables module level clock gating for starve/idle condition. */
+#define GC_MODULE_POWER_CONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING        2 : 2
+#define GC_MODULE_POWER_CONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_End        2
+#define GC_MODULE_POWER_CONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_Start      2
+#define GC_MODULE_POWER_CONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_Type     U01
+
+/* Number of clock cycles to wait after turning on the clock. */
+#define GC_MODULE_POWER_CONTROLS_TURN_ON_COUNTER                           7 : 4
+#define GC_MODULE_POWER_CONTROLS_TURN_ON_COUNTER_End                           7
+#define GC_MODULE_POWER_CONTROLS_TURN_ON_COUNTER_Start                         4
+#define GC_MODULE_POWER_CONTROLS_TURN_ON_COUNTER_Type                        U04
+
+/* Counter value for clock gating the module if the module is idle for  this  **
+** amount of clock cycles.                                                    */
+#define GC_MODULE_POWER_CONTROLS_TURN_OFF_COUNTER                        31 : 16
+#define GC_MODULE_POWER_CONTROLS_TURN_OFF_COUNTER_End                         31
+#define GC_MODULE_POWER_CONTROLS_TURN_OFF_COUNTER_Start                       16
+#define GC_MODULE_POWER_CONTROLS_TURN_OFF_COUNTER_Type                       U16
+
+/*******************************************************************************
+** Register gcModulePowerModuleControl
+*/
+
+/* Module level control registers. */
+
+#define GC_MODULE_POWER_MODULE_CONTROL_Address                           0x00104
+#define GC_MODULE_POWER_MODULE_CONTROL_MSB                                    15
+#define GC_MODULE_POWER_MODULE_CONTROL_LSB                                     0
+#define GC_MODULE_POWER_MODULE_CONTROL_BLK                                     0
+#define GC_MODULE_POWER_MODULE_CONTROL_Count                                   1
+#define GC_MODULE_POWER_MODULE_CONTROL_FieldMask                      0x00000007
+#define GC_MODULE_POWER_MODULE_CONTROL_ReadMask                       0x00000007
+#define GC_MODULE_POWER_MODULE_CONTROL_WriteMask                      0x00000007
+#define GC_MODULE_POWER_MODULE_CONTROL_ResetValue                     0x00000000
+
+/* Disables module level clock gating for FE. */
+#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_FE      0 : 0
+#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_FE_End      0
+#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_FE_Start    0
+#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_FE_Type   U01
+
+/* Disables module level clock gating for DE. */
+#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_DE      1 : 1
+#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_DE_End      1
+#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_DE_Start    1
+#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_DE_Type   U01
+
+/* Disables module level clock gating for PE. */
+#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_PE      2 : 2
+#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_PE_End      2
+#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_PE_Start    2
+#define GC_MODULE_POWER_MODULE_CONTROL_DISABLE_MODULE_CLOCK_GATING_PE_Type   U01
+
+/*******************************************************************************
+** Register gcModulePowerModuleStatus
+*/
+
+/* Module level control status. */
+
+#define GC_MODULE_POWER_MODULE_STATUS_Address                            0x00108
+#define GC_MODULE_POWER_MODULE_STATUS_MSB                                     15
+#define GC_MODULE_POWER_MODULE_STATUS_LSB                                      0
+#define GC_MODULE_POWER_MODULE_STATUS_BLK                                      0
+#define GC_MODULE_POWER_MODULE_STATUS_Count                                    1
+#define GC_MODULE_POWER_MODULE_STATUS_FieldMask                       0x00000007
+#define GC_MODULE_POWER_MODULE_STATUS_ReadMask                        0x00000007
+#define GC_MODULE_POWER_MODULE_STATUS_WriteMask                       0x00000000
+#define GC_MODULE_POWER_MODULE_STATUS_ResetValue                      0x00000000
+
+/* Module level clock gating is ON for FE. */
+#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_FE                0 : 0
+#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_FE_End                0
+#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_FE_Start              0
+#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_FE_Type             U01
+
+/* Module level clock gating is ON for DE. */
+#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_DE                1 : 1
+#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_DE_End                1
+#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_DE_Start              1
+#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_DE_Type             U01
+
+/* Module level clock gating is ON for PE. */
+#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_PE                2 : 2
+#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_PE_End                2
+#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_PE_Start              2
+#define GC_MODULE_POWER_MODULE_STATUS_MODULE_CLOCK_GATED_PE_Type             U01
+
+/*******************************************************************************
+** State gcregSrcAddress
+*/
+
+/* 32-bit aligned base address of the source surface. */
+
+#define gcregSrcAddressRegAddrs                                           0x0480
+#define GCREG_SRC_ADDRESS_MSB                                                 15
+#define GCREG_SRC_ADDRESS_LSB                                                  0
+#define GCREG_SRC_ADDRESS_BLK                                                  0
+#define GCREG_SRC_ADDRESS_Count                                                1
+#define GCREG_SRC_ADDRESS_FieldMask                                   0xFFFFFFFF
+#define GCREG_SRC_ADDRESS_ReadMask                                    0xFFFFFFFC
+#define GCREG_SRC_ADDRESS_WriteMask                                   0xFFFFFFFC
+#define GCREG_SRC_ADDRESS_ResetValue                                  0x00000000
+
+#define GCREG_SRC_ADDRESS_ADDRESS                                         31 : 0
+#define GCREG_SRC_ADDRESS_ADDRESS_End                                         30
+#define GCREG_SRC_ADDRESS_ADDRESS_Start                                        0
+#define GCREG_SRC_ADDRESS_ADDRESS_Type                                       U31
+
+/*******************************************************************************
+** State gcregSrcStride
+*/
+
+/* Stride of the source surface in bytes. To calculate the stride multiply
+** the surface width in pixels (8-pixel aligned) by the number of bytes per
+** pixel.
+*/
+
+#define gcregSrcStrideRegAddrs                                            0x0481
+#define GCREG_SRC_STRIDE_MSB                                                  15
+#define GCREG_SRC_STRIDE_LSB                                                   0
+#define GCREG_SRC_STRIDE_BLK                                                   0
+#define GCREG_SRC_STRIDE_Count                                                 1
+#define GCREG_SRC_STRIDE_FieldMask                                    0x0003FFFF
+#define GCREG_SRC_STRIDE_ReadMask                                     0x0003FFFC
+#define GCREG_SRC_STRIDE_WriteMask                                    0x0003FFFC
+#define GCREG_SRC_STRIDE_ResetValue                                   0x00000000
+
+#define GCREG_SRC_STRIDE_STRIDE                                           17 : 0
+#define GCREG_SRC_STRIDE_STRIDE_End                                           17
+#define GCREG_SRC_STRIDE_STRIDE_Start                                          0
+#define GCREG_SRC_STRIDE_STRIDE_Type                                         U18
+
+/*******************************************************************************
+** State gcregSrcRotationConfig
+*/
+
+/* 90 degree rotation configuration for the source surface. Width field
+** specifies the width of the surface in pixels.
+*/
+
+#define gcregSrcRotationConfigRegAddrs                                    0x0482
+#define GCREG_SRC_ROTATION_CONFIG_MSB                                         15
+#define GCREG_SRC_ROTATION_CONFIG_LSB                                          0
+#define GCREG_SRC_ROTATION_CONFIG_BLK                                          0
+#define GCREG_SRC_ROTATION_CONFIG_Count                                        1
+#define GCREG_SRC_ROTATION_CONFIG_FieldMask                           0x0001FFFF
+#define GCREG_SRC_ROTATION_CONFIG_ReadMask                            0x0001FFFF
+#define GCREG_SRC_ROTATION_CONFIG_WriteMask                           0x0001FFFF
+#define GCREG_SRC_ROTATION_CONFIG_ResetValue                          0x00000000
+
+#define GCREG_SRC_ROTATION_CONFIG_WIDTH                                   15 : 0
+#define GCREG_SRC_ROTATION_CONFIG_WIDTH_End                                   15
+#define GCREG_SRC_ROTATION_CONFIG_WIDTH_Start                                  0
+#define GCREG_SRC_ROTATION_CONFIG_WIDTH_Type                                 U16
+
+#define GCREG_SRC_ROTATION_CONFIG_ROTATION                               16 : 16
+#define GCREG_SRC_ROTATION_CONFIG_ROTATION_End                                16
+#define GCREG_SRC_ROTATION_CONFIG_ROTATION_Start                              16
+#define GCREG_SRC_ROTATION_CONFIG_ROTATION_Type                              U01
+#define   GCREG_SRC_ROTATION_CONFIG_ROTATION_DISABLE                         0x0
+#define   GCREG_SRC_ROTATION_CONFIG_ROTATION_ENABLE                          0x1
+
+struct gcregsrcrotationconfig {
+	/* gcregSrcRotationConfigRegAddrs:GCREG_SRC_ROTATION_CONFIG_WIDTH */
+	unsigned int surf_width:16;
+
+	/* gcregSrcRotationConfigRegAddrs:GCREG_SRC_ROTATION_CONFIG_ROTATION */
+	unsigned int enable:1;
+
+	/* gcregSrcRotationConfigRegAddrs:reserved */
+	unsigned int _reserved_17_31:15;
+};
+
+/*******************************************************************************
+** State gcregSrcConfig
+*/
+
+/* Source surface configuration register. */
+
+#define gcregSrcConfigRegAddrs                                            0x0483
+#define GCREG_SRC_CONFIG_MSB                                                  15
+#define GCREG_SRC_CONFIG_LSB                                                   0
+#define GCREG_SRC_CONFIG_BLK                                                   0
+#define GCREG_SRC_CONFIG_Count                                                 1
+#define GCREG_SRC_CONFIG_FieldMask                                    0xFF31B1FF
+#define GCREG_SRC_CONFIG_ReadMask                                     0xFF31B1FF
+#define GCREG_SRC_CONFIG_WriteMask                                    0xFF31B1FF
+#define GCREG_SRC_CONFIG_ResetValue                                   0x00000000
+
+/* Control source endianess. */
+#define GCREG_SRC_CONFIG_ENDIAN_CONTROL                                  31 : 30
+#define GCREG_SRC_CONFIG_ENDIAN_CONTROL_End                                   31
+#define GCREG_SRC_CONFIG_ENDIAN_CONTROL_Start                                 30
+#define GCREG_SRC_CONFIG_ENDIAN_CONTROL_Type                                 U02
+#define   GCREG_SRC_CONFIG_ENDIAN_CONTROL_NO_SWAP                            0x0
+#define   GCREG_SRC_CONFIG_ENDIAN_CONTROL_SWAP_WORD                          0x1
+#define   GCREG_SRC_CONFIG_ENDIAN_CONTROL_SWAP_DWORD                         0x2
+
+/* Disable 420 L2 cache  NOTE: the field is valid for chips with 420 L2 cache **
+** defined.                                                                   */
+#define GCREG_SRC_CONFIG_DISABLE420_L2_CACHE                             29 : 29
+#define GCREG_SRC_CONFIG_DISABLE420_L2_CACHE_End                              29
+#define GCREG_SRC_CONFIG_DISABLE420_L2_CACHE_Start                            29
+#define GCREG_SRC_CONFIG_DISABLE420_L2_CACHE_Type                            U01
+#define   GCREG_SRC_CONFIG_DISABLE420_L2_CACHE_ENABLED                       0x0
+#define   GCREG_SRC_CONFIG_DISABLE420_L2_CACHE_DISABLED                      0x1
+
+/* Defines the pixel format of the source surface. */
+#define GCREG_SRC_CONFIG_SOURCE_FORMAT                                   28 : 24
+#define GCREG_SRC_CONFIG_SOURCE_FORMAT_End                                    28
+#define GCREG_SRC_CONFIG_SOURCE_FORMAT_Start                                  24
+#define GCREG_SRC_CONFIG_SOURCE_FORMAT_Type                                  U05
+#define   GCREG_SRC_CONFIG_SOURCE_FORMAT_X4R4G4B4                           0x00
+#define   GCREG_SRC_CONFIG_SOURCE_FORMAT_A4R4G4B4                           0x01
+#define   GCREG_SRC_CONFIG_SOURCE_FORMAT_X1R5G5B5                           0x02
+#define   GCREG_SRC_CONFIG_SOURCE_FORMAT_A1R5G5B5                           0x03
+#define   GCREG_SRC_CONFIG_SOURCE_FORMAT_R5G6B5                             0x04
+#define   GCREG_SRC_CONFIG_SOURCE_FORMAT_X8R8G8B8                           0x05
+#define   GCREG_SRC_CONFIG_SOURCE_FORMAT_A8R8G8B8                           0x06
+#define   GCREG_SRC_CONFIG_SOURCE_FORMAT_YUY2                               0x07
+#define   GCREG_SRC_CONFIG_SOURCE_FORMAT_UYVY                               0x08
+#define   GCREG_SRC_CONFIG_SOURCE_FORMAT_INDEX8                             0x09
+#define   GCREG_SRC_CONFIG_SOURCE_FORMAT_MONOCHROME                         0x0A
+#define   GCREG_SRC_CONFIG_SOURCE_FORMAT_YV12                               0x0F
+#define   GCREG_SRC_CONFIG_SOURCE_FORMAT_A8                                 0x10
+#define   GCREG_SRC_CONFIG_SOURCE_FORMAT_NV12                               0x11
+#define   GCREG_SRC_CONFIG_SOURCE_FORMAT_NV16                               0x12
+#define   GCREG_SRC_CONFIG_SOURCE_FORMAT_RG16                               0x13
+
+/* Color channel swizzles. */
+#define GCREG_SRC_CONFIG_SWIZZLE                                         21 : 20
+#define GCREG_SRC_CONFIG_SWIZZLE_End                                          21
+#define GCREG_SRC_CONFIG_SWIZZLE_Start                                        20
+#define GCREG_SRC_CONFIG_SWIZZLE_Type                                        U02
+#define   GCREG_SRC_CONFIG_SWIZZLE_ARGB                                      0x0
+#define   GCREG_SRC_CONFIG_SWIZZLE_RGBA                                      0x1
+#define   GCREG_SRC_CONFIG_SWIZZLE_ABGR                                      0x2
+#define   GCREG_SRC_CONFIG_SWIZZLE_BGRA                                      0x3
+
+/* Mono expansion: if 0, transparency color will be 0, otherwise transparency **
+** color will be 1.                                                           */
+#define GCREG_SRC_CONFIG_MONO_TRANSPARENCY                               15 : 15
+#define GCREG_SRC_CONFIG_MONO_TRANSPARENCY_End                                15
+#define GCREG_SRC_CONFIG_MONO_TRANSPARENCY_Start                              15
+#define GCREG_SRC_CONFIG_MONO_TRANSPARENCY_Type                              U01
+#define   GCREG_SRC_CONFIG_MONO_TRANSPARENCY_BACKGROUND                      0x0
+#define   GCREG_SRC_CONFIG_MONO_TRANSPARENCY_FOREGROUND                      0x1
+
+/* Mono expansion or masked blit: stream packing in pixels. Determines how    **
+** many horizontal pixels are there per each 32-bit chunk. For example, if    **
+** set to Packed8, each 32-bit chunk is 8-pixel wide, which also means that   **
+** it defines 4 vertical lines of pixels.                                     */
+#define GCREG_SRC_CONFIG_PACK                                            13 : 12
+#define GCREG_SRC_CONFIG_PACK_End                                             13
+#define GCREG_SRC_CONFIG_PACK_Start                                           12
+#define GCREG_SRC_CONFIG_PACK_Type                                           U02
+#define   GCREG_SRC_CONFIG_PACK_PACKED8                                      0x0
+#define   GCREG_SRC_CONFIG_PACK_PACKED16                                     0x1
+#define   GCREG_SRC_CONFIG_PACK_PACKED32                                     0x2
+#define   GCREG_SRC_CONFIG_PACK_UNPACKED                                     0x3
+
+/* Source data location: set to STREAM for mono expansion blits or masked     **
+** blits. For mono expansion blits the complete bitmap comes from the command **
+** stream. For masked blits the source data comes from the memory and the     **
+** mask from the command stream.                                              */
+#define GCREG_SRC_CONFIG_LOCATION                                          8 : 8
+#define GCREG_SRC_CONFIG_LOCATION_End                                          8
+#define GCREG_SRC_CONFIG_LOCATION_Start                                        8
+#define GCREG_SRC_CONFIG_LOCATION_Type                                       U01
+#define   GCREG_SRC_CONFIG_LOCATION_MEMORY                                   0x0
+#define   GCREG_SRC_CONFIG_LOCATION_STREAM                                   0x1
+
+/* Source linear/tiled address computation control. */
+#define GCREG_SRC_CONFIG_TILED                                             7 : 7
+#define GCREG_SRC_CONFIG_TILED_End                                             7
+#define GCREG_SRC_CONFIG_TILED_Start                                           7
+#define GCREG_SRC_CONFIG_TILED_Type                                          U01
+#define   GCREG_SRC_CONFIG_TILED_DISABLED                                    0x0
+#define   GCREG_SRC_CONFIG_TILED_ENABLED                                     0x1
+
+/* If set to ABSOLUTE, the source coordinates are treated as absolute         **
+** coordinates inside the source surface. If set to RELATIVE, the source      **
+** coordinates are treated as the offsets from the destination coordinates    **
+** with the source size equal to the size of the destination.                 */
+#define GCREG_SRC_CONFIG_SRC_RELATIVE                                      6 : 6
+#define GCREG_SRC_CONFIG_SRC_RELATIVE_End                                      6
+#define GCREG_SRC_CONFIG_SRC_RELATIVE_Start                                    6
+#define GCREG_SRC_CONFIG_SRC_RELATIVE_Type                                   U01
+#define   GCREG_SRC_CONFIG_SRC_RELATIVE_ABSOLUTE                             0x0
+#define   GCREG_SRC_CONFIG_SRC_RELATIVE_RELATIVE                             0x1
+
+struct gcregsrcconfig {
+	/* gcregSrcConfigRegAddrs:reserved */
+	unsigned int _reserved_0_5:6;
+
+	/* gcregSrcConfigRegAddrs:GCREG_SRC_CONFIG_SRC_RELATIVE */
+	unsigned int relative:1;
+
+	/* gcregSrcConfigRegAddrs:GCREG_SRC_CONFIG_TILED */
+	unsigned int tiled:1;
+
+	/* gcregSrcConfigRegAddrs:GCREG_SRC_CONFIG_LOCATION */
+	unsigned int stream:1;
+
+	/* gcregSrcConfigRegAddrs:reserved */
+	unsigned int _reserved_9_11:3;
+
+	/* gcregSrcConfigRegAddrs:GCREG_SRC_CONFIG_PACK */
+	unsigned int monopack:2;
+
+	/* gcregSrcConfigRegAddrs:reserved */
+	unsigned int _reserved_14:1;
+
+	/* gcregSrcConfigRegAddrs:GCREG_SRC_CONFIG_MONO_TRANSPARENCY */
+	unsigned int monotransp:1;
+
+	/* gcregSrcConfigRegAddrs:reserved */
+	unsigned int _reserved_16_19:4;
+
+	/* gcregSrcConfigRegAddrs:GCREG_SRC_CONFIG_SWIZZLE */
+	unsigned int swizzle:2;
+
+	/* gcregSrcConfigRegAddrs:reserved */
+	unsigned int _reserved_22_23:2;
+
+	/* gcregSrcConfigRegAddrs:GCREG_SRC_CONFIG_SOURCE_FORMAT */
+	unsigned int format:5;
+
+	/* gcregSrcConfigRegAddrs:GCREG_SRC_CONFIG_DISABLE420_L2_CACHE */
+	unsigned int disable420L2cache:1;
+
+	/* gcregSrcConfigRegAddrs:GCREG_SRC_CONFIG_ENDIAN_CONTROL */
+	unsigned int endian:2;
+};
+
+/*******************************************************************************
+** State gcregSrcOrigin
+*/
+
+/* Absolute or relative (see SRC_RELATIVE field of gcregSrcConfig register) X
+** and Y coordinates in pixels of the top left corner of the source rectangle
+** within the source surface.
+*/
+
+#define gcregSrcOriginRegAddrs                                            0x0484
+#define GCREG_SRC_ORIGIN_MSB                                                  15
+#define GCREG_SRC_ORIGIN_LSB                                                   0
+#define GCREG_SRC_ORIGIN_BLK                                                   0
+#define GCREG_SRC_ORIGIN_Count                                                 1
+#define GCREG_SRC_ORIGIN_FieldMask                                    0xFFFFFFFF
+#define GCREG_SRC_ORIGIN_ReadMask                                     0xFFFFFFFF
+#define GCREG_SRC_ORIGIN_WriteMask                                    0xFFFFFFFF
+#define GCREG_SRC_ORIGIN_ResetValue                                   0x00000000
+
+#define GCREG_SRC_ORIGIN_Y                                               31 : 16
+#define GCREG_SRC_ORIGIN_Y_End                                                31
+#define GCREG_SRC_ORIGIN_Y_Start                                              16
+#define GCREG_SRC_ORIGIN_Y_Type                                              U16
+
+#define GCREG_SRC_ORIGIN_X                                                15 : 0
+#define GCREG_SRC_ORIGIN_X_End                                                15
+#define GCREG_SRC_ORIGIN_X_Start                                               0
+#define GCREG_SRC_ORIGIN_X_Type                                              U16
+
+struct gcregsrcorigin {
+	/* gcregSrcOriginRegAddrs:GCREG_SRC_ORIGIN_X */
+	unsigned int x:16;
+
+	/* gcregSrcOriginRegAddrs:GCREG_SRC_ORIGIN_Y */
+	unsigned int y:16;
+};
+
+static const struct gcregsrcorigin gcregsrcorigin_min = {
+	/* gcregSrcOriginRegAddrs:GCREG_SRC_ORIGIN_X */
+	0,
+
+	/* gcregSrcOriginRegAddrs:GCREG_SRC_ORIGIN_Y */
+	0
+};
+
+/*******************************************************************************
+** State gcregSrcSize
+*/
+
+/* Width and height of the source rectangle in pixels. If the source is
+** relative (see SRC_RELATIVE field of gcregSrcConfig register) or a regular
+** bitblt is being performed without stretching, this register is ignored and
+** the source size is assumed to be the same as the destination.
+*/
+
+#define gcregSrcSizeRegAddrs                                              0x0485
+#define GCREG_SRC_SIZE_MSB                                                    15
+#define GCREG_SRC_SIZE_LSB                                                     0
+#define GCREG_SRC_SIZE_BLK                                                     0
+#define GCREG_SRC_SIZE_Count                                                   1
+#define GCREG_SRC_SIZE_FieldMask                                      0xFFFFFFFF
+#define GCREG_SRC_SIZE_ReadMask                                       0xFFFFFFFF
+#define GCREG_SRC_SIZE_WriteMask                                      0xFFFFFFFF
+#define GCREG_SRC_SIZE_ResetValue                                     0x00000000
+
+#define GCREG_SRC_SIZE_Y                                                 31 : 16
+#define GCREG_SRC_SIZE_Y_End                                                  31
+#define GCREG_SRC_SIZE_Y_Start                                                16
+#define GCREG_SRC_SIZE_Y_Type                                                U16
+
+#define GCREG_SRC_SIZE_X                                                  15 : 0
+#define GCREG_SRC_SIZE_X_End                                                  15
+#define GCREG_SRC_SIZE_X_Start                                                 0
+#define GCREG_SRC_SIZE_X_Type                                                U16
+
+struct gcregsrcsize {
+	/* gcregSrcOriginRegAddrs:GCREG_SRC_SIZE_X */
+	unsigned int width:16;
+
+	/* gcregSrcOriginRegAddrs:GCREG_SRC_SIZE_Y */
+	unsigned int height:16;
+};
+
+static const struct gcregsrcsize gcregsrcsize_max = {
+	/* gcregSrcOriginRegAddrs:GCREG_SRC_SIZE_X */
+	32767,
+
+	/* gcregSrcOriginRegAddrs:GCREG_SRC_SIZE_Y */
+	32767
+};
+
+/*******************************************************************************
+** State gcregSrcColorBg
+*/
+
+/* In mono expansion defines the source color if the mono pixel is 0. The color
+** must be set in A8R8G8B8 format. In color blits defines the source
+** transparency color and must be of the same format as the source surface.
+*/
+
+#define gcregSrcColorBgRegAddrs                                           0x0486
+#define GCREG_SRC_COLOR_BG_MSB                                                15
+#define GCREG_SRC_COLOR_BG_LSB                                                 0
+#define GCREG_SRC_COLOR_BG_BLK                                                 0
+#define GCREG_SRC_COLOR_BG_Count                                               1
+#define GCREG_SRC_COLOR_BG_FieldMask                                  0xFFFFFFFF
+#define GCREG_SRC_COLOR_BG_ReadMask                                   0xFFFFFFFF
+#define GCREG_SRC_COLOR_BG_WriteMask                                  0xFFFFFFFF
+#define GCREG_SRC_COLOR_BG_ResetValue                                 0x00000000
+
+#define GCREG_SRC_COLOR_BG_ALPHA                                         31 : 24
+#define GCREG_SRC_COLOR_BG_ALPHA_End                                          31
+#define GCREG_SRC_COLOR_BG_ALPHA_Start                                        24
+#define GCREG_SRC_COLOR_BG_ALPHA_Type                                        U08
+
+#define GCREG_SRC_COLOR_BG_RED                                           23 : 16
+#define GCREG_SRC_COLOR_BG_RED_End                                            23
+#define GCREG_SRC_COLOR_BG_RED_Start                                          16
+#define GCREG_SRC_COLOR_BG_RED_Type                                          U08
+
+#define GCREG_SRC_COLOR_BG_GREEN                                          15 : 8
+#define GCREG_SRC_COLOR_BG_GREEN_End                                          15
+#define GCREG_SRC_COLOR_BG_GREEN_Start                                         8
+#define GCREG_SRC_COLOR_BG_GREEN_Type                                        U08
+
+#define GCREG_SRC_COLOR_BG_BLUE                                            7 : 0
+#define GCREG_SRC_COLOR_BG_BLUE_End                                            7
+#define GCREG_SRC_COLOR_BG_BLUE_Start                                          0
+#define GCREG_SRC_COLOR_BG_BLUE_Type                                         U08
+
+/*******************************************************************************
+** State gcregSrcColorFg
+*/
+
+/* In mono expansion defines the source color if the mono pixel is 1. The color
+** must be set in A8R8G8B8.
+*/
+
+#define gcregSrcColorFgRegAddrs                                           0x0487
+#define GCREG_SRC_COLOR_FG_MSB                                                15
+#define GCREG_SRC_COLOR_FG_LSB                                                 0
+#define GCREG_SRC_COLOR_FG_BLK                                                 0
+#define GCREG_SRC_COLOR_FG_Count                                               1
+#define GCREG_SRC_COLOR_FG_FieldMask                                  0xFFFFFFFF
+#define GCREG_SRC_COLOR_FG_ReadMask                                   0xFFFFFFFF
+#define GCREG_SRC_COLOR_FG_WriteMask                                  0xFFFFFFFF
+#define GCREG_SRC_COLOR_FG_ResetValue                                 0x00000000
+
+#define GCREG_SRC_COLOR_FG_ALPHA                                         31 : 24
+#define GCREG_SRC_COLOR_FG_ALPHA_End                                          31
+#define GCREG_SRC_COLOR_FG_ALPHA_Start                                        24
+#define GCREG_SRC_COLOR_FG_ALPHA_Type                                        U08
+
+#define GCREG_SRC_COLOR_FG_RED                                           23 : 16
+#define GCREG_SRC_COLOR_FG_RED_End                                            23
+#define GCREG_SRC_COLOR_FG_RED_Start                                          16
+#define GCREG_SRC_COLOR_FG_RED_Type                                          U08
+
+#define GCREG_SRC_COLOR_FG_GREEN                                          15 : 8
+#define GCREG_SRC_COLOR_FG_GREEN_End                                          15
+#define GCREG_SRC_COLOR_FG_GREEN_Start                                         8
+#define GCREG_SRC_COLOR_FG_GREEN_Type                                        U08
+
+#define GCREG_SRC_COLOR_FG_BLUE                                            7 : 0
+#define GCREG_SRC_COLOR_FG_BLUE_End                                            7
+#define GCREG_SRC_COLOR_FG_BLUE_Start                                          0
+#define GCREG_SRC_COLOR_FG_BLUE_Type                                         U08
+
+/*******************************************************************************
+** State gcregStretchFactorLow
+*/
+
+#define gcregStretchFactorLowRegAddrs                                     0x0488
+#define GCREG_STRETCH_FACTOR_LOW_MSB                                          15
+#define GCREG_STRETCH_FACTOR_LOW_LSB                                           0
+#define GCREG_STRETCH_FACTOR_LOW_BLK                                           0
+#define GCREG_STRETCH_FACTOR_LOW_Count                                         1
+#define GCREG_STRETCH_FACTOR_LOW_FieldMask                            0x7FFFFFFF
+#define GCREG_STRETCH_FACTOR_LOW_ReadMask                             0x7FFFFFFF
+#define GCREG_STRETCH_FACTOR_LOW_WriteMask                            0x7FFFFFFF
+#define GCREG_STRETCH_FACTOR_LOW_ResetValue                           0x00000000
+
+/* Horizontal stretch factor in 15.16 fixed point format. The value is        **
+** calculated using the following formula: factor = ((srcWidth - 1) << 16) /  **
+** (dstWidth - 1). Stretch blit uses only the integer part of the value,      **
+** while Filter blit uses all 31 bits.                                        */
+#define GCREG_STRETCH_FACTOR_LOW_X                                        30 : 0
+#define GCREG_STRETCH_FACTOR_LOW_X_End                                        30
+#define GCREG_STRETCH_FACTOR_LOW_X_Start                                       0
+#define GCREG_STRETCH_FACTOR_LOW_X_Type                                      U31
+
+/*******************************************************************************
+** State gcregStretchFactorHigh
+*/
+
+#define gcregStretchFactorHighRegAddrs                                    0x0489
+#define GCREG_STRETCH_FACTOR_HIGH_MSB                                         15
+#define GCREG_STRETCH_FACTOR_HIGH_LSB                                          0
+#define GCREG_STRETCH_FACTOR_LOW_HIGH_BLK                                      0
+#define GCREG_STRETCH_FACTOR_HIGH_Count                                        1
+#define GCREG_STRETCH_FACTOR_HIGH_FieldMask                           0x7FFFFFFF
+#define GCREG_STRETCH_FACTOR_HIGH_ReadMask                            0x7FFFFFFF
+#define GCREG_STRETCH_FACTOR_HIGH_WriteMask                           0x7FFFFFFF
+#define GCREG_STRETCH_FACTOR_HIGH_ResetValue                          0x00000000
+
+/* Vertical stretch factor in 15.16 fixed point format. The value is          **
+** calculated using the following formula: factor = ((srcHeight - 1) << 16) / **
+** (dstHeight - 1). Stretch blit uses only the integer part of the value,     **
+** while Filter blit uses all 31 bits.                                        */
+#define GCREG_STRETCH_FACTOR_HIGH_Y                                       30 : 0
+#define GCREG_STRETCH_FACTOR_HIGH_Y_End                                       30
+#define GCREG_STRETCH_FACTOR_HIGH_Y_Start                                      0
+#define GCREG_STRETCH_FACTOR_HIGH_Y_Type                                     U31
+
+/*******************************************************************************
+** State gcregDestAddress
+*/
+
+/* 32-bit aligned base address of the destination surface. */
+
+#define gcregDestAddressRegAddrs                                          0x048A
+#define GCREG_DEST_ADDRESS_MSB                                                15
+#define GCREG_DEST_ADDRESS_LSB                                                 0
+#define GCREG_DEST_ADDRESS_BLK                                                 0
+#define GCREG_DEST_ADDRESS_Count                                               1
+#define GCREG_DEST_ADDRESS_FieldMask                                  0xFFFFFFFF
+#define GCREG_DEST_ADDRESS_ReadMask                                   0xFFFFFFFC
+#define GCREG_DEST_ADDRESS_WriteMask                                  0xFFFFFFFC
+#define GCREG_DEST_ADDRESS_ResetValue                                 0x00000000
+
+#define GCREG_DEST_ADDRESS_ADDRESS                                        31 : 0
+#define GCREG_DEST_ADDRESS_ADDRESS_End                                        30
+#define GCREG_DEST_ADDRESS_ADDRESS_Start                                       0
+#define GCREG_DEST_ADDRESS_ADDRESS_Type                                      U31
+
+/*******************************************************************************
+** State gcregDestStride
+*/
+
+/* Stride of the destination surface in bytes. To calculate the stride
+** multiply the surface width in pixels (8-pixel aligned) by the number of
+** bytes per pixel.
+*/
+
+#define gcregDestStrideRegAddrs                                           0x048B
+#define GCREG_DEST_STRIDE_MSB                                                 15
+#define GCREG_DEST_STRIDE_LSB                                                  0
+#define GCREG_DEST_STRIDE_BLK                                                  0
+#define GCREG_DEST_STRIDE_Count                                                1
+#define GCREG_DEST_STRIDE_FieldMask                                   0x0003FFFF
+#define GCREG_DEST_STRIDE_ReadMask                                    0x0003FFFC
+#define GCREG_DEST_STRIDE_WriteMask                                   0x0003FFFC
+#define GCREG_DEST_STRIDE_ResetValue                                  0x00000000
+
+#define GCREG_DEST_STRIDE_STRIDE                                          17 : 0
+#define GCREG_DEST_STRIDE_STRIDE_End                                          17
+#define GCREG_DEST_STRIDE_STRIDE_Start                                         0
+#define GCREG_DEST_STRIDE_STRIDE_Type                                        U18
+
+/*******************************************************************************
+** State gcregDestRotationConfig
+*/
+
+/* 90 degree rotation configuration for the destination surface. Width field
+** specifies the width of the surface in pixels.
+*/
+
+#define gcregDestRotationConfigRegAddrs                                   0x048C
+#define GCREG_DEST_ROTATION_CONFIG_MSB                                        15
+#define GCREG_DEST_ROTATION_CONFIG_LSB                                         0
+#define GCREG_DEST_ROTATION_CONFIG_BLK                                         0
+#define GCREG_DEST_ROTATION_CONFIG_Count                                       1
+#define GCREG_DEST_ROTATION_CONFIG_FieldMask                          0x0001FFFF
+#define GCREG_DEST_ROTATION_CONFIG_ReadMask                           0x0001FFFF
+#define GCREG_DEST_ROTATION_CONFIG_WriteMask                          0x0001FFFF
+#define GCREG_DEST_ROTATION_CONFIG_ResetValue                         0x00000000
+
+#define GCREG_DEST_ROTATION_CONFIG_WIDTH                                  15 : 0
+#define GCREG_DEST_ROTATION_CONFIG_WIDTH_End                                  15
+#define GCREG_DEST_ROTATION_CONFIG_WIDTH_Start                                 0
+#define GCREG_DEST_ROTATION_CONFIG_WIDTH_Type                                U16
+
+#define GCREG_DEST_ROTATION_CONFIG_ROTATION                              16 : 16
+#define GCREG_DEST_ROTATION_CONFIG_ROTATION_End                               16
+#define GCREG_DEST_ROTATION_CONFIG_ROTATION_Start                             16
+#define GCREG_DEST_ROTATION_CONFIG_ROTATION_Type                             U01
+#define   GCREG_DEST_ROTATION_CONFIG_ROTATION_DISABLE                        0x0
+#define   GCREG_DEST_ROTATION_CONFIG_ROTATION_ENABLE                         0x1
+
+struct gcregdstrotationconfig {
+	/* gcregDestRotationConfigRegAddrs:GCREG_DEST_ROTATION_CONFIG_WIDTH */
+	unsigned int surf_width:16;
+
+	/* gcregDestRotationConfigRegAddrs:GCREG_DEST_ROTATION_CONFIG_ROTATION*/
+	unsigned int enable:1;
+
+	/* gcregDestRotationConfigRegAddrs:reserved */
+	unsigned int _reserved_17_31:15;
+};
+
+/*******************************************************************************
+** State gcregDestConfig
+*/
+
+/* Destination surface configuration register. */
+
+#define gcregDestConfigRegAddrs                                           0x048D
+#define GCREG_DEST_CONFIG_MSB                                                 15
+#define GCREG_DEST_CONFIG_LSB                                                  0
+#define GCREG_DEST_CONFIG_BLK                                                  0
+#define GCREG_DEST_CONFIG_Count                                                1
+#define GCREG_DEST_CONFIG_FieldMask                                   0x0733F11F
+#define GCREG_DEST_CONFIG_ReadMask                                    0x0733F11F
+#define GCREG_DEST_CONFIG_WriteMask                                   0x0733F11F
+#define GCREG_DEST_CONFIG_ResetValue                                  0x00000000
+
+/* MinorTile. */
+#define GCREG_DEST_CONFIG_MINOR_TILED                                    26 : 26
+#define GCREG_DEST_CONFIG_MINOR_TILED_End                                     26
+#define GCREG_DEST_CONFIG_MINOR_TILED_Start                                   26
+#define GCREG_DEST_CONFIG_MINOR_TILED_Type                                   U01
+#define   GCREG_DEST_CONFIG_MINOR_TILED_DISABLED                             0x0
+#define   GCREG_DEST_CONFIG_MINOR_TILED_ENABLED                              0x1
+
+/* Performance fix for de. */
+#define GCREG_DEST_CONFIG_INTER_TILE_PER_FIX                             25 : 25
+#define GCREG_DEST_CONFIG_INTER_TILE_PER_FIX_End                              25
+#define GCREG_DEST_CONFIG_INTER_TILE_PER_FIX_Start                            25
+#define GCREG_DEST_CONFIG_INTER_TILE_PER_FIX_Type                            U01
+#define   GCREG_DEST_CONFIG_INTER_TILE_PER_FIX_DISABLED                      0x1
+#define   GCREG_DEST_CONFIG_INTER_TILE_PER_FIX_ENABLED                       0x0
+
+/* Control GDI Strecth Blit. */
+#define GCREG_DEST_CONFIG_GDI_STRE                                       24 : 24
+#define GCREG_DEST_CONFIG_GDI_STRE_End                                        24
+#define GCREG_DEST_CONFIG_GDI_STRE_Start                                      24
+#define GCREG_DEST_CONFIG_GDI_STRE_Type                                      U01
+#define   GCREG_DEST_CONFIG_GDI_STRE_DISABLED                                0x0
+#define   GCREG_DEST_CONFIG_GDI_STRE_ENABLED                                 0x1
+
+/* Control destination endianess. */
+#define GCREG_DEST_CONFIG_ENDIAN_CONTROL                                 21 : 20
+#define GCREG_DEST_CONFIG_ENDIAN_CONTROL_End                                  21
+#define GCREG_DEST_CONFIG_ENDIAN_CONTROL_Start                                20
+#define GCREG_DEST_CONFIG_ENDIAN_CONTROL_Type                                U02
+#define   GCREG_DEST_CONFIG_ENDIAN_CONTROL_NO_SWAP                           0x0
+#define   GCREG_DEST_CONFIG_ENDIAN_CONTROL_SWAP_WORD                         0x1
+#define   GCREG_DEST_CONFIG_ENDIAN_CONTROL_SWAP_DWORD                        0x2
+
+/* Color channel swizzles. */
+#define GCREG_DEST_CONFIG_SWIZZLE                                        17 : 16
+#define GCREG_DEST_CONFIG_SWIZZLE_End                                         17
+#define GCREG_DEST_CONFIG_SWIZZLE_Start                                       16
+#define GCREG_DEST_CONFIG_SWIZZLE_Type                                       U02
+#define   GCREG_DEST_CONFIG_SWIZZLE_ARGB                                     0x0
+#define   GCREG_DEST_CONFIG_SWIZZLE_RGBA                                     0x1
+#define   GCREG_DEST_CONFIG_SWIZZLE_ABGR                                     0x2
+#define   GCREG_DEST_CONFIG_SWIZZLE_BGRA                                     0x3
+
+/* Determines the type of primitive to be rendered. BIT_BLT_REVERSED and      **
+** INVALID_COMMAND values are defined for internal use and should not be      **
+** used.                                                                      */
+#define GCREG_DEST_CONFIG_COMMAND                                        15 : 12
+#define GCREG_DEST_CONFIG_COMMAND_End                                         15
+#define GCREG_DEST_CONFIG_COMMAND_Start                                       12
+#define GCREG_DEST_CONFIG_COMMAND_Type                                       U04
+#define   GCREG_DEST_CONFIG_COMMAND_CLEAR                                    0x0
+#define   GCREG_DEST_CONFIG_COMMAND_LINE                                     0x1
+#define   GCREG_DEST_CONFIG_COMMAND_BIT_BLT                                  0x2
+#define   GCREG_DEST_CONFIG_COMMAND_BIT_BLT_REVERSED                         0x3
+#define   GCREG_DEST_CONFIG_COMMAND_STRETCH_BLT                              0x4
+#define   GCREG_DEST_CONFIG_COMMAND_HOR_FILTER_BLT                           0x5
+#define   GCREG_DEST_CONFIG_COMMAND_VER_FILTER_BLT                           0x6
+#define   GCREG_DEST_CONFIG_COMMAND_ONE_PASS_FILTER_BLT                      0x7
+#define   GCREG_DEST_CONFIG_COMMAND_MULTI_SOURCE_BLT                         0x8
+
+/* Destination linear/tiled address computation control. Reserved field for   **
+** future expansion. */
+#define GCREG_DEST_CONFIG_TILED                                            8 : 8
+#define GCREG_DEST_CONFIG_TILED_End                                            8
+#define GCREG_DEST_CONFIG_TILED_Start                                          8
+#define GCREG_DEST_CONFIG_TILED_Type                                         U01
+#define   GCREG_DEST_CONFIG_TILED_DISABLED                                   0x0
+#define   GCREG_DEST_CONFIG_TILED_ENABLED                                    0x1
+
+/* Defines the pixel format of the destination surface. */
+#define GCREG_DEST_CONFIG_FORMAT                                           4 : 0
+#define GCREG_DEST_CONFIG_FORMAT_End                                           4
+#define GCREG_DEST_CONFIG_FORMAT_Start                                         0
+#define GCREG_DEST_CONFIG_FORMAT_Type                                        U05
+#define   GCREG_DEST_CONFIG_FORMAT_X4R4G4B4                                 0x00
+#define   GCREG_DEST_CONFIG_FORMAT_A4R4G4B4                                 0x01
+#define   GCREG_DEST_CONFIG_FORMAT_X1R5G5B5                                 0x02
+#define   GCREG_DEST_CONFIG_FORMAT_A1R5G5B5                                 0x03
+#define   GCREG_DEST_CONFIG_FORMAT_R5G6B5                                   0x04
+#define   GCREG_DEST_CONFIG_FORMAT_X8R8G8B8                                 0x05
+#define   GCREG_DEST_CONFIG_FORMAT_A8R8G8B8                                 0x06
+#define   GCREG_DEST_CONFIG_FORMAT_YUY2                                     0x07
+#define   GCREG_DEST_CONFIG_FORMAT_UYVY                                     0x08
+#define   GCREG_DEST_CONFIG_FORMAT_INDEX8                                   0x09
+#define   GCREG_DEST_CONFIG_FORMAT_MONOCHROME                               0x0A
+#define   GCREG_DEST_CONFIG_FORMAT_YV12                                     0x0F
+#define   GCREG_DEST_CONFIG_FORMAT_A8                                       0x10
+#define   GCREG_DEST_CONFIG_FORMAT_NV12                                     0x11
+#define   GCREG_DEST_CONFIG_FORMAT_NV16                                     0x12
+#define   GCREG_DEST_CONFIG_FORMAT_RG16                                     0x13
+
+struct gcregdstconfig {
+	/* gcregDestConfigRegAddrs:GCREG_DEST_CONFIG_FORMAT */
+	unsigned int format:5;
+
+	/* gcregDestConfigRegAddrs:reserved */
+	unsigned int _reserved_5_7:3;
+
+	/* gcregDestConfigRegAddrs:GCREG_DEST_CONFIG_TILED */
+	unsigned int tiled:1;
+
+	/* gcregDestConfigRegAddrs:reserved */
+	unsigned int _reserved_9_11:3;
+
+	/* gcregDestConfigRegAddrs:GCREG_DEST_CONFIG_COMMAND */
+	unsigned int command:4;
+
+	/* gcregDestConfigRegAddrs:GCREG_DEST_CONFIG_SWIZZLE */
+	unsigned int swizzle:2;
+
+	/* gcregDestConfigRegAddrs:reserved */
+	unsigned int _reserved_18_19:2;
+
+	/* gcregDestConfigRegAddrs:GCREG_DEST_CONFIG_ENDIAN_CONTROL */
+	unsigned int endian:2;
+
+	/* gcregDestConfigRegAddrs:reserved */
+	unsigned int _reserved_22_23:2;
+
+	/* gcregDestConfigRegAddrs:GCREG_DEST_CONFIG_GDI_STRE */
+	unsigned int gdi:1;
+
+	/* gcregDestConfigRegAddrs:GCREG_DEST_CONFIG_INTER_TILE_PER_FIX */
+	unsigned int inner_tile_fix:1;
+
+	/* gcregDestConfigRegAddrs:GCREG_DEST_CONFIG_MINOR_TILED */
+	unsigned int minor_tile:1;
+
+	/* gcregDestConfigRegAddrs:reserved */
+	unsigned int _reserved_27_31:5;
+};
+
+/*******************************************************************************
+** State gcregFilterKernel
+*/
+
+/* Filter blit coefficient table. The algorithm uses 5 bits of pixel
+** coordinate's fraction to index the kernel array, which makes it a 32-entry
+** array. Each entry consists of 9 kernel values. In practice we store only a
+** half of the table, because the other half is a mirror of the first,
+** therefore:
+**     rows_to_store    = 32 / 2 + 1 = 17
+**     values_to_store  = rows_to_store * 9 = 153
+**     even_value_count = (values_to_store + 1) & ~1 = 154
+**     dword_count      = even_value_count / 2 = 77
+*/
+
+#define gcregFilterKernelRegAddrs                                         0x0600
+#define GCREG_FILTER_KERNEL_MSB                                               15
+#define GCREG_FILTER_KERNEL_LSB                                                7
+#define GCREG_FILTER_KERNEL_BLK                                                7
+#define GCREG_FILTER_KERNEL_Count                                            128
+#define GCREG_FILTER_KERNEL_FieldMask                                 0xFFFFFFFF
+#define GCREG_FILTER_KERNEL_ReadMask                                  0xFFFFFFFF
+#define GCREG_FILTER_KERNEL_WriteMask                                 0xFFFFFFFF
+#define GCREG_FILTER_KERNEL_ResetValue                                0x00000000
+
+#define GCREG_FILTER_KERNEL_COEFFICIENT0                                  15 : 0
+#define GCREG_FILTER_KERNEL_COEFFICIENT0_End                                  15
+#define GCREG_FILTER_KERNEL_COEFFICIENT0_Start                                 0
+#define GCREG_FILTER_KERNEL_COEFFICIENT0_Type                                U16
+
+#define GCREG_FILTER_KERNEL_COEFFICIENT1                                 31 : 16
+#define GCREG_FILTER_KERNEL_COEFFICIENT1_End                                  31
+#define GCREG_FILTER_KERNEL_COEFFICIENT1_Start                                16
+#define GCREG_FILTER_KERNEL_COEFFICIENT1_Type                                U16
+
+/*******************************************************************************
+** State gcregHoriFilterKernel
+*/
+
+/* One Pass filter Filter blit hori coefficient table. */
+
+#define gcregHoriFilterKernelRegAddrs                                     0x0A00
+#define GCREG_HORI_FILTER_KERNEL_MSB                                          15
+#define GCREG_HORI_FILTER_KERNEL_LSB                                           7
+#define GCREG_HORI_FILTER_KERNEL_BLK                                           7
+#define GCREG_HORI_FILTER_KERNEL_Count                                       128
+#define GCREG_HORI_FILTER_KERNEL_FieldMask                            0xFFFFFFFF
+#define GCREG_HORI_FILTER_KERNEL_ReadMask                             0xFFFFFFFF
+#define GCREG_HORI_FILTER_KERNEL_WriteMask                            0xFFFFFFFF
+#define GCREG_HORI_FILTER_KERNEL_ResetValue                           0x00000000
+
+#define GCREG_HORI_FILTER_KERNEL_COEFFICIENT0                             15 : 0
+#define GCREG_HORI_FILTER_KERNEL_COEFFICIENT0_End                             15
+#define GCREG_HORI_FILTER_KERNEL_COEFFICIENT0_Start                            0
+#define GCREG_HORI_FILTER_KERNEL_COEFFICIENT0_Type                           U16
+
+#define GCREG_HORI_FILTER_KERNEL_COEFFICIENT1                            31 : 16
+#define GCREG_HORI_FILTER_KERNEL_COEFFICIENT1_End                             31
+#define GCREG_HORI_FILTER_KERNEL_COEFFICIENT1_Start                           16
+#define GCREG_HORI_FILTER_KERNEL_COEFFICIENT1_Type                           U16
+
+/*******************************************************************************
+** State gcregVertiFilterKernel
+*/
+
+/* One Pass Filter blit vertical coefficient table. */
+
+#define gcregVertiFilterKernelRegAddrs                                    0x0A80
+#define GCREG_VERTI_FILTER_KERNEL_MSB                                         15
+#define GCREG_VERTI_FILTER_KERNEL_LSB                                          7
+#define GCREG_VERTI_FILTER_KERNEL_BLK                                          7
+#define GCREG_VERTI_FILTER_KERNEL_Count                                      128
+#define GCREG_VERTI_FILTER_KERNEL_FieldMask                           0xFFFFFFFF
+#define GCREG_VERTI_FILTER_KERNEL_ReadMask                            0xFFFFFFFF
+#define GCREG_VERTI_FILTER_KERNEL_WriteMask                           0xFFFFFFFF
+#define GCREG_VERTI_FILTER_KERNEL_ResetValue                          0x00000000
+
+#define GCREG_VERTI_FILTER_KERNEL_COEFFICIENT0                            15 : 0
+#define GCREG_VERTI_FILTER_KERNEL_COEFFICIENT0_End                            15
+#define GCREG_VERTI_FILTER_KERNEL_COEFFICIENT0_Start                           0
+#define GCREG_VERTI_FILTER_KERNEL_COEFFICIENT0_Type                          U16
+
+#define GCREG_VERTI_FILTER_KERNEL_COEFFICIENT1                           31 : 16
+#define GCREG_VERTI_FILTER_KERNEL_COEFFICIENT1_End                            31
+#define GCREG_VERTI_FILTER_KERNEL_COEFFICIENT1_Start                          16
+#define GCREG_VERTI_FILTER_KERNEL_COEFFICIENT1_Type                          U16
+
+/*******************************************************************************
+** State gcregVRSourceImageLow
+*/
+
+/* Bounding box of the source image. */
+
+#define gcregVRSourceImageLowRegAddrs                                     0x04A6
+#define GCREG_VR_SOURCE_IMAGE_LOW_Address                                0x01298
+#define GCREG_VR_SOURCE_IMAGE_LOW_MSB                                         15
+#define GCREG_VR_SOURCE_IMAGE_LOW_LSB                                          0
+#define GCREG_VR_SOURCE_IMAGE_LOW_BLK                                          0
+#define GCREG_VR_SOURCE_IMAGE_LOW_Count                                        1
+#define GCREG_VR_SOURCE_IMAGE_LOW_FieldMask                           0xFFFFFFFF
+#define GCREG_VR_SOURCE_IMAGE_LOW_ReadMask                            0xFFFFFFFF
+#define GCREG_VR_SOURCE_IMAGE_LOW_WriteMask                           0xFFFFFFFF
+#define GCREG_VR_SOURCE_IMAGE_LOW_ResetValue                          0x00000000
+
+#define GCREG_VR_SOURCE_IMAGE_LOW_LEFT                                    15 : 0
+#define GCREG_VR_SOURCE_IMAGE_LOW_LEFT_End                                    15
+#define GCREG_VR_SOURCE_IMAGE_LOW_LEFT_Start                                   0
+#define GCREG_VR_SOURCE_IMAGE_LOW_LEFT_Type                                  U16
+
+#define GCREG_VR_SOURCE_IMAGE_LOW_TOP                                    31 : 16
+#define GCREG_VR_SOURCE_IMAGE_LOW_TOP_End                                     31
+#define GCREG_VR_SOURCE_IMAGE_LOW_TOP_Start                                   16
+#define GCREG_VR_SOURCE_IMAGE_LOW_TOP_Type                                   U16
+
+/*******************************************************************************
+** State gcregVRSourceImageHigh
+*/
+
+#define gcregVRSourceImageHighRegAddrs                                    0x04A7
+#define GCREG_VR_SOURCE_IMAGE_HIGH_MSB                                        15
+#define GCREG_VR_SOURCE_IMAGE_HIGH_LSB                                         0
+#define GCREG_VR_SOURCE_IMAGE_LOW_HIGH_BLK                                     0
+#define GCREG_VR_SOURCE_IMAGE_HIGH_Count                                       1
+#define GCREG_VR_SOURCE_IMAGE_HIGH_FieldMask                          0xFFFFFFFF
+#define GCREG_VR_SOURCE_IMAGE_HIGH_ReadMask                           0xFFFFFFFF
+#define GCREG_VR_SOURCE_IMAGE_HIGH_WriteMask                          0xFFFFFFFF
+#define GCREG_VR_SOURCE_IMAGE_HIGH_ResetValue                         0x00000000
+
+#define GCREG_VR_SOURCE_IMAGE_HIGH_RIGHT                                  15 : 0
+#define GCREG_VR_SOURCE_IMAGE_HIGH_RIGHT_End                                  15
+#define GCREG_VR_SOURCE_IMAGE_HIGH_RIGHT_Start                                 0
+#define GCREG_VR_SOURCE_IMAGE_HIGH_RIGHT_Type                                U16
+
+#define GCREG_VR_SOURCE_IMAGE_HIGH_BOTTOM                                31 : 16
+#define GCREG_VR_SOURCE_IMAGE_HIGH_BOTTOM_End                                 31
+#define GCREG_VR_SOURCE_IMAGE_HIGH_BOTTOM_Start                               16
+#define GCREG_VR_SOURCE_IMAGE_HIGH_BOTTOM_Type                               U16
+
+/*******************************************************************************
+** State gcregVRSourceOriginLow
+*/
+
+/* Fractional origin of the source window to be rendered within the source
+** image.
+*/
+
+#define gcregVRSourceOriginLowRegAddrs                                    0x04A8
+#define GCREG_VR_SOURCE_ORIGIN_LOW_MSB                                        15
+#define GCREG_VR_SOURCE_ORIGIN_LOW_LSB                                         0
+#define GCREG_VR_SOURCE_ORIGIN_LOW_BLK                                         0
+#define GCREG_VR_SOURCE_ORIGIN_LOW_Count                                       1
+#define GCREG_VR_SOURCE_ORIGIN_LOW_FieldMask                          0xFFFFFFFF
+#define GCREG_VR_SOURCE_ORIGIN_LOW_ReadMask                           0xFFFFFFFF
+#define GCREG_VR_SOURCE_ORIGIN_LOW_WriteMask                          0xFFFFFFFF
+#define GCREG_VR_SOURCE_ORIGIN_LOW_ResetValue                         0x00000000
+
+#define GCREG_VR_SOURCE_ORIGIN_LOW_X                                      31 : 0
+#define GCREG_VR_SOURCE_ORIGIN_LOW_X_End                                      31
+#define GCREG_VR_SOURCE_ORIGIN_LOW_X_Start                                     0
+#define GCREG_VR_SOURCE_ORIGIN_LOW_X_Type                                    U32
+
+/*******************************************************************************
+** State gcregVRSourceOriginHigh
+*/
+
+#define gcregVRSourceOriginHighRegAddrs                                   0x04A9
+#define GCREG_VR_SOURCE_ORIGIN_HIGH_MSB                                       15
+#define GCREG_VR_SOURCE_ORIGIN_HIGH_LSB                                        0
+#define GCREG_VR_SOURCE_ORIGIN_LOW_HIGH_BLK                                    0
+#define GCREG_VR_SOURCE_ORIGIN_HIGH_Count                                      1
+#define GCREG_VR_SOURCE_ORIGIN_HIGH_FieldMask                         0xFFFFFFFF
+#define GCREG_VR_SOURCE_ORIGIN_HIGH_ReadMask                          0xFFFFFFFF
+#define GCREG_VR_SOURCE_ORIGIN_HIGH_WriteMask                         0xFFFFFFFF
+#define GCREG_VR_SOURCE_ORIGIN_HIGH_ResetValue                        0x00000000
+
+#define GCREG_VR_SOURCE_ORIGIN_HIGH_Y                                     31 : 0
+#define GCREG_VR_SOURCE_ORIGIN_HIGH_Y_End                                     31
+#define GCREG_VR_SOURCE_ORIGIN_HIGH_Y_Start                                    0
+#define GCREG_VR_SOURCE_ORIGIN_HIGH_Y_Type                                   U32
+
+/*******************************************************************************
+** State gcregVRTargetWindowLow
+*/
+
+/* Bounding box of the destination window to be rendered within the
+** destination image.
+*/
+
+#define gcregVRTargetWindowLowRegAddrs                                    0x04AA
+#define GCREG_VR_TARGET_WINDOW_LOW_Address                               0x012A8
+#define GCREG_VR_TARGET_WINDOW_LOW_MSB                                        15
+#define GCREG_VR_TARGET_WINDOW_LOW_LSB                                         0
+#define GCREG_VR_TARGET_WINDOW_LOW_BLK                                         0
+#define GCREG_VR_TARGET_WINDOW_LOW_Count                                       1
+#define GCREG_VR_TARGET_WINDOW_LOW_FieldMask                          0xFFFFFFFF
+#define GCREG_VR_TARGET_WINDOW_LOW_ReadMask                           0xFFFFFFFF
+#define GCREG_VR_TARGET_WINDOW_LOW_WriteMask                          0xFFFFFFFF
+#define GCREG_VR_TARGET_WINDOW_LOW_ResetValue                         0x00000000
+
+#define GCREG_VR_TARGET_WINDOW_LOW_LEFT                                   15 : 0
+#define GCREG_VR_TARGET_WINDOW_LOW_LEFT_End                                   15
+#define GCREG_VR_TARGET_WINDOW_LOW_LEFT_Start                                  0
+#define GCREG_VR_TARGET_WINDOW_LOW_LEFT_Type                                 U16
+
+#define GCREG_VR_TARGET_WINDOW_LOW_TOP                                   31 : 16
+#define GCREG_VR_TARGET_WINDOW_LOW_TOP_End                                    31
+#define GCREG_VR_TARGET_WINDOW_LOW_TOP_Start                                  16
+#define GCREG_VR_TARGET_WINDOW_LOW_TOP_Type                                  U16
+
+/*******************************************************************************
+** State gcregVRTargetWindowHigh
+*/
+
+#define gcregVRTargetWindowHighRegAddrs                                   0x04AB
+#define GCREG_VR_TARGET_WINDOW_HIGH_MSB                                       15
+#define GCREG_VR_TARGET_WINDOW_HIGH_LSB                                        0
+#define GCREG_VR_TARGET_WINDOW_LOW_HIGH_BLK                                    0
+#define GCREG_VR_TARGET_WINDOW_HIGH_Count                                      1
+#define GCREG_VR_TARGET_WINDOW_HIGH_FieldMask                         0xFFFFFFFF
+#define GCREG_VR_TARGET_WINDOW_HIGH_ReadMask                          0xFFFFFFFF
+#define GCREG_VR_TARGET_WINDOW_HIGH_WriteMask                         0xFFFFFFFF
+#define GCREG_VR_TARGET_WINDOW_HIGH_ResetValue                        0x00000000
+
+#define GCREG_VR_TARGET_WINDOW_HIGH_RIGHT                                 15 : 0
+#define GCREG_VR_TARGET_WINDOW_HIGH_RIGHT_End                                 15
+#define GCREG_VR_TARGET_WINDOW_HIGH_RIGHT_Start                                0
+#define GCREG_VR_TARGET_WINDOW_HIGH_RIGHT_Type                               U16
+
+#define GCREG_VR_TARGET_WINDOW_HIGH_BOTTOM                               31 : 16
+#define GCREG_VR_TARGET_WINDOW_HIGH_BOTTOM_End                                31
+#define GCREG_VR_TARGET_WINDOW_HIGH_BOTTOM_Start                              16
+#define GCREG_VR_TARGET_WINDOW_HIGH_BOTTOM_Type                              U16
+
+/*******************************************************************************
+** State gcregVRConfig
+*/
+
+/* Video Rasterizer kick-off register. */
+
+#define gcregVRConfigRegAddrs                                             0x04A5
+#define GCREG_VR_CONFIG_MSB                                                   15
+#define GCREG_VR_CONFIG_LSB                                                    0
+#define GCREG_VR_CONFIG_BLK                                                    0
+#define GCREG_VR_CONFIG_Count                                                  1
+#define GCREG_VR_CONFIG_FieldMask                                     0x0000000B
+#define GCREG_VR_CONFIG_ReadMask                                      0x0000000B
+#define GCREG_VR_CONFIG_WriteMask                                     0x0000000B
+#define GCREG_VR_CONFIG_ResetValue                                    0x00000000
+
+/* Kick-off command. */
+#define GCREG_VR_CONFIG_START                                              1 : 0
+#define GCREG_VR_CONFIG_START_End                                              1
+#define GCREG_VR_CONFIG_START_Start                                            0
+#define GCREG_VR_CONFIG_START_Type                                           U02
+#define   GCREG_VR_CONFIG_START_HORIZONTAL_BLIT                              0x0
+#define   GCREG_VR_CONFIG_START_VERTICAL_BLIT                                0x1
+#define   GCREG_VR_CONFIG_START_ONE_PASS_BLIT                                0x2
+
+#define GCREG_VR_CONFIG_MASK_START                                         3 : 3
+#define GCREG_VR_CONFIG_MASK_START_End                                         3
+#define GCREG_VR_CONFIG_MASK_START_Start                                       3
+#define GCREG_VR_CONFIG_MASK_START_Type                                      U01
+#define   GCREG_VR_CONFIG_MASK_START_ENABLED                                 0x0
+#define   GCREG_VR_CONFIG_MASK_START_MASKED                                  0x1
+
+/*******************************************************************************
+** State gcregVRConfigEx
+*/
+
+/* Video Rasterizer configuration register. */
+
+#define gcregVRConfigExRegAddrs                                           0x04B9
+#define GCREG_VR_CONFIG_EX_Address                                       0x012E4
+#define GCREG_VR_CONFIG_EX_MSB                                                15
+#define GCREG_VR_CONFIG_EX_LSB                                                 0
+#define GCREG_VR_CONFIG_EX_BLK                                                 0
+#define GCREG_VR_CONFIG_EX_Count                                               1
+#define GCREG_VR_CONFIG_EX_FieldMask                                  0x000001FB
+#define GCREG_VR_CONFIG_EX_ReadMask                                   0x000001FB
+#define GCREG_VR_CONFIG_EX_WriteMask                                  0x000001FB
+#define GCREG_VR_CONFIG_EX_ResetValue                                 0x00000000
+
+/* Line width in pixels for vertical pass. */
+#define GCREG_VR_CONFIG_EX_VERTICAL_LINE_WIDTH                             1 : 0
+#define GCREG_VR_CONFIG_EX_VERTICAL_LINE_WIDTH_End                             1
+#define GCREG_VR_CONFIG_EX_VERTICAL_LINE_WIDTH_Start                           0
+#define GCREG_VR_CONFIG_EX_VERTICAL_LINE_WIDTH_Type                          U02
+#define   GCREG_VR_CONFIG_EX_VERTICAL_LINE_WIDTH_AUTO                        0x0
+#define   GCREG_VR_CONFIG_EX_VERTICAL_LINE_WIDTH_PIXELS16                    0x1
+#define   GCREG_VR_CONFIG_EX_VERTICAL_LINE_WIDTH_PIXELS32                    0x2
+
+#define GCREG_VR_CONFIG_EX_MASK_VERTICAL_LINE_WIDTH                        3 : 3
+#define GCREG_VR_CONFIG_EX_MASK_VERTICAL_LINE_WIDTH_End                        3
+#define GCREG_VR_CONFIG_EX_MASK_VERTICAL_LINE_WIDTH_Start                      3
+#define GCREG_VR_CONFIG_EX_MASK_VERTICAL_LINE_WIDTH_Type                     U01
+#define   GCREG_VR_CONFIG_EX_MASK_VERTICAL_LINE_WIDTH_ENABLED                0x0
+#define   GCREG_VR_CONFIG_EX_MASK_VERTICAL_LINE_WIDTH_MASKED                 0x1
+
+/* one pass filter tap. */
+#define GCREG_VR_CONFIG_EX_FILTER_TAP                                      7 : 4
+#define GCREG_VR_CONFIG_EX_FILTER_TAP_End                                      7
+#define GCREG_VR_CONFIG_EX_FILTER_TAP_Start                                    4
+#define GCREG_VR_CONFIG_EX_FILTER_TAP_Type                                   U04
+
+#define GCREG_VR_CONFIG_EX_MASK_FILTER_TAP                                 8 : 8
+#define GCREG_VR_CONFIG_EX_MASK_FILTER_TAP_End                                 8
+#define GCREG_VR_CONFIG_EX_MASK_FILTER_TAP_Start                               8
+#define GCREG_VR_CONFIG_EX_MASK_FILTER_TAP_Type                              U01
+#define   GCREG_VR_CONFIG_EX_MASK_FILTER_TAP_ENABLED                         0x0
+#define   GCREG_VR_CONFIG_EX_MASK_FILTER_TAP_MASKED                          0x1
+
+/*******************************************************************************
+** State gcregBWConfig
+*/
+
+#define gcregBWConfigRegAddrs                                             0x04BC
+#define GCREG_BW_CONFIG_MSB                                                   15
+#define GCREG_BW_CONFIG_LSB                                                    0
+#define GCREG_BW_CONFIG_BLK                                                    0
+#define GCREG_BW_CONFIG_Count                                                  1
+#define GCREG_BW_CONFIG_FieldMask                                     0x00009999
+#define GCREG_BW_CONFIG_ReadMask                                      0x00009999
+#define GCREG_BW_CONFIG_WriteMask                                     0x00009999
+#define GCREG_BW_CONFIG_ResetValue                                    0x00000000
+
+/* One Pass Filter Block Config. */
+#define GCREG_BW_CONFIG_BLOCK_CONFIG                                       0 : 0
+#define GCREG_BW_CONFIG_BLOCK_CONFIG_End                                       0
+#define GCREG_BW_CONFIG_BLOCK_CONFIG_Start                                     0
+#define GCREG_BW_CONFIG_BLOCK_CONFIG_Type                                    U01
+#define   GCREG_BW_CONFIG_BLOCK_CONFIG_AUTO                                  0x0
+#define   GCREG_BW_CONFIG_BLOCK_CONFIG_CUSTOMIZE                             0x1
+
+#define GCREG_BW_CONFIG_MASK_BLOCK_CONFIG                                  3 : 3
+#define GCREG_BW_CONFIG_MASK_BLOCK_CONFIG_End                                  3
+#define GCREG_BW_CONFIG_MASK_BLOCK_CONFIG_Start                                3
+#define GCREG_BW_CONFIG_MASK_BLOCK_CONFIG_Type                               U01
+#define   GCREG_BW_CONFIG_MASK_BLOCK_CONFIG_ENABLED                          0x0
+#define   GCREG_BW_CONFIG_MASK_BLOCK_CONFIG_MASKED                           0x1
+
+/* block walk direction in one pass filter blit. */
+#define GCREG_BW_CONFIG_BLOCK_WALK_DIRECTION                               4 : 4
+#define GCREG_BW_CONFIG_BLOCK_WALK_DIRECTION_End                               4
+#define GCREG_BW_CONFIG_BLOCK_WALK_DIRECTION_Start                             4
+#define GCREG_BW_CONFIG_BLOCK_WALK_DIRECTION_Type                            U01
+#define   GCREG_BW_CONFIG_BLOCK_WALK_DIRECTION_RIGHT_BOTTOM                  0x0
+#define   GCREG_BW_CONFIG_BLOCK_WALK_DIRECTION_BOTTOM_RIGHT                  0x1
+
+#define GCREG_BW_CONFIG_MASK_BLOCK_WALK_DIRECTION                          7 : 7
+#define GCREG_BW_CONFIG_MASK_BLOCK_WALK_DIRECTION_End                          7
+#define GCREG_BW_CONFIG_MASK_BLOCK_WALK_DIRECTION_Start                        7
+#define GCREG_BW_CONFIG_MASK_BLOCK_WALK_DIRECTION_Type                       U01
+#define   GCREG_BW_CONFIG_MASK_BLOCK_WALK_DIRECTION_ENABLED                  0x0
+#define   GCREG_BW_CONFIG_MASK_BLOCK_WALK_DIRECTION_MASKED                   0x1
+
+/* block walk direction in one pass filter blit. */
+#define GCREG_BW_CONFIG_TILE_WALK_DIRECTION                                8 : 8
+#define GCREG_BW_CONFIG_TILE_WALK_DIRECTION_End                                8
+#define GCREG_BW_CONFIG_TILE_WALK_DIRECTION_Start                              8
+#define GCREG_BW_CONFIG_TILE_WALK_DIRECTION_Type                             U01
+#define   GCREG_BW_CONFIG_TILE_WALK_DIRECTION_RIGHT_BOTTOM                   0x0
+#define   GCREG_BW_CONFIG_TILE_WALK_DIRECTION_BOTTOM_RIGHT                   0x1
+
+#define GCREG_BW_CONFIG_MASK_TILE_WALK_DIRECTION                         11 : 11
+#define GCREG_BW_CONFIG_MASK_TILE_WALK_DIRECTION_End                          11
+#define GCREG_BW_CONFIG_MASK_TILE_WALK_DIRECTION_Start                        11
+#define GCREG_BW_CONFIG_MASK_TILE_WALK_DIRECTION_Type                        U01
+#define   GCREG_BW_CONFIG_MASK_TILE_WALK_DIRECTION_ENABLED                   0x0
+#define   GCREG_BW_CONFIG_MASK_TILE_WALK_DIRECTION_MASKED                    0x1
+
+/* block walk direction in one pass filter blit. */
+#define GCREG_BW_CONFIG_PIXEL_WALK_DIRECTION                             12 : 12
+#define GCREG_BW_CONFIG_PIXEL_WALK_DIRECTION_End                              12
+#define GCREG_BW_CONFIG_PIXEL_WALK_DIRECTION_Start                            12
+#define GCREG_BW_CONFIG_PIXEL_WALK_DIRECTION_Type                            U01
+#define   GCREG_BW_CONFIG_PIXEL_WALK_DIRECTION_RIGHT_BOTTOM                  0x0
+#define   GCREG_BW_CONFIG_PIXEL_WALK_DIRECTION_BOTTOM_RIGHT                  0x1
+
+#define GCREG_BW_CONFIG_MASK_PIXEL_WALK_DIRECTION                        15 : 15
+#define GCREG_BW_CONFIG_MASK_PIXEL_WALK_DIRECTION_End                         15
+#define GCREG_BW_CONFIG_MASK_PIXEL_WALK_DIRECTION_Start                       15
+#define GCREG_BW_CONFIG_MASK_PIXEL_WALK_DIRECTION_Type                       U01
+#define   GCREG_BW_CONFIG_MASK_PIXEL_WALK_DIRECTION_ENABLED                  0x0
+#define   GCREG_BW_CONFIG_MASK_PIXEL_WALK_DIRECTION_MASKED                   0x1
+
+/*******************************************************************************
+** State gcregBWBlockSize
+*/
+
+/* Walker Block size. */
+
+#define gcregBWBlockSizeRegAddrs                                          0x04BD
+#define GCREG_BW_BLOCK_SIZE_MSB                                               15
+#define GCREG_BW_BLOCK_SIZE_LSB                                                0
+#define GCREG_BW_BLOCK_SIZE_BLK                                                0
+#define GCREG_BW_BLOCK_SIZE_Count                                              1
+#define GCREG_BW_BLOCK_SIZE_FieldMask                                 0xFFFFFFFF
+#define GCREG_BW_BLOCK_SIZE_ReadMask                                  0xFFFFFFFF
+#define GCREG_BW_BLOCK_SIZE_WriteMask                                 0xFFFFFFFF
+#define GCREG_BW_BLOCK_SIZE_ResetValue                                0x00000000
+
+#define GCREG_BW_BLOCK_SIZE_WIDTH                                         15 : 0
+#define GCREG_BW_BLOCK_SIZE_WIDTH_End                                         15
+#define GCREG_BW_BLOCK_SIZE_WIDTH_Start                                        0
+#define GCREG_BW_BLOCK_SIZE_WIDTH_Type                                       U16
+
+#define GCREG_BW_BLOCK_SIZE_HEIGHT                                       31 : 16
+#define GCREG_BW_BLOCK_SIZE_HEIGHT_End                                        31
+#define GCREG_BW_BLOCK_SIZE_HEIGHT_Start                                      16
+#define GCREG_BW_BLOCK_SIZE_HEIGHT_Type                                      U16
+
+/*******************************************************************************
+** State gcregBWTileSize
+*/
+
+/* Walker tile size. */
+
+#define gcregBWTileSizeRegAddrs                                           0x04BE
+#define GCREG_BW_TILE_SIZE_MSB                                                15
+#define GCREG_BW_TILE_SIZE_LSB                                                 0
+#define GCREG_BW_TILE_SIZE_BLK                                                 0
+#define GCREG_BW_TILE_SIZE_Count                                               1
+#define GCREG_BW_TILE_SIZE_FieldMask                                  0xFFFFFFFF
+#define GCREG_BW_TILE_SIZE_ReadMask                                   0xFFFFFFFF
+#define GCREG_BW_TILE_SIZE_WriteMask                                  0xFFFFFFFF
+#define GCREG_BW_TILE_SIZE_ResetValue                                 0x00000000
+
+#define GCREG_BW_TILE_SIZE_WIDTH                                          15 : 0
+#define GCREG_BW_TILE_SIZE_WIDTH_End                                          15
+#define GCREG_BW_TILE_SIZE_WIDTH_Start                                         0
+#define GCREG_BW_TILE_SIZE_WIDTH_Type                                        U16
+
+#define GCREG_BW_TILE_SIZE_HEIGHT                                        31 : 16
+#define GCREG_BW_TILE_SIZE_HEIGHT_End                                         31
+#define GCREG_BW_TILE_SIZE_HEIGHT_Start                                       16
+#define GCREG_BW_TILE_SIZE_HEIGHT_Type                                       U16
+
+/*******************************************************************************
+** State gcregBWBlockMask
+*/
+
+/* Walker Block Mask. */
+
+#define gcregBWBlockMaskRegAddrs                                          0x04BF
+#define GCREG_BW_BLOCK_MASK_MSB                                               15
+#define GCREG_BW_BLOCK_MASK_LSB                                                0
+#define GCREG_BW_BLOCK_MASK_BLK                                                0
+#define GCREG_BW_BLOCK_MASK_Count                                              1
+#define GCREG_BW_BLOCK_MASK_FieldMask                                 0xFFFFFFFF
+#define GCREG_BW_BLOCK_MASK_ReadMask                                  0xFFFFFFFF
+#define GCREG_BW_BLOCK_MASK_WriteMask                                 0xFFFFFFFF
+#define GCREG_BW_BLOCK_MASK_ResetValue                                0x00000000
+
+#define GCREG_BW_BLOCK_MASK_HORIZONTAL                                    15 : 0
+#define GCREG_BW_BLOCK_MASK_HORIZONTAL_End                                    15
+#define GCREG_BW_BLOCK_MASK_HORIZONTAL_Start                                   0
+#define GCREG_BW_BLOCK_MASK_HORIZONTAL_Type                                  U16
+
+#define GCREG_BW_BLOCK_MASK_VERTICAL                                     31 : 16
+#define GCREG_BW_BLOCK_MASK_VERTICAL_End                                      31
+#define GCREG_BW_BLOCK_MASK_VERTICAL_Start                                    16
+#define GCREG_BW_BLOCK_MASK_VERTICAL_Type                                    U16
+
+/*******************************************************************************
+** State gcregIndexColorTable
+*/
+
+/* 256 color entries for the indexed color mode. Colors are assumed to be in
+** the destination format and no color conversion is done on the values.
+*/
+
+#define gcregIndexColorTableRegAddrs                                      0x0700
+#define GCREG_INDEX_COLOR_TABLE_MSB                                           15
+#define GCREG_INDEX_COLOR_TABLE_LSB                                            8
+#define GCREG_INDEX_COLOR_TABLE_BLK                                            8
+#define GCREG_INDEX_COLOR_TABLE_Count                                        256
+#define GCREG_INDEX_COLOR_TABLE_FieldMask                             0xFFFFFFFF
+#define GCREG_INDEX_COLOR_TABLE_ReadMask                              0xFFFFFFFF
+#define GCREG_INDEX_COLOR_TABLE_WriteMask                             0xFFFFFFFF
+#define GCREG_INDEX_COLOR_TABLE_ResetValue                            0x00000000
+
+#define GCREG_INDEX_COLOR_TABLE_ALPHA                                    31 : 24
+#define GCREG_INDEX_COLOR_TABLE_ALPHA_End                                     31
+#define GCREG_INDEX_COLOR_TABLE_ALPHA_Start                                   24
+#define GCREG_INDEX_COLOR_TABLE_ALPHA_Type                                   U08
+
+#define GCREG_INDEX_COLOR_TABLE_RED                                      23 : 16
+#define GCREG_INDEX_COLOR_TABLE_RED_End                                       23
+#define GCREG_INDEX_COLOR_TABLE_RED_Start                                     16
+#define GCREG_INDEX_COLOR_TABLE_RED_Type                                     U08
+
+#define GCREG_INDEX_COLOR_TABLE_GREEN                                     15 : 8
+#define GCREG_INDEX_COLOR_TABLE_GREEN_End                                     15
+#define GCREG_INDEX_COLOR_TABLE_GREEN_Start                                    8
+#define GCREG_INDEX_COLOR_TABLE_GREEN_Type                                   U08
+
+#define GCREG_INDEX_COLOR_TABLE_BLUE                                       7 : 0
+#define GCREG_INDEX_COLOR_TABLE_BLUE_End                                       7
+#define GCREG_INDEX_COLOR_TABLE_BLUE_Start                                     0
+#define GCREG_INDEX_COLOR_TABLE_BLUE_Type                                    U08
+
+/*******************************************************************************
+** State gcregIndexColorTable32
+*/
+
+/* 256 color entries for the indexed color mode. Colors are assumed to be in
+** the A8R8G8B8 format and no color conversion is done on the values. This
+** register is used only with chips with PE20 feature available.
+*/
+
+#define gcregIndexColorTable32RegAddrs                                    0x0D00
+#define GCREG_INDEX_COLOR_TABLE32_MSB                                         15
+#define GCREG_INDEX_COLOR_TABLE32_LSB                                          8
+#define GCREG_INDEX_COLOR_TABLE32_BLK                                          8
+#define GCREG_INDEX_COLOR_TABLE32_Count                                      256
+#define GCREG_INDEX_COLOR_TABLE32_FieldMask                           0xFFFFFFFF
+#define GCREG_INDEX_COLOR_TABLE32_ReadMask                            0xFFFFFFFF
+#define GCREG_INDEX_COLOR_TABLE32_WriteMask                           0xFFFFFFFF
+#define GCREG_INDEX_COLOR_TABLE32_ResetValue                          0x00000000
+
+#define GCREG_INDEX_COLOR_TABLE32_ALPHA                                  31 : 24
+#define GCREG_INDEX_COLOR_TABLE32_ALPHA_End                                   31
+#define GCREG_INDEX_COLOR_TABLE32_ALPHA_Start                                 24
+#define GCREG_INDEX_COLOR_TABLE32_ALPHA_Type                                 U08
+
+#define GCREG_INDEX_COLOR_TABLE32_RED                                    23 : 16
+#define GCREG_INDEX_COLOR_TABLE32_RED_End                                     23
+#define GCREG_INDEX_COLOR_TABLE32_RED_Start                                   16
+#define GCREG_INDEX_COLOR_TABLE32_RED_Type                                   U08
+
+#define GCREG_INDEX_COLOR_TABLE32_GREEN                                   15 : 8
+#define GCREG_INDEX_COLOR_TABLE32_GREEN_End                                   15
+#define GCREG_INDEX_COLOR_TABLE32_GREEN_Start                                  8
+#define GCREG_INDEX_COLOR_TABLE32_GREEN_Type                                 U08
+
+#define GCREG_INDEX_COLOR_TABLE32_BLUE                                     7 : 0
+#define GCREG_INDEX_COLOR_TABLE32_BLUE_End                                     7
+#define GCREG_INDEX_COLOR_TABLE32_BLUE_Start                                   0
+#define GCREG_INDEX_COLOR_TABLE32_BLUE_Type                                  U08
+
+/*******************************************************************************
+** State gcregRop
+*/
+
+/* Raster operation foreground and background codes. Even though ROP is not
+** used in CLEAR, HOR_FILTER_BLT, VER_FILTER_BLT and alpha-eanbled BIT_BLTs,
+** ROP code still has to be programmed, because the engine makes the decision
+** whether source, destination and pattern are involved in the current
+** operation and the correct decision is essential for the engine to complete
+** the operation as expected.
+*/
+
+#define gcregRopRegAddrs                                                  0x0497
+#define GCREG_ROP_MSB                                                         15
+#define GCREG_ROP_LSB                                                          0
+#define GCREG_ROP_BLK                                                          0
+#define GCREG_ROP_Count                                                        1
+#define GCREG_ROP_FieldMask                                           0x0030FFFF
+#define GCREG_ROP_ReadMask                                            0x0030FFFF
+#define GCREG_ROP_WriteMask                                           0x0030FFFF
+#define GCREG_ROP_ResetValue                                          0x00000000
+
+/* ROP type: ROP2, ROP3 or ROP4 */
+#define GCREG_ROP_TYPE                                                   21 : 20
+#define GCREG_ROP_TYPE_End                                                    21
+#define GCREG_ROP_TYPE_Start                                                  20
+#define GCREG_ROP_TYPE_Type                                                  U02
+#define   GCREG_ROP_TYPE_ROP2_PATTERN                                        0x0
+#define   GCREG_ROP_TYPE_ROP2_SOURCE                                         0x1
+#define   GCREG_ROP_TYPE_ROP3                                                0x2
+#define   GCREG_ROP_TYPE_ROP4                                                0x3
+
+/* Background ROP code is used for transparent pixels. */
+#define GCREG_ROP_ROP_BG                                                  15 : 8
+#define GCREG_ROP_ROP_BG_End                                                  15
+#define GCREG_ROP_ROP_BG_Start                                                 8
+#define GCREG_ROP_ROP_BG_Type                                                U08
+
+/* Background ROP code is used for opaque pixels. */
+#define GCREG_ROP_ROP_FG                                                   7 : 0
+#define GCREG_ROP_ROP_FG_End                                                   7
+#define GCREG_ROP_ROP_FG_Start                                                 0
+#define GCREG_ROP_ROP_FG_Type                                                U08
+
+struct gcregrop {
+	unsigned int fg:8;
+	unsigned int bg:8;
+	unsigned int _reserved_16_19:4;
+	unsigned int type:2;
+	unsigned int _reserved_22_31:10;
+};
+
+/*******************************************************************************
+** State gcregClipTopLeft
+*/
+
+/* Top left corner of the clipping rectangle defined in pixels. Clipping is
+** always on and everything beyond the clipping rectangle will be clipped
+** out. Clipping is not used with filter blits.
+*/
+
+#define gcregClipTopLeftRegAddrs                                          0x0498
+#define GCREG_CLIP_TOP_LEFT_MSB                                               15
+#define GCREG_CLIP_TOP_LEFT_LSB                                                0
+#define GCREG_CLIP_TOP_LEFT_BLK                                                0
+#define GCREG_CLIP_TOP_LEFT_Count                                              1
+#define GCREG_CLIP_TOP_LEFT_FieldMask                                 0x7FFF7FFF
+#define GCREG_CLIP_TOP_LEFT_ReadMask                                  0x7FFF7FFF
+#define GCREG_CLIP_TOP_LEFT_WriteMask                                 0x7FFF7FFF
+#define GCREG_CLIP_TOP_LEFT_ResetValue                                0x00000000
+
+#define GCREG_CLIP_TOP_LEFT_Y                                            30 : 16
+#define GCREG_CLIP_TOP_LEFT_Y_End                                             30
+#define GCREG_CLIP_TOP_LEFT_Y_Start                                           16
+#define GCREG_CLIP_TOP_LEFT_Y_Type                                           U15
+
+#define GCREG_CLIP_TOP_LEFT_X                                             14 : 0
+#define GCREG_CLIP_TOP_LEFT_X_End                                             14
+#define GCREG_CLIP_TOP_LEFT_X_Start                                            0
+#define GCREG_CLIP_TOP_LEFT_X_Type                                           U15
+
+struct gcregcliplt {
+	unsigned int left:15;
+	unsigned int _reserved_15:1;
+	unsigned int top:15;
+	unsigned int _reserved_31:1;
+};
+
+/*******************************************************************************
+** State gcregClipBottomRight
+*/
+
+/* Bottom right corner of the clipping rectangle defined in pixels. Clipping
+** is always on and everything beyond the clipping rectangle will be clipped
+** out. Clipping is not used with filter blits.
+*/
+
+#define gcregClipBottomRightRegAddrs                                      0x0499
+#define GCREG_CLIP_BOTTOM_RIGHT_MSB                                           15
+#define GCREG_CLIP_BOTTOM_RIGHT_LSB                                            0
+#define GCREG_CLIP_BOTTOM_RIGHT_BLK                                            0
+#define GCREG_CLIP_BOTTOM_RIGHT_Count                                          1
+#define GCREG_CLIP_BOTTOM_RIGHT_FieldMask                             0x7FFF7FFF
+#define GCREG_CLIP_BOTTOM_RIGHT_ReadMask                              0x7FFF7FFF
+#define GCREG_CLIP_BOTTOM_RIGHT_WriteMask                             0x7FFF7FFF
+#define GCREG_CLIP_BOTTOM_RIGHT_ResetValue                            0x00000000
+
+#define GCREG_CLIP_BOTTOM_RIGHT_Y                                        30 : 16
+#define GCREG_CLIP_BOTTOM_RIGHT_Y_End                                         30
+#define GCREG_CLIP_BOTTOM_RIGHT_Y_Start                                       16
+#define GCREG_CLIP_BOTTOM_RIGHT_Y_Type                                       U15
+
+#define GCREG_CLIP_BOTTOM_RIGHT_X                                         14 : 0
+#define GCREG_CLIP_BOTTOM_RIGHT_X_End                                         14
+#define GCREG_CLIP_BOTTOM_RIGHT_X_Start                                        0
+#define GCREG_CLIP_BOTTOM_RIGHT_X_Type                                       U15
+
+struct gcregcliprb {
+	unsigned int right:15;
+	unsigned int _reserved_15:1;
+	unsigned int bottom:15;
+	unsigned int _reserved_31:1;
+};
+
+/*******************************************************************************
+** State gcregConfig
+*/
+
+#define gcregConfigRegAddrs                                               0x049B
+#define GCREG_CONFIG_MSB                                                      15
+#define GCREG_CONFIG_LSB                                                       0
+#define GCREG_CONFIG_BLK                                                       0
+#define GCREG_CONFIG_Count                                                     1
+#define GCREG_CONFIG_FieldMask                                        0x00370031
+#define GCREG_CONFIG_ReadMask                                         0x00370031
+#define GCREG_CONFIG_WriteMask                                        0x00370031
+#define GCREG_CONFIG_ResetValue                                       0x00000000
+
+#define GCREG_CONFIG_MIRROR_BLT_MODE                                       5 : 4
+#define GCREG_CONFIG_MIRROR_BLT_MODE_End                                       5
+#define GCREG_CONFIG_MIRROR_BLT_MODE_Start                                     4
+#define GCREG_CONFIG_MIRROR_BLT_MODE_Type                                    U02
+#define   GCREG_CONFIG_MIRROR_BLT_MODE_NORMAL                                0x0
+#define   GCREG_CONFIG_MIRROR_BLT_MODE_HMIRROR                               0x1
+#define   GCREG_CONFIG_MIRROR_BLT_MODE_VMIRROR                               0x2
+#define   GCREG_CONFIG_MIRROR_BLT_MODE_FULL_MIRROR                           0x3
+
+#define GCREG_CONFIG_MIRROR_BLT_ENABLE                                     0 : 0
+#define GCREG_CONFIG_MIRROR_BLT_ENABLE_End                                     0
+#define GCREG_CONFIG_MIRROR_BLT_ENABLE_Start                                   0
+#define GCREG_CONFIG_MIRROR_BLT_ENABLE_Type                                  U01
+#define   GCREG_CONFIG_MIRROR_BLT_ENABLE_OFF                                 0x0
+#define   GCREG_CONFIG_MIRROR_BLT_ENABLE_ON                                  0x1
+
+/* Source select for the old walkers. */
+#define GCREG_CONFIG_SOURCE_SELECT                                       18 : 16
+#define GCREG_CONFIG_SOURCE_SELECT_End                                        18
+#define GCREG_CONFIG_SOURCE_SELECT_Start                                      16
+#define GCREG_CONFIG_SOURCE_SELECT_Type                                      U03
+
+/* Destination select for the old walkers. */
+#define GCREG_CONFIG_DESTINATION_SELECT                                  21 : 20
+#define GCREG_CONFIG_DESTINATION_SELECT_End                                   21
+#define GCREG_CONFIG_DESTINATION_SELECT_Start                                 20
+#define GCREG_CONFIG_DESTINATION_SELECT_Type                                 U02
+
+/*******************************************************************************
+** State gcregSrcOriginFraction
+*/
+
+/* Fraction for the source origin. Together with values in gcregSrcOrigin
+** these values form signed 16.16 fixed point origin for the source
+** rectangle. Fractions are only used in filter blit in split frame mode.
+*/
+
+#define gcregSrcOriginFractionRegAddrs                                    0x049E
+#define GCREG_SRC_ORIGIN_FRACTION_MSB                                         15
+#define GCREG_SRC_ORIGIN_FRACTION_LSB                                          0
+#define GCREG_SRC_ORIGIN_FRACTION_BLK                                          0
+#define GCREG_SRC_ORIGIN_FRACTION_Count                                        1
+#define GCREG_SRC_ORIGIN_FRACTION_FieldMask                           0xFFFFFFFF
+#define GCREG_SRC_ORIGIN_FRACTION_ReadMask                            0xFFFFFFFF
+#define GCREG_SRC_ORIGIN_FRACTION_WriteMask                           0xFFFFFFFF
+#define GCREG_SRC_ORIGIN_FRACTION_ResetValue                          0x00000000
+
+#define GCREG_SRC_ORIGIN_FRACTION_Y                                      31 : 16
+#define GCREG_SRC_ORIGIN_FRACTION_Y_End                                       31
+#define GCREG_SRC_ORIGIN_FRACTION_Y_Start                                     16
+#define GCREG_SRC_ORIGIN_FRACTION_Y_Type                                     U16
+
+#define GCREG_SRC_ORIGIN_FRACTION_X                                       15 : 0
+#define GCREG_SRC_ORIGIN_FRACTION_X_End                                       15
+#define GCREG_SRC_ORIGIN_FRACTION_X_Start                                      0
+#define GCREG_SRC_ORIGIN_FRACTION_X_Type                                     U16
+
+/*******************************************************************************
+** State gcregAlphaControl
+*/
+
+#define gcregAlphaControlRegAddrs                                         0x049F
+#define GCREG_ALPHA_CONTROL_MSB                                               15
+#define GCREG_ALPHA_CONTROL_LSB                                                0
+#define GCREG_ALPHA_CONTROL_BLK                                                0
+#define GCREG_ALPHA_CONTROL_Count                                              1
+#define GCREG_ALPHA_CONTROL_FieldMask                                 0xFFFF0001
+#define GCREG_ALPHA_CONTROL_ReadMask                                  0xFFFF0001
+#define GCREG_ALPHA_CONTROL_WriteMask                                 0xFFFF0001
+#define GCREG_ALPHA_CONTROL_ResetValue                                0x00000000
+
+#define GCREG_ALPHA_CONTROL_ENABLE                                         0 : 0
+#define GCREG_ALPHA_CONTROL_ENABLE_End                                         0
+#define GCREG_ALPHA_CONTROL_ENABLE_Start                                       0
+#define GCREG_ALPHA_CONTROL_ENABLE_Type                                      U01
+#define   GCREG_ALPHA_CONTROL_ENABLE_OFF                                     0x0
+#define   GCREG_ALPHA_CONTROL_ENABLE_ON                                      0x1
+
+struct gcregalphacontrol {
+	/* gcregAlphaControlRegAddrs:GCREG_ALPHA_CONTROL_ENABLE */
+	unsigned int enable:1;
+
+	/* gcregAlphaControlRegAddrs:reserved */
+	unsigned int _reserved_1_31:31;
+};
+
+/*******************************************************************************
+** State gcregAlphaModes
+*/
+
+#define gcregAlphaModesRegAddrs                                           0x04A0
+#define GCREG_ALPHA_MODES_MSB                                                 15
+#define GCREG_ALPHA_MODES_LSB                                                  0
+#define GCREG_ALPHA_MODES_BLK                                                  0
+#define GCREG_ALPHA_MODES_Count                                                1
+#define GCREG_ALPHA_MODES_FieldMask                                   0xFF113311
+#define GCREG_ALPHA_MODES_ReadMask                                    0xFF113311
+#define GCREG_ALPHA_MODES_WriteMask                                   0xFF113311
+#define GCREG_ALPHA_MODES_ResetValue                                  0x00000000
+
+#define GCREG_ALPHA_MODES_SRC_ALPHA_MODE                                   0 : 0
+#define GCREG_ALPHA_MODES_SRC_ALPHA_MODE_End                                   0
+#define GCREG_ALPHA_MODES_SRC_ALPHA_MODE_Start                                 0
+#define GCREG_ALPHA_MODES_SRC_ALPHA_MODE_Type                                U01
+#define   GCREG_ALPHA_MODES_SRC_ALPHA_MODE_NORMAL                            0x0
+#define   GCREG_ALPHA_MODES_SRC_ALPHA_MODE_INVERSED                          0x1
+
+#define GCREG_ALPHA_MODES_DST_ALPHA_MODE                                   4 : 4
+#define GCREG_ALPHA_MODES_DST_ALPHA_MODE_End                                   4
+#define GCREG_ALPHA_MODES_DST_ALPHA_MODE_Start                                 4
+#define GCREG_ALPHA_MODES_DST_ALPHA_MODE_Type                                U01
+#define   GCREG_ALPHA_MODES_DST_ALPHA_MODE_NORMAL                            0x0
+#define   GCREG_ALPHA_MODES_DST_ALPHA_MODE_INVERSED                          0x1
+
+#define GCREG_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE                            9 : 8
+#define GCREG_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_End                            9
+#define GCREG_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_Start                          8
+#define GCREG_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_Type                         U02
+#define   GCREG_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_NORMAL                     0x0
+#define   GCREG_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_GLOBAL                     0x1
+#define   GCREG_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_SCALED                     0x2
+
+#define GCREG_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE                          13 : 12
+#define GCREG_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_End                           13
+#define GCREG_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_Start                         12
+#define GCREG_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_Type                         U02
+#define   GCREG_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_NORMAL                     0x0
+#define   GCREG_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_GLOBAL                     0x1
+#define   GCREG_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_SCALED                     0x2
+
+#define GCREG_ALPHA_MODES_SRC_BLENDING_MODE                              26 : 24
+#define GCREG_ALPHA_MODES_SRC_BLENDING_MODE_End                               26
+#define GCREG_ALPHA_MODES_SRC_BLENDING_MODE_Start                             24
+#define GCREG_ALPHA_MODES_SRC_BLENDING_MODE_Type                             U03
+#define   GCREG_ALPHA_MODES_SRC_BLENDING_MODE_ZERO                           0x0
+#define   GCREG_ALPHA_MODES_SRC_BLENDING_MODE_ONE                            0x1
+#define   GCREG_ALPHA_MODES_SRC_BLENDING_MODE_NORMAL                         0x2
+#define   GCREG_ALPHA_MODES_SRC_BLENDING_MODE_INVERSED                       0x3
+#define   GCREG_ALPHA_MODES_SRC_BLENDING_MODE_COLOR                          0x4
+#define   GCREG_ALPHA_MODES_SRC_BLENDING_MODE_COLOR_INVERSED                 0x5
+#define   GCREG_ALPHA_MODES_SRC_BLENDING_MODE_SATURATED_ALPHA                0x6
+#define   GCREG_ALPHA_MODES_SRC_BLENDING_MODE_SATURATED_DEST_ALPHA           0x7
+
+/* Src Blending factor is calculate from Src alpha. */
+#define GCREG_ALPHA_MODES_SRC_ALPHA_FACTOR                               27 : 27
+#define GCREG_ALPHA_MODES_SRC_ALPHA_FACTOR_End                                27
+#define GCREG_ALPHA_MODES_SRC_ALPHA_FACTOR_Start                              27
+#define GCREG_ALPHA_MODES_SRC_ALPHA_FACTOR_Type                              U01
+#define   GCREG_ALPHA_MODES_SRC_ALPHA_FACTOR_DISABLED                        0x0
+#define   GCREG_ALPHA_MODES_SRC_ALPHA_FACTOR_ENABLED                         0x1
+
+#define GCREG_ALPHA_MODES_DST_BLENDING_MODE                              30 : 28
+#define GCREG_ALPHA_MODES_DST_BLENDING_MODE_End                               30
+#define GCREG_ALPHA_MODES_DST_BLENDING_MODE_Start                             28
+#define GCREG_ALPHA_MODES_DST_BLENDING_MODE_Type                             U03
+#define   GCREG_ALPHA_MODES_DST_BLENDING_MODE_ZERO                           0x0
+#define   GCREG_ALPHA_MODES_DST_BLENDING_MODE_ONE                            0x1
+#define   GCREG_ALPHA_MODES_DST_BLENDING_MODE_NORMAL                         0x2
+#define   GCREG_ALPHA_MODES_DST_BLENDING_MODE_INVERSED                       0x3
+#define   GCREG_ALPHA_MODES_DST_BLENDING_MODE_COLOR                          0x4
+#define   GCREG_ALPHA_MODES_DST_BLENDING_MODE_COLOR_INVERSED                 0x5
+#define   GCREG_ALPHA_MODES_DST_BLENDING_MODE_SATURATED_ALPHA                0x6
+#define   GCREG_ALPHA_MODES_DST_BLENDING_MODE_SATURATED_DEST_ALPHA           0x7
+
+/* Dst Blending factor is calculate from Dst alpha. */
+#define GCREG_ALPHA_MODES_DST_ALPHA_FACTOR                               31 : 31
+#define GCREG_ALPHA_MODES_DST_ALPHA_FACTOR_End                                31
+#define GCREG_ALPHA_MODES_DST_ALPHA_FACTOR_Start                              31
+#define GCREG_ALPHA_MODES_DST_ALPHA_FACTOR_Type                              U01
+#define   GCREG_ALPHA_MODES_DST_ALPHA_FACTOR_DISABLED                        0x0
+#define   GCREG_ALPHA_MODES_DST_ALPHA_FACTOR_ENABLED                         0x1
+
+struct gcregalphamodes {
+	/* gcregAlphaModes:GCREG_ALPHA_MODES_SRC_ALPHA_MODE */
+	unsigned int src_inverse:1;
+
+	/* gcregAlphaModes:reserved */
+	unsigned int _reserved_1_3:3;
+
+	/* gcregAlphaModes:GCREG_ALPHA_MODES_DST_ALPHA_MODE */
+	unsigned int dst_inverse:1;
+
+	/* gcregAlphaModes:reserved */
+	unsigned int _reserved_5_7:3;
+
+	/* gcregAlphaModes:GCREG_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE */
+	unsigned int src_global_alpha:2;
+
+	/* gcregAlphaModes:reserved */
+	unsigned int _reserved_10_11:2;
+
+	/* gcregAlphaModes:GCREG_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE */
+	unsigned int dst_global_alpha:2;
+
+	/* gcregAlphaModes:reserved */
+	unsigned int _reserved_14_23:10;
+
+	/* gcregAlphaModes:GCREG_ALPHA_MODES_SRC_BLENDING_MODE */
+	unsigned int src_blend:3;
+
+	/* gcregAlphaModes:GCREG_ALPHA_MODES_SRC_ALPHA_FACTOR */
+	unsigned int src_color_reverse:1;
+
+	/* gcregAlphaModes:GCREG_ALPHA_MODES_DST_BLENDING_MODE */
+	unsigned int dst_blend:3;
+
+	/* gcregAlphaModes:GCREG_ALPHA_MODES_DST_ALPHA_FACTOR */
+	unsigned int dst_color_reverse:1;
+};
+
+/*******************************************************************************
+** State UPlaneAddress
+*/
+
+/* 32-bit aligned base address of the source U plane. */
+
+#define gcregUPlaneAddressRegAddrs                                        0x04A1
+#define GCREG_UPLANE_ADDRESS_MSB                                              15
+#define GCREG_UPLANE_ADDRESS_LSB                                               0
+#define GCREG_UPLANE_ADDRESS_BLK                                               0
+#define GCREG_UPLANE_ADDRESS_Count                                             1
+#define GCREG_UPLANE_ADDRESS_FieldMask                                0xFFFFFFFF
+#define GCREG_UPLANE_ADDRESS_ReadMask                                 0xFFFFFFFC
+#define GCREG_UPLANE_ADDRESS_WriteMask                                0xFFFFFFFC
+#define GCREG_UPLANE_ADDRESS_ResetValue                               0x00000000
+
+#define GCREG_UPLANE_ADDRESS_ADDRESS                                      31 : 0
+#define GCREG_UPLANE_ADDRESS_ADDRESS_End                                      30
+#define GCREG_UPLANE_ADDRESS_ADDRESS_Start                                     0
+#define GCREG_UPLANE_ADDRESS_ADDRESS_Type                                    U31
+
+/*******************************************************************************
+** State UPlaneStride
+*/
+
+/* Stride of the source U plane in bytes. */
+
+#define gcregUPlaneStrideRegAddrs                                         0x04A2
+#define GCREG_UPLANE_STRIDE_MSB                                               15
+#define GCREG_UPLANE_STRIDE_LSB                                                0
+#define GCREG_UPLANE_STRIDE_BLK                                                0
+#define GCREG_UPLANE_STRIDE_Count                                              1
+#define GCREG_UPLANE_STRIDE_FieldMask                                 0x0003FFFF
+#define GCREG_UPLANE_STRIDE_ReadMask                                  0x0003FFFC
+#define GCREG_UPLANE_STRIDE_WriteMask                                 0x0003FFFC
+#define GCREG_UPLANE_STRIDE_ResetValue                                0x00000000
+
+#define GCREG_UPLANE_STRIDE_STRIDE                                        17 : 0
+#define GCREG_UPLANE_STRIDE_STRIDE_End                                        17
+#define GCREG_UPLANE_STRIDE_STRIDE_Start                                       0
+#define GCREG_UPLANE_STRIDE_STRIDE_Type                                      U18
+
+/*******************************************************************************
+** State VPlaneAddress
+*/
+
+/* 32-bit aligned base address of the source V plane. */
+
+#define gcregVPlaneAddressRegAddrs                                        0x04A3
+#define GCREG_VPLANE_ADDRESS_MSB                                              15
+#define GCREG_VPLANE_ADDRESS_LSB                                               0
+#define GCREG_VPLANE_ADDRESS_BLK                                               0
+#define GCREG_VPLANE_ADDRESS_Count                                             1
+#define GCREG_VPLANE_ADDRESS_FieldMask                                0xFFFFFFFF
+#define GCREG_VPLANE_ADDRESS_ReadMask                                 0xFFFFFFFC
+#define GCREG_VPLANE_ADDRESS_WriteMask                                0xFFFFFFFC
+#define GCREG_VPLANE_ADDRESS_ResetValue                               0x00000000
+
+#define GCREG_VPLANE_ADDRESS_ADDRESS                                      31 : 0
+#define GCREG_VPLANE_ADDRESS_ADDRESS_End                                      30
+#define GCREG_VPLANE_ADDRESS_ADDRESS_Start                                     0
+#define GCREG_VPLANE_ADDRESS_ADDRESS_Type                                    U31
+
+/*******************************************************************************
+** State VPlaneStride
+*/
+
+/* Stride of the source V plane in bytes. */
+
+#define gcregVPlaneStrideRegAddrs                                         0x04A4
+#define GCREG_VPLANE_STRIDE_MSB                                               15
+#define GCREG_VPLANE_STRIDE_LSB                                                0
+#define GCREG_VPLANE_STRIDE_BLK                                                0
+#define GCREG_VPLANE_STRIDE_Count                                              1
+#define GCREG_VPLANE_STRIDE_FieldMask                                 0x0003FFFF
+#define GCREG_VPLANE_STRIDE_ReadMask                                  0x0003FFFC
+#define GCREG_VPLANE_STRIDE_WriteMask                                 0x0003FFFC
+#define GCREG_VPLANE_STRIDE_ResetValue                                0x00000000
+
+#define GCREG_VPLANE_STRIDE_STRIDE                                        17 : 0
+#define GCREG_VPLANE_STRIDE_STRIDE_End                                        17
+#define GCREG_VPLANE_STRIDE_STRIDE_Start                                       0
+#define GCREG_VPLANE_STRIDE_STRIDE_Type                                      U18
+
+/*******************************************************************************
+** State gcregPEConfig
+*/
+
+/* PE debug register. */
+
+#define gcregPEConfigRegAddrs                                             0x04AC
+#define GCREG_PE_CONFIG_Address                                          0x012B0
+#define GCREG_PE_CONFIG_MSB                                                   15
+#define GCREG_PE_CONFIG_LSB                                                    0
+#define GCREG_PE_CONFIG_BLK                                                    0
+#define GCREG_PE_CONFIG_Count                                                  1
+#define GCREG_PE_CONFIG_FieldMask                                     0x0000000B
+#define GCREG_PE_CONFIG_ReadMask                                      0x0000000B
+#define GCREG_PE_CONFIG_WriteMask                                     0x0000000B
+#define GCREG_PE_CONFIG_ResetValue                                    0x00000000
+
+#define GCREG_PE_CONFIG_DESTINATION_FETCH                                  1 : 0
+#define GCREG_PE_CONFIG_DESTINATION_FETCH_End                                  1
+#define GCREG_PE_CONFIG_DESTINATION_FETCH_Start                                0
+#define GCREG_PE_CONFIG_DESTINATION_FETCH_Type                               U02
+#define   GCREG_PE_CONFIG_DESTINATION_FETCH_DISABLE                          0x0
+#define   GCREG_PE_CONFIG_DESTINATION_FETCH_DEFAULT                          0x1
+#define   GCREG_PE_CONFIG_DESTINATION_FETCH_ALWAYS                           0x2
+
+#define GCREG_PE_CONFIG_MASK_DESTINATION_FETCH                             3 : 3
+#define GCREG_PE_CONFIG_MASK_DESTINATION_FETCH_End                             3
+#define GCREG_PE_CONFIG_MASK_DESTINATION_FETCH_Start                           3
+#define GCREG_PE_CONFIG_MASK_DESTINATION_FETCH_Type                          U01
+#define   GCREG_PE_CONFIG_MASK_DESTINATION_FETCH_ENABLED                     0x0
+#define   GCREG_PE_CONFIG_MASK_DESTINATION_FETCH_MASKED                      0x1
+
+/*******************************************************************************
+** State gcregDstRotationHeight
+*/
+
+/* 180/270 degree rotation configuration for the destination surface. Height
+** field specifies the height of the surface in pixels.
+*/
+
+#define gcregDstRotationHeightRegAddrs                                    0x04AD
+#define GCREG_DST_ROTATION_HEIGHT_MSB                                         15
+#define GCREG_DST_ROTATION_HEIGHT_LSB                                          0
+#define GCREG_DST_ROTATION_HEIGHT_BLK                                          0
+#define GCREG_DST_ROTATION_HEIGHT_Count                                        1
+#define GCREG_DST_ROTATION_HEIGHT_FieldMask                           0x0000FFFF
+#define GCREG_DST_ROTATION_HEIGHT_ReadMask                            0x0000FFFF
+#define GCREG_DST_ROTATION_HEIGHT_WriteMask                           0x0000FFFF
+#define GCREG_DST_ROTATION_HEIGHT_ResetValue                          0x00000000
+
+#define GCREG_DST_ROTATION_HEIGHT_HEIGHT                                  15 : 0
+#define GCREG_DST_ROTATION_HEIGHT_HEIGHT_End                                  15
+#define GCREG_DST_ROTATION_HEIGHT_HEIGHT_Start                                 0
+#define GCREG_DST_ROTATION_HEIGHT_HEIGHT_Type                                U16
+
+struct gcregdstrotationheight {
+	/* gcregDstRotationHeightRegAddrs:GCREG_DST_ROTATION_HEIGHT_HEIGHT */
+	unsigned int height:16;
+
+	/* gcregDstRotationHeightRegAddrs:reserved */
+	unsigned int _reserved_16_31:16;
+};
+
+/*******************************************************************************
+** State gcregSrcRotationHeight
+*/
+
+/* 180/270 degree rotation configuration for the Source surface. Height field
+** specifies the height of the surface in pixels.
+*/
+
+#define gcregSrcRotationHeightRegAddrs                                    0x04AE
+#define GCREG_SRC_ROTATION_HEIGHT_MSB                                         15
+#define GCREG_SRC_ROTATION_HEIGHT_LSB                                          0
+#define GCREG_SRC_ROTATION_HEIGHT_BLK                                          0
+#define GCREG_SRC_ROTATION_HEIGHT_Count                                        1
+#define GCREG_SRC_ROTATION_HEIGHT_FieldMask                           0x0000FFFF
+#define GCREG_SRC_ROTATION_HEIGHT_ReadMask                            0x0000FFFF
+#define GCREG_SRC_ROTATION_HEIGHT_WriteMask                           0x0000FFFF
+#define GCREG_SRC_ROTATION_HEIGHT_ResetValue                          0x00000000
+
+#define GCREG_SRC_ROTATION_HEIGHT_HEIGHT                                  15 : 0
+#define GCREG_SRC_ROTATION_HEIGHT_HEIGHT_End                                  15
+#define GCREG_SRC_ROTATION_HEIGHT_HEIGHT_Start                                 0
+#define GCREG_SRC_ROTATION_HEIGHT_HEIGHT_Type                                U16
+
+struct gcregsrcrotationheight {
+	/* gcregSrcRotationHeightRegAddrs:GCREG_SRC_ROTATION_HEIGHT_HEIGHT */
+	unsigned int height:16;
+
+	/* gcregSrcRotationHeightRegAddrs:reserved */
+	unsigned int _reserved_16_31:16;
+};
+
+/*******************************************************************************
+** State gcregRotAngle
+*/
+
+/* 0/90/180/270 degree rotation configuration for the Source surface. Height
+** field specifies the height of the surface in pixels.
+*/
+
+#define gcregRotAngleRegAddrs                                             0x04AF
+#define GCREG_ROT_ANGLE_MSB                                                   15
+#define GCREG_ROT_ANGLE_LSB                                                    0
+#define GCREG_ROT_ANGLE_BLK                                                    0
+#define GCREG_ROT_ANGLE_Count                                                  1
+#define GCREG_ROT_ANGLE_FieldMask                                     0x000BB33F
+#define GCREG_ROT_ANGLE_ReadMask                                      0x000BB33F
+#define GCREG_ROT_ANGLE_WriteMask                                     0x000BB33F
+#define GCREG_ROT_ANGLE_ResetValue                                    0x00000000
+
+#define GCREG_ROT_ANGLE_SRC                                                2 : 0
+#define GCREG_ROT_ANGLE_SRC_End                                                2
+#define GCREG_ROT_ANGLE_SRC_Start                                              0
+#define GCREG_ROT_ANGLE_SRC_Type                                             U03
+#define   GCREG_ROT_ANGLE_SRC_ROT0                                           0x0
+#define   GCREG_ROT_ANGLE_SRC_FLIP_X                                         0x1
+#define   GCREG_ROT_ANGLE_SRC_FLIP_Y                                         0x2
+#define   GCREG_ROT_ANGLE_SRC_ROT90                                          0x4
+#define   GCREG_ROT_ANGLE_SRC_ROT180                                         0x5
+#define   GCREG_ROT_ANGLE_SRC_ROT270                                         0x6
+
+#define GCREG_ROT_ANGLE_DST                                                5 : 3
+#define GCREG_ROT_ANGLE_DST_End                                                5
+#define GCREG_ROT_ANGLE_DST_Start                                              3
+#define GCREG_ROT_ANGLE_DST_Type                                             U03
+#define   GCREG_ROT_ANGLE_DST_ROT0                                           0x0
+#define   GCREG_ROT_ANGLE_DST_FLIP_X                                         0x1
+#define   GCREG_ROT_ANGLE_DST_FLIP_Y                                         0x2
+#define   GCREG_ROT_ANGLE_DST_ROT90                                          0x4
+#define   GCREG_ROT_ANGLE_DST_ROT180                                         0x5
+#define   GCREG_ROT_ANGLE_DST_ROT270                                         0x6
+
+#define GCREG_ROT_ANGLE_MASK_SRC                                           8 : 8
+#define GCREG_ROT_ANGLE_MASK_SRC_End                                           8
+#define GCREG_ROT_ANGLE_MASK_SRC_Start                                         8
+#define GCREG_ROT_ANGLE_MASK_SRC_Type                                        U01
+#define   GCREG_ROT_ANGLE_MASK_SRC_ENABLED                                   0x0
+#define   GCREG_ROT_ANGLE_MASK_SRC_MASKED                                    0x1
+
+#define GCREG_ROT_ANGLE_MASK_DST                                           9 : 9
+#define GCREG_ROT_ANGLE_MASK_DST_End                                           9
+#define GCREG_ROT_ANGLE_MASK_DST_Start                                         9
+#define GCREG_ROT_ANGLE_MASK_DST_Type                                        U01
+#define   GCREG_ROT_ANGLE_MASK_DST_ENABLED                                   0x0
+#define   GCREG_ROT_ANGLE_MASK_DST_MASKED                                    0x1
+
+#define GCREG_ROT_ANGLE_SRC_MIRROR                                       13 : 12
+#define GCREG_ROT_ANGLE_SRC_MIRROR_End                                        13
+#define GCREG_ROT_ANGLE_SRC_MIRROR_Start                                      12
+#define GCREG_ROT_ANGLE_SRC_MIRROR_Type                                      U02
+#define   GCREG_ROT_ANGLE_SRC_MIRROR_NONE                                    0x0
+#define   GCREG_ROT_ANGLE_SRC_MIRROR_MIRROR_X                                0x1
+#define   GCREG_ROT_ANGLE_SRC_MIRROR_MIRROR_Y                                0x2
+#define   GCREG_ROT_ANGLE_SRC_MIRROR_MIRROR_XY                               0x3
+
+#define GCREG_ROT_ANGLE_MASK_SRC_MIRROR                                  15 : 15
+#define GCREG_ROT_ANGLE_MASK_SRC_MIRROR_End                                   15
+#define GCREG_ROT_ANGLE_MASK_SRC_MIRROR_Start                                 15
+#define GCREG_ROT_ANGLE_MASK_SRC_MIRROR_Type                                 U01
+#define   GCREG_ROT_ANGLE_MASK_SRC_MIRROR_ENABLED                            0x0
+#define   GCREG_ROT_ANGLE_MASK_SRC_MIRROR_MASKED                             0x1
+
+#define GCREG_ROT_ANGLE_DST_MIRROR                                       17 : 16
+#define GCREG_ROT_ANGLE_DST_MIRROR_End                                        17
+#define GCREG_ROT_ANGLE_DST_MIRROR_Start                                      16
+#define GCREG_ROT_ANGLE_DST_MIRROR_Type                                      U02
+#define   GCREG_ROT_ANGLE_DST_MIRROR_NONE                                    0x0
+#define   GCREG_ROT_ANGLE_DST_MIRROR_MIRROR_X                                0x1
+#define   GCREG_ROT_ANGLE_DST_MIRROR_MIRROR_Y                                0x2
+#define   GCREG_ROT_ANGLE_DST_MIRROR_MIRROR_XY                               0x3
+
+#define GCREG_ROT_ANGLE_MASK_DST_MIRROR                                  19 : 19
+#define GCREG_ROT_ANGLE_MASK_DST_MIRROR_End                                   19
+#define GCREG_ROT_ANGLE_MASK_DST_MIRROR_Start                                 19
+#define GCREG_ROT_ANGLE_MASK_DST_MIRROR_Type                                 U01
+#define   GCREG_ROT_ANGLE_MASK_DST_MIRROR_ENABLED                            0x0
+#define   GCREG_ROT_ANGLE_MASK_DST_MIRROR_MASKED                             0x1
+
+/*******************************************************************************
+** State gcregClearPixelValue32
+*/
+
+/* Clear color value in A8R8G8B8 format. */
+
+#define gcregClearPixelValue32RegAddrs                                    0x04B0
+#define GCREG_CLEAR_PIXEL_VALUE32_MSB                                         15
+#define GCREG_CLEAR_PIXEL_VALUE32_LSB                                          0
+#define GCREG_CLEAR_PIXEL_VALUE32_BLK                                          0
+#define GCREG_CLEAR_PIXEL_VALUE32_Count                                        1
+#define GCREG_CLEAR_PIXEL_VALUE32_FieldMask                           0xFFFFFFFF
+#define GCREG_CLEAR_PIXEL_VALUE32_ReadMask                            0xFFFFFFFF
+#define GCREG_CLEAR_PIXEL_VALUE32_WriteMask                           0xFFFFFFFF
+#define GCREG_CLEAR_PIXEL_VALUE32_ResetValue                          0x00000000
+
+#define GCREG_CLEAR_PIXEL_VALUE32_ALPHA                                  31 : 24
+#define GCREG_CLEAR_PIXEL_VALUE32_ALPHA_End                                   31
+#define GCREG_CLEAR_PIXEL_VALUE32_ALPHA_Start                                 24
+#define GCREG_CLEAR_PIXEL_VALUE32_ALPHA_Type                                 U08
+
+#define GCREG_CLEAR_PIXEL_VALUE32_RED                                    23 : 16
+#define GCREG_CLEAR_PIXEL_VALUE32_RED_End                                     23
+#define GCREG_CLEAR_PIXEL_VALUE32_RED_Start                                   16
+#define GCREG_CLEAR_PIXEL_VALUE32_RED_Type                                   U08
+
+#define GCREG_CLEAR_PIXEL_VALUE32_GREEN                                   15 : 8
+#define GCREG_CLEAR_PIXEL_VALUE32_GREEN_End                                   15
+#define GCREG_CLEAR_PIXEL_VALUE32_GREEN_Start                                  8
+#define GCREG_CLEAR_PIXEL_VALUE32_GREEN_Type                                 U08
+
+#define GCREG_CLEAR_PIXEL_VALUE32_BLUE                                     7 : 0
+#define GCREG_CLEAR_PIXEL_VALUE32_BLUE_End                                     7
+#define GCREG_CLEAR_PIXEL_VALUE32_BLUE_Start                                   0
+#define GCREG_CLEAR_PIXEL_VALUE32_BLUE_Type                                  U08
+
+struct gcregclearcolor {
+	/* gcregClearPixelValue32RegAddrs:GCREG_CLEAR_PIXEL_VALUE32_BLUE */
+	unsigned int b:8;
+
+	/* gcregClearPixelValue32RegAddrs:GCREG_CLEAR_PIXEL_VALUE32_GREEN */
+	unsigned int g:8;
+
+	/* gcregClearPixelValue32RegAddrs:GCREG_CLEAR_PIXEL_VALUE32_RED */
+	unsigned int r:8;
+
+	/* gcregClearPixelValue32RegAddrs:GCREG_CLEAR_PIXEL_VALUE32_ALPHA */
+	unsigned int a:8;
+};
+
+/*******************************************************************************
+** State gcregDestColorKey
+*/
+
+/* Defines the destination transparency color in destination format. */
+
+#define gcregDestColorKeyRegAddrs                                         0x04B1
+#define GCREG_DEST_COLOR_KEY_MSB                                              15
+#define GCREG_DEST_COLOR_KEY_LSB                                               0
+#define GCREG_DEST_COLOR_KEY_BLK                                               0
+#define GCREG_DEST_COLOR_KEY_Count                                             1
+#define GCREG_DEST_COLOR_KEY_FieldMask                                0xFFFFFFFF
+#define GCREG_DEST_COLOR_KEY_ReadMask                                 0xFFFFFFFF
+#define GCREG_DEST_COLOR_KEY_WriteMask                                0xFFFFFFFF
+#define GCREG_DEST_COLOR_KEY_ResetValue                               0x00000000
+
+#define GCREG_DEST_COLOR_KEY_ALPHA                                       31 : 24
+#define GCREG_DEST_COLOR_KEY_ALPHA_End                                        31
+#define GCREG_DEST_COLOR_KEY_ALPHA_Start                                      24
+#define GCREG_DEST_COLOR_KEY_ALPHA_Type                                      U08
+
+#define GCREG_DEST_COLOR_KEY_RED                                         23 : 16
+#define GCREG_DEST_COLOR_KEY_RED_End                                          23
+#define GCREG_DEST_COLOR_KEY_RED_Start                                        16
+#define GCREG_DEST_COLOR_KEY_RED_Type                                        U08
+
+#define GCREG_DEST_COLOR_KEY_GREEN                                        15 : 8
+#define GCREG_DEST_COLOR_KEY_GREEN_End                                        15
+#define GCREG_DEST_COLOR_KEY_GREEN_Start                                       8
+#define GCREG_DEST_COLOR_KEY_GREEN_Type                                      U08
+
+#define GCREG_DEST_COLOR_KEY_BLUE                                          7 : 0
+#define GCREG_DEST_COLOR_KEY_BLUE_End                                          7
+#define GCREG_DEST_COLOR_KEY_BLUE_Start                                        0
+#define GCREG_DEST_COLOR_KEY_BLUE_Type                                       U08
+
+/*******************************************************************************
+** State gcregGlobalSrcColor
+*/
+
+/* Defines the global source color and alpha values. */
+
+#define gcregGlobalSrcColorRegAddrs                                       0x04B2
+#define GCREG_GLOBAL_SRC_COLOR_MSB                                            15
+#define GCREG_GLOBAL_SRC_COLOR_LSB                                             0
+#define GCREG_GLOBAL_SRC_COLOR_BLK                                             0
+#define GCREG_GLOBAL_SRC_COLOR_Count                                           1
+#define GCREG_GLOBAL_SRC_COLOR_FieldMask                              0xFFFFFFFF
+#define GCREG_GLOBAL_SRC_COLOR_ReadMask                               0xFFFFFFFF
+#define GCREG_GLOBAL_SRC_COLOR_WriteMask                              0xFFFFFFFF
+#define GCREG_GLOBAL_SRC_COLOR_ResetValue                             0x00000000
+
+#define GCREG_GLOBAL_SRC_COLOR_ALPHA                                     31 : 24
+#define GCREG_GLOBAL_SRC_COLOR_ALPHA_End                                      31
+#define GCREG_GLOBAL_SRC_COLOR_ALPHA_Start                                    24
+#define GCREG_GLOBAL_SRC_COLOR_ALPHA_Type                                    U08
+
+#define GCREG_GLOBAL_SRC_COLOR_RED                                       23 : 16
+#define GCREG_GLOBAL_SRC_COLOR_RED_End                                        23
+#define GCREG_GLOBAL_SRC_COLOR_RED_Start                                      16
+#define GCREG_GLOBAL_SRC_COLOR_RED_Type                                      U08
+
+#define GCREG_GLOBAL_SRC_COLOR_GREEN                                      15 : 8
+#define GCREG_GLOBAL_SRC_COLOR_GREEN_End                                      15
+#define GCREG_GLOBAL_SRC_COLOR_GREEN_Start                                     8
+#define GCREG_GLOBAL_SRC_COLOR_GREEN_Type                                    U08
+
+#define GCREG_GLOBAL_SRC_COLOR_BLUE                                        7 : 0
+#define GCREG_GLOBAL_SRC_COLOR_BLUE_End                                        7
+#define GCREG_GLOBAL_SRC_COLOR_BLUE_Start                                      0
+#define GCREG_GLOBAL_SRC_COLOR_BLUE_Type                                     U08
+
+struct gcregglobalsrccolor {
+	/* gcregGlobalSrcColorRegAddrs:GCREG_GLOBAL_SRC_COLOR_BLUE */
+	unsigned int b:8;
+
+	/* gcregGlobalSrcColorRegAddrs:GCREG_GLOBAL_SRC_COLOR_GREEN */
+	unsigned int g:8;
+
+	/* gcregGlobalSrcColorRegAddrs:GCREG_GLOBAL_SRC_COLOR_RED */
+	unsigned int r:8;
+
+	/* gcregGlobalSrcColorRegAddrs:GCREG_GLOBAL_SRC_COLOR_ALPHA */
+	unsigned int a:8;
+};
+
+/*******************************************************************************
+** State gcregGlobalDestColor
+*/
+
+/* Defines the global destination color and alpha values. */
+
+#define gcregGlobalDestColorRegAddrs                                      0x04B3
+#define GCREG_GLOBAL_DEST_COLOR_MSB                                           15
+#define GCREG_GLOBAL_DEST_COLOR_LSB                                            0
+#define GCREG_GLOBAL_DEST_COLOR_BLK                                            0
+#define GCREG_GLOBAL_DEST_COLOR_Count                                          1
+#define GCREG_GLOBAL_DEST_COLOR_FieldMask                             0xFFFFFFFF
+#define GCREG_GLOBAL_DEST_COLOR_ReadMask                              0xFFFFFFFF
+#define GCREG_GLOBAL_DEST_COLOR_WriteMask                             0xFFFFFFFF
+#define GCREG_GLOBAL_DEST_COLOR_ResetValue                            0x00000000
+
+#define GCREG_GLOBAL_DEST_COLOR_ALPHA                                    31 : 24
+#define GCREG_GLOBAL_DEST_COLOR_ALPHA_End                                     31
+#define GCREG_GLOBAL_DEST_COLOR_ALPHA_Start                                   24
+#define GCREG_GLOBAL_DEST_COLOR_ALPHA_Type                                   U08
+
+#define GCREG_GLOBAL_DEST_COLOR_RED                                      23 : 16
+#define GCREG_GLOBAL_DEST_COLOR_RED_End                                       23
+#define GCREG_GLOBAL_DEST_COLOR_RED_Start                                     16
+#define GCREG_GLOBAL_DEST_COLOR_RED_Type                                     U08
+
+#define GCREG_GLOBAL_DEST_COLOR_GREEN                                     15 : 8
+#define GCREG_GLOBAL_DEST_COLOR_GREEN_End                                     15
+#define GCREG_GLOBAL_DEST_COLOR_GREEN_Start                                    8
+#define GCREG_GLOBAL_DEST_COLOR_GREEN_Type                                   U08
+
+#define GCREG_GLOBAL_DEST_COLOR_BLUE                                       7 : 0
+#define GCREG_GLOBAL_DEST_COLOR_BLUE_End                                       7
+#define GCREG_GLOBAL_DEST_COLOR_BLUE_Start                                     0
+#define GCREG_GLOBAL_DEST_COLOR_BLUE_Type                                    U08
+
+struct gcregglobaldstcolor {
+	/* gcregGlobalDestColorRegAddrs:GCREG_GLOBAL_DEST_COLOR_BLUE */
+	unsigned int b:8;
+
+	/* gcregGlobalDestColorRegAddrs:GCREG_GLOBAL_DEST_COLOR_GREEN */
+	unsigned int g:8;
+
+	/* gcregGlobalDestColorRegAddrs:GCREG_GLOBAL_DEST_COLOR_RED */
+	unsigned int r:8;
+
+	/* gcregGlobalDestColorRegAddrs:GCREG_GLOBAL_DEST_COLOR_ALPHA */
+	unsigned int a:8;
+};
+
+/*******************************************************************************
+** State gcregColorMultiplyModes
+*/
+
+/* Color modes to multiply Source or Destination pixel color by alpha
+** channel. Alpha can be from global color source or current pixel.
+*/
+
+#define gcregColorMultiplyModesRegAddrs                                   0x04B4
+#define GCREG_COLOR_MULTIPLY_MODES_MSB                                        15
+#define GCREG_COLOR_MULTIPLY_MODES_LSB                                         0
+#define GCREG_COLOR_MULTIPLY_MODES_BLK                                         0
+#define GCREG_COLOR_MULTIPLY_MODES_Count                                       1
+#define GCREG_COLOR_MULTIPLY_MODES_FieldMask                          0x00100311
+#define GCREG_COLOR_MULTIPLY_MODES_ReadMask                           0x00100311
+#define GCREG_COLOR_MULTIPLY_MODES_WriteMask                          0x00100311
+#define GCREG_COLOR_MULTIPLY_MODES_ResetValue                         0x00000000
+
+#define GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY                         0 : 0
+#define GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_End                         0
+#define GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_Start                       0
+#define GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_Type                      U01
+#define   GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_DISABLE                 0x0
+#define   GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_ENABLE                  0x1
+
+#define GCREG_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY                         4 : 4
+#define GCREG_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_End                         4
+#define GCREG_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_Start                       4
+#define GCREG_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_Type                      U01
+#define   GCREG_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_DISABLE                 0x0
+#define   GCREG_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_ENABLE                  0x1
+
+#define GCREG_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY                  9 : 8
+#define GCREG_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_End                  9
+#define GCREG_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_Start                8
+#define GCREG_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_Type               U02
+#define   GCREG_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_DISABLE          0x0
+#define   GCREG_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_ALPHA            0x1
+#define   GCREG_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_COLOR            0x2
+
+#define GCREG_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY                        20 : 20
+#define GCREG_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_End                         20
+#define GCREG_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_Start                       20
+#define GCREG_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_Type                       U01
+#define   GCREG_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_DISABLE                  0x0
+#define   GCREG_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_ENABLE                   0x1
+
+struct gcregcolormultiplymodes {
+	/* gcregColorMultiplyModesRegAddrs:
+		GCREG_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY */
+	unsigned int srcpremul:1;
+
+	/* gcregColorMultiplyModesRegAddrs:
+		reserved */
+	unsigned int _reserved_1_3:3;
+
+	/* gcregColorMultiplyModesRegAddrs:
+		GCREG_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY */
+	unsigned int dstpremul:1;
+
+	/* gcregColorMultiplyModesRegAddrs:
+		reserved */
+	unsigned int _reserved_5_7:3;
+
+	/* gcregColorMultiplyModesRegAddrs:
+		GCREG_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY */
+	unsigned int srcglobalpremul:2;
+
+	/* gcregColorMultiplyModesRegAddrs:
+		reserved */
+	unsigned int _reserved_10_19:10;
+
+	/* gcregColorMultiplyModesRegAddrs:
+		GCREG_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY */
+	unsigned int dstdemul:1;
+
+	/* gcregColorMultiplyModesRegAddrs:
+		reserved */
+	unsigned int _reserved_21_31:11;
+};
+
+/*******************************************************************************
+** State gcregPETransparency
+*/
+
+#define gcregPETransparencyRegAddrs                                       0x04B5
+#define GCREG_PE_TRANSPARENCY_MSB                                             15
+#define GCREG_PE_TRANSPARENCY_LSB                                              0
+#define GCREG_PE_TRANSPARENCY_BLK                                              0
+#define GCREG_PE_TRANSPARENCY_Count                                            1
+#define GCREG_PE_TRANSPARENCY_FieldMask                               0xB3331333
+#define GCREG_PE_TRANSPARENCY_ReadMask                                0xB3331333
+#define GCREG_PE_TRANSPARENCY_WriteMask                               0xB3331333
+#define GCREG_PE_TRANSPARENCY_ResetValue                              0x00000000
+
+/* Source transparency mode. */
+#define GCREG_PE_TRANSPARENCY_SOURCE                                       1 : 0
+#define GCREG_PE_TRANSPARENCY_SOURCE_End                                       1
+#define GCREG_PE_TRANSPARENCY_SOURCE_Start                                     0
+#define GCREG_PE_TRANSPARENCY_SOURCE_Type                                    U02
+#define   GCREG_PE_TRANSPARENCY_SOURCE_OPAQUE                                0x0
+#define   GCREG_PE_TRANSPARENCY_SOURCE_MASK                                  0x1
+#define   GCREG_PE_TRANSPARENCY_SOURCE_KEY                                   0x2
+
+/* Pattern transparency mode. KEY transparency mode is reserved. */
+#define GCREG_PE_TRANSPARENCY_PATTERN                                      5 : 4
+#define GCREG_PE_TRANSPARENCY_PATTERN_End                                      5
+#define GCREG_PE_TRANSPARENCY_PATTERN_Start                                    4
+#define GCREG_PE_TRANSPARENCY_PATTERN_Type                                   U02
+#define   GCREG_PE_TRANSPARENCY_PATTERN_OPAQUE                               0x0
+#define   GCREG_PE_TRANSPARENCY_PATTERN_MASK                                 0x1
+#define   GCREG_PE_TRANSPARENCY_PATTERN_KEY                                  0x2
+
+/* Destination transparency mode. MASK transparency mode is reserved. */
+#define GCREG_PE_TRANSPARENCY_DESTINATION                                  9 : 8
+#define GCREG_PE_TRANSPARENCY_DESTINATION_End                                  9
+#define GCREG_PE_TRANSPARENCY_DESTINATION_Start                                8
+#define GCREG_PE_TRANSPARENCY_DESTINATION_Type                               U02
+#define   GCREG_PE_TRANSPARENCY_DESTINATION_OPAQUE                           0x0
+#define   GCREG_PE_TRANSPARENCY_DESTINATION_MASK                             0x1
+#define   GCREG_PE_TRANSPARENCY_DESTINATION_KEY                              0x2
+
+/* Mask field for Source/Pattern/Destination fields. */
+#define GCREG_PE_TRANSPARENCY_MASK_TRANSPARENCY                          12 : 12
+#define GCREG_PE_TRANSPARENCY_MASK_TRANSPARENCY_End                           12
+#define GCREG_PE_TRANSPARENCY_MASK_TRANSPARENCY_Start                         12
+#define GCREG_PE_TRANSPARENCY_MASK_TRANSPARENCY_Type                         U01
+#define   GCREG_PE_TRANSPARENCY_MASK_TRANSPARENCY_ENABLED                    0x0
+#define   GCREG_PE_TRANSPARENCY_MASK_TRANSPARENCY_MASKED                     0x1
+
+/* Source usage override. */
+#define GCREG_PE_TRANSPARENCY_USE_SRC_OVERRIDE                           17 : 16
+#define GCREG_PE_TRANSPARENCY_USE_SRC_OVERRIDE_End                            17
+#define GCREG_PE_TRANSPARENCY_USE_SRC_OVERRIDE_Start                          16
+#define GCREG_PE_TRANSPARENCY_USE_SRC_OVERRIDE_Type                          U02
+#define   GCREG_PE_TRANSPARENCY_USE_SRC_OVERRIDE_DEFAULT                     0x0
+#define   GCREG_PE_TRANSPARENCY_USE_SRC_OVERRIDE_USE_ENABLE                  0x1
+#define   GCREG_PE_TRANSPARENCY_USE_SRC_OVERRIDE_USE_DISABLE                 0x2
+
+/* Pattern usage override. */
+#define GCREG_PE_TRANSPARENCY_USE_PAT_OVERRIDE                           21 : 20
+#define GCREG_PE_TRANSPARENCY_USE_PAT_OVERRIDE_End                            21
+#define GCREG_PE_TRANSPARENCY_USE_PAT_OVERRIDE_Start                          20
+#define GCREG_PE_TRANSPARENCY_USE_PAT_OVERRIDE_Type                          U02
+#define   GCREG_PE_TRANSPARENCY_USE_PAT_OVERRIDE_DEFAULT                     0x0
+#define   GCREG_PE_TRANSPARENCY_USE_PAT_OVERRIDE_USE_ENABLE                  0x1
+#define   GCREG_PE_TRANSPARENCY_USE_PAT_OVERRIDE_USE_DISABLE                 0x2
+
+/* Destination usage override. */
+#define GCREG_PE_TRANSPARENCY_USE_DST_OVERRIDE                           25 : 24
+#define GCREG_PE_TRANSPARENCY_USE_DST_OVERRIDE_End                            25
+#define GCREG_PE_TRANSPARENCY_USE_DST_OVERRIDE_Start                          24
+#define GCREG_PE_TRANSPARENCY_USE_DST_OVERRIDE_Type                          U02
+#define   GCREG_PE_TRANSPARENCY_USE_DST_OVERRIDE_DEFAULT                     0x0
+#define   GCREG_PE_TRANSPARENCY_USE_DST_OVERRIDE_USE_ENABLE                  0x1
+#define   GCREG_PE_TRANSPARENCY_USE_DST_OVERRIDE_USE_DISABLE                 0x2
+
+/* 2D resource usage override mask field. */
+#define GCREG_PE_TRANSPARENCY_MASK_RESOURCE_OVERRIDE                     28 : 28
+#define GCREG_PE_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_End                      28
+#define GCREG_PE_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_Start                    28
+#define GCREG_PE_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_Type                    U01
+#define   GCREG_PE_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_ENABLED               0x0
+#define   GCREG_PE_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_MASKED                0x1
+
+/* DEB Color Key. */
+#define GCREG_PE_TRANSPARENCY_DFB_COLOR_KEY                              29 : 29
+#define GCREG_PE_TRANSPARENCY_DFB_COLOR_KEY_End                               29
+#define GCREG_PE_TRANSPARENCY_DFB_COLOR_KEY_Start                             29
+#define GCREG_PE_TRANSPARENCY_DFB_COLOR_KEY_Type                             U01
+#define   GCREG_PE_TRANSPARENCY_DFB_COLOR_KEY_DISABLED                       0x0
+#define   GCREG_PE_TRANSPARENCY_DFB_COLOR_KEY_ENABLED                        0x1
+
+#define GCREG_PE_TRANSPARENCY_MASK_DFB_COLOR_KEY                         31 : 31
+#define GCREG_PE_TRANSPARENCY_MASK_DFB_COLOR_KEY_End                          31
+#define GCREG_PE_TRANSPARENCY_MASK_DFB_COLOR_KEY_Start                        31
+#define GCREG_PE_TRANSPARENCY_MASK_DFB_COLOR_KEY_Type                        U01
+#define   GCREG_PE_TRANSPARENCY_MASK_DFB_COLOR_KEY_ENABLED                   0x0
+#define   GCREG_PE_TRANSPARENCY_MASK_DFB_COLOR_KEY_MASKED                    0x1
+
+/*******************************************************************************
+** State gcregPEControl
+*/
+
+/* General purpose control register. */
+
+#define gcregPEControlRegAddrs                                            0x04B6
+#define GCREG_PE_CONTROL_MSB                                                  15
+#define GCREG_PE_CONTROL_LSB                                                   0
+#define GCREG_PE_CONTROL_BLK                                                   0
+#define GCREG_PE_CONTROL_Count                                                 1
+#define GCREG_PE_CONTROL_FieldMask                                    0x00000999
+#define GCREG_PE_CONTROL_ReadMask                                     0x00000999
+#define GCREG_PE_CONTROL_WriteMask                                    0x00000999
+#define GCREG_PE_CONTROL_ResetValue                                   0x00000000
+
+#define GCREG_PE_CONTROL_YUV                                               0 : 0
+#define GCREG_PE_CONTROL_YUV_End                                               0
+#define GCREG_PE_CONTROL_YUV_Start                                             0
+#define GCREG_PE_CONTROL_YUV_Type                                            U01
+#define   GCREG_PE_CONTROL_YUV_601                                           0x0
+#define   GCREG_PE_CONTROL_YUV_709                                           0x1
+
+#define GCREG_PE_CONTROL_MASK_YUV                                          3 : 3
+#define GCREG_PE_CONTROL_MASK_YUV_End                                          3
+#define GCREG_PE_CONTROL_MASK_YUV_Start                                        3
+#define GCREG_PE_CONTROL_MASK_YUV_Type                                       U01
+#define   GCREG_PE_CONTROL_MASK_YUV_ENABLED                                  0x0
+#define   GCREG_PE_CONTROL_MASK_YUV_MASKED                                   0x1
+
+#define GCREG_PE_CONTROL_UV_SWIZZLE                                        4 : 4
+#define GCREG_PE_CONTROL_UV_SWIZZLE_End                                        4
+#define GCREG_PE_CONTROL_UV_SWIZZLE_Start                                      4
+#define GCREG_PE_CONTROL_UV_SWIZZLE_Type                                     U01
+#define   GCREG_PE_CONTROL_UV_SWIZZLE_UV                                     0x0
+#define   GCREG_PE_CONTROL_UV_SWIZZLE_VU                                     0x1
+
+#define GCREG_PE_CONTROL_MASK_UV_SWIZZLE                                   7 : 7
+#define GCREG_PE_CONTROL_MASK_UV_SWIZZLE_End                                   7
+#define GCREG_PE_CONTROL_MASK_UV_SWIZZLE_Start                                 7
+#define GCREG_PE_CONTROL_MASK_UV_SWIZZLE_Type                                U01
+#define   GCREG_PE_CONTROL_MASK_UV_SWIZZLE_ENABLED                           0x0
+#define   GCREG_PE_CONTROL_MASK_UV_SWIZZLE_MASKED                            0x1
+
+/* YUV to RGB convert enable */
+#define GCREG_PE_CONTROL_YUVRGB                                            8 : 8
+#define GCREG_PE_CONTROL_YUVRGB_End                                            8
+#define GCREG_PE_CONTROL_YUVRGB_Start                                          8
+#define GCREG_PE_CONTROL_YUVRGB_Type                                         U01
+#define   GCREG_PE_CONTROL_YUVRGB_DISABLED                                   0x0
+#define   GCREG_PE_CONTROL_YUVRGB_ENABLED                                    0x1
+
+#define GCREG_PE_CONTROL_MASK_YUVRGB                                     11 : 11
+#define GCREG_PE_CONTROL_MASK_YUVRGB_End                                      11
+#define GCREG_PE_CONTROL_MASK_YUVRGB_Start                                    11
+#define GCREG_PE_CONTROL_MASK_YUVRGB_Type                                    U01
+#define   GCREG_PE_CONTROL_MASK_YUVRGB_ENABLED                               0x0
+#define   GCREG_PE_CONTROL_MASK_YUVRGB_MASKED                                0x1
+
+/*******************************************************************************
+** State gcregSrcColorKeyHigh
+*/
+
+/* Defines the source transparency color in source format. */
+
+#define gcregSrcColorKeyHighRegAddrs                                      0x04B7
+#define GCREG_SRC_COLOR_KEY_HIGH_Address                                 0x012DC
+#define GCREG_SRC_COLOR_KEY_HIGH_MSB                                          15
+#define GCREG_SRC_COLOR_KEY_HIGH_LSB                                           0
+#define GCREG_SRC_COLOR_KEY_HIGH_BLK                                           0
+#define GCREG_SRC_COLOR_KEY_HIGH_Count                                         1
+#define GCREG_SRC_COLOR_KEY_HIGH_FieldMask                            0xFFFFFFFF
+#define GCREG_SRC_COLOR_KEY_HIGH_ReadMask                             0xFFFFFFFF
+#define GCREG_SRC_COLOR_KEY_HIGH_WriteMask                            0xFFFFFFFF
+#define GCREG_SRC_COLOR_KEY_HIGH_ResetValue                           0x00000000
+
+#define GCREG_SRC_COLOR_KEY_HIGH_ALPHA                                   31 : 24
+#define GCREG_SRC_COLOR_KEY_HIGH_ALPHA_End                                    31
+#define GCREG_SRC_COLOR_KEY_HIGH_ALPHA_Start                                  24
+#define GCREG_SRC_COLOR_KEY_HIGH_ALPHA_Type                                  U08
+
+#define GCREG_SRC_COLOR_KEY_HIGH_RED                                     23 : 16
+#define GCREG_SRC_COLOR_KEY_HIGH_RED_End                                      23
+#define GCREG_SRC_COLOR_KEY_HIGH_RED_Start                                    16
+#define GCREG_SRC_COLOR_KEY_HIGH_RED_Type                                    U08
+
+#define GCREG_SRC_COLOR_KEY_HIGH_GREEN                                    15 : 8
+#define GCREG_SRC_COLOR_KEY_HIGH_GREEN_End                                    15
+#define GCREG_SRC_COLOR_KEY_HIGH_GREEN_Start                                   8
+#define GCREG_SRC_COLOR_KEY_HIGH_GREEN_Type                                  U08
+
+#define GCREG_SRC_COLOR_KEY_HIGH_BLUE                                      7 : 0
+#define GCREG_SRC_COLOR_KEY_HIGH_BLUE_End                                      7
+#define GCREG_SRC_COLOR_KEY_HIGH_BLUE_Start                                    0
+#define GCREG_SRC_COLOR_KEY_HIGH_BLUE_Type                                   U08
+
+/*******************************************************************************
+** State gcregDestColorKeyHigh
+*/
+
+/* Defines the destination transparency color in destination format. */
+
+#define gcregDestColorKeyHighRegAddrs                                     0x04B8
+#define GCREG_DEST_COLOR_KEY_HIGH_MSB                                         15
+#define GCREG_DEST_COLOR_KEY_HIGH_LSB                                          0
+#define GCREG_DEST_COLOR_KEY_HIGH_BLK                                          0
+#define GCREG_DEST_COLOR_KEY_HIGH_Count                                        1
+#define GCREG_DEST_COLOR_KEY_HIGH_FieldMask                           0xFFFFFFFF
+#define GCREG_DEST_COLOR_KEY_HIGH_ReadMask                            0xFFFFFFFF
+#define GCREG_DEST_COLOR_KEY_HIGH_WriteMask                           0xFFFFFFFF
+#define GCREG_DEST_COLOR_KEY_HIGH_ResetValue                          0x00000000
+
+#define GCREG_DEST_COLOR_KEY_HIGH_ALPHA                                  31 : 24
+#define GCREG_DEST_COLOR_KEY_HIGH_ALPHA_End                                   31
+#define GCREG_DEST_COLOR_KEY_HIGH_ALPHA_Start                                 24
+#define GCREG_DEST_COLOR_KEY_HIGH_ALPHA_Type                                 U08
+
+#define GCREG_DEST_COLOR_KEY_HIGH_RED                                    23 : 16
+#define GCREG_DEST_COLOR_KEY_HIGH_RED_End                                     23
+#define GCREG_DEST_COLOR_KEY_HIGH_RED_Start                                   16
+#define GCREG_DEST_COLOR_KEY_HIGH_RED_Type                                   U08
+
+#define GCREG_DEST_COLOR_KEY_HIGH_GREEN                                   15 : 8
+#define GCREG_DEST_COLOR_KEY_HIGH_GREEN_End                                   15
+#define GCREG_DEST_COLOR_KEY_HIGH_GREEN_Start                                  8
+#define GCREG_DEST_COLOR_KEY_HIGH_GREEN_Type                                 U08
+
+#define GCREG_DEST_COLOR_KEY_HIGH_BLUE                                     7 : 0
+#define GCREG_DEST_COLOR_KEY_HIGH_BLUE_End                                     7
+#define GCREG_DEST_COLOR_KEY_HIGH_BLUE_Start                                   0
+#define GCREG_DEST_COLOR_KEY_HIGH_BLUE_Type                                  U08
+
+/*******************************************************************************
+** State gcregPEDitherLow
+*/
+
+/* PE dither register.
+** If you don't want dither, set all fields to their reset values.
+*/
+
+#define gcregPEDitherLowRegAddrs                                          0x04BA
+#define GCREG_PE_DITHER_LOW_MSB                                               15
+#define GCREG_PE_DITHER_LOW_LSB                                                0
+#define GCREG_PE_DITHER_LOW_BLK                                                0
+#define GCREG_PE_DITHER_LOW_Count                                              1
+#define GCREG_PE_DITHER_LOW_FieldMask                                 0xFFFFFFFF
+#define GCREG_PE_DITHER_LOW_ReadMask                                  0xFFFFFFFF
+#define GCREG_PE_DITHER_LOW_WriteMask                                 0xFFFFFFFF
+#define GCREG_PE_DITHER_LOW_ResetValue                                0xFFFFFFFF
+
+/* X,Y = 0,0 */
+#define GCREG_PE_DITHER_LOW_PIXEL_X0_Y0                                    3 : 0
+#define GCREG_PE_DITHER_LOW_PIXEL_X0_Y0_End                                    3
+#define GCREG_PE_DITHER_LOW_PIXEL_X0_Y0_Start                                  0
+#define GCREG_PE_DITHER_LOW_PIXEL_X0_Y0_Type                                 U04
+
+/* X,Y = 1,0 */
+#define GCREG_PE_DITHER_LOW_PIXEL_X1_Y0                                    7 : 4
+#define GCREG_PE_DITHER_LOW_PIXEL_X1_Y0_End                                    7
+#define GCREG_PE_DITHER_LOW_PIXEL_X1_Y0_Start                                  4
+#define GCREG_PE_DITHER_LOW_PIXEL_X1_Y0_Type                                 U04
+
+/* X,Y = 2,0 */
+#define GCREG_PE_DITHER_LOW_PIXEL_X2_Y0                                   11 : 8
+#define GCREG_PE_DITHER_LOW_PIXEL_X2_Y0_End                                   11
+#define GCREG_PE_DITHER_LOW_PIXEL_X2_Y0_Start                                  8
+#define GCREG_PE_DITHER_LOW_PIXEL_X2_Y0_Type                                 U04
+
+/* X,Y = 3,0 */
+#define GCREG_PE_DITHER_LOW_PIXEL_X3_Y0                                  15 : 12
+#define GCREG_PE_DITHER_LOW_PIXEL_X3_Y0_End                                   15
+#define GCREG_PE_DITHER_LOW_PIXEL_X3_Y0_Start                                 12
+#define GCREG_PE_DITHER_LOW_PIXEL_X3_Y0_Type                                 U04
+
+/* X,Y = 0,1 */
+#define GCREG_PE_DITHER_LOW_PIXEL_X0_Y1                                  19 : 16
+#define GCREG_PE_DITHER_LOW_PIXEL_X0_Y1_End                                   19
+#define GCREG_PE_DITHER_LOW_PIXEL_X0_Y1_Start                                 16
+#define GCREG_PE_DITHER_LOW_PIXEL_X0_Y1_Type                                 U04
+
+/* X,Y = 1,1 */
+#define GCREG_PE_DITHER_LOW_PIXEL_X1_Y1                                  23 : 20
+#define GCREG_PE_DITHER_LOW_PIXEL_X1_Y1_End                                   23
+#define GCREG_PE_DITHER_LOW_PIXEL_X1_Y1_Start                                 20
+#define GCREG_PE_DITHER_LOW_PIXEL_X1_Y1_Type                                 U04
+
+/* X,Y = 2,1 */
+#define GCREG_PE_DITHER_LOW_PIXEL_X2_Y1                                  27 : 24
+#define GCREG_PE_DITHER_LOW_PIXEL_X2_Y1_End                                   27
+#define GCREG_PE_DITHER_LOW_PIXEL_X2_Y1_Start                                 24
+#define GCREG_PE_DITHER_LOW_PIXEL_X2_Y1_Type                                 U04
+
+/* X,Y = 3,1 */
+#define GCREG_PE_DITHER_LOW_PIXEL_X3_Y1                                  31 : 28
+#define GCREG_PE_DITHER_LOW_PIXEL_X3_Y1_End                                   31
+#define GCREG_PE_DITHER_LOW_PIXEL_X3_Y1_Start                                 28
+#define GCREG_PE_DITHER_LOW_PIXEL_X3_Y1_Type                                 U04
+
+/*******************************************************************************
+** State gcregPEDitherHigh
+*/
+
+#define gcregPEDitherHighRegAddrs                                         0x04BB
+#define GCREG_PE_DITHER_HIGH_MSB                                              15
+#define GCREG_PE_DITHER_HIGH_LSB                                               0
+#define GCREG_PE_DITHER_LOW_HIGH_BLK                                           0
+#define GCREG_PE_DITHER_HIGH_Count                                             1
+#define GCREG_PE_DITHER_HIGH_FieldMask                                0xFFFFFFFF
+#define GCREG_PE_DITHER_HIGH_ReadMask                                 0xFFFFFFFF
+#define GCREG_PE_DITHER_HIGH_WriteMask                                0xFFFFFFFF
+#define GCREG_PE_DITHER_HIGH_ResetValue                               0xFFFFFFFF
+
+/* X,Y = 0,2 */
+#define GCREG_PE_DITHER_HIGH_PIXEL_X0_Y2                                   3 : 0
+#define GCREG_PE_DITHER_HIGH_PIXEL_X0_Y2_End                                   3
+#define GCREG_PE_DITHER_HIGH_PIXEL_X0_Y2_Start                                 0
+#define GCREG_PE_DITHER_HIGH_PIXEL_X0_Y2_Type                                U04
+
+/* X,Y = 1,2 */
+#define GCREG_PE_DITHER_HIGH_PIXEL_X1_Y2                                   7 : 4
+#define GCREG_PE_DITHER_HIGH_PIXEL_X1_Y2_End                                   7
+#define GCREG_PE_DITHER_HIGH_PIXEL_X1_Y2_Start                                 4
+#define GCREG_PE_DITHER_HIGH_PIXEL_X1_Y2_Type                                U04
+
+/* X,Y = 2,2 */
+#define GCREG_PE_DITHER_HIGH_PIXEL_X2_Y2                                  11 : 8
+#define GCREG_PE_DITHER_HIGH_PIXEL_X2_Y2_End                                  11
+#define GCREG_PE_DITHER_HIGH_PIXEL_X2_Y2_Start                                 8
+#define GCREG_PE_DITHER_HIGH_PIXEL_X2_Y2_Type                                U04
+
+/* X,Y = 0,3 */
+#define GCREG_PE_DITHER_HIGH_PIXEL_X3_Y2                                 15 : 12
+#define GCREG_PE_DITHER_HIGH_PIXEL_X3_Y2_End                                  15
+#define GCREG_PE_DITHER_HIGH_PIXEL_X3_Y2_Start                                12
+#define GCREG_PE_DITHER_HIGH_PIXEL_X3_Y2_Type                                U04
+
+/* X,Y = 1,3 */
+#define GCREG_PE_DITHER_HIGH_PIXEL_X0_Y3                                 19 : 16
+#define GCREG_PE_DITHER_HIGH_PIXEL_X0_Y3_End                                  19
+#define GCREG_PE_DITHER_HIGH_PIXEL_X0_Y3_Start                                16
+#define GCREG_PE_DITHER_HIGH_PIXEL_X0_Y3_Type                                U04
+
+/* X,Y = 2,3 */
+#define GCREG_PE_DITHER_HIGH_PIXEL_X1_Y3                                 23 : 20
+#define GCREG_PE_DITHER_HIGH_PIXEL_X1_Y3_End                                  23
+#define GCREG_PE_DITHER_HIGH_PIXEL_X1_Y3_Start                                20
+#define GCREG_PE_DITHER_HIGH_PIXEL_X1_Y3_Type                                U04
+
+/* X,Y = 3,3 */
+#define GCREG_PE_DITHER_HIGH_PIXEL_X2_Y3                                 27 : 24
+#define GCREG_PE_DITHER_HIGH_PIXEL_X2_Y3_End                                  27
+#define GCREG_PE_DITHER_HIGH_PIXEL_X2_Y3_Start                                24
+#define GCREG_PE_DITHER_HIGH_PIXEL_X2_Y3_Type                                U04
+
+/* X,Y = 3,2 */
+#define GCREG_PE_DITHER_HIGH_PIXEL_X3_Y3                                 31 : 28
+#define GCREG_PE_DITHER_HIGH_PIXEL_X3_Y3_End                                  31
+#define GCREG_PE_DITHER_HIGH_PIXEL_X3_Y3_Start                                28
+#define GCREG_PE_DITHER_HIGH_PIXEL_X3_Y3_Type                                U04
+
+/*******************************************************************************
+** State gcregSrcExConfig
+*/
+
+#define gcregSrcExConfigRegAddrs                                          0x04C0
+#define GCREG_SRC_EX_CONFIG_MSB                                               15
+#define GCREG_SRC_EX_CONFIG_LSB                                                0
+#define GCREG_SRC_EX_CONFIG_BLK                                                0
+#define GCREG_SRC_EX_CONFIG_Count                                              1
+#define GCREG_SRC_EX_CONFIG_FieldMask                                 0x00000109
+#define GCREG_SRC_EX_CONFIG_ReadMask                                  0x00000109
+#define GCREG_SRC_EX_CONFIG_WriteMask                                 0x00000109
+#define GCREG_SRC_EX_CONFIG_ResetValue                                0x00000000
+
+/* Source multi tiled address computation control. */
+#define GCREG_SRC_EX_CONFIG_MULTI_TILED                                    0 : 0
+#define GCREG_SRC_EX_CONFIG_MULTI_TILED_End                                    0
+#define GCREG_SRC_EX_CONFIG_MULTI_TILED_Start                                  0
+#define GCREG_SRC_EX_CONFIG_MULTI_TILED_Type                                 U01
+#define   GCREG_SRC_EX_CONFIG_MULTI_TILED_DISABLED                           0x0
+#define   GCREG_SRC_EX_CONFIG_MULTI_TILED_ENABLED                            0x1
+
+/* Source super tiled address computation control. */
+#define GCREG_SRC_EX_CONFIG_SUPER_TILED                                    3 : 3
+#define GCREG_SRC_EX_CONFIG_SUPER_TILED_End                                    3
+#define GCREG_SRC_EX_CONFIG_SUPER_TILED_Start                                  3
+#define GCREG_SRC_EX_CONFIG_SUPER_TILED_Type                                 U01
+#define   GCREG_SRC_EX_CONFIG_SUPER_TILED_DISABLED                           0x0
+#define   GCREG_SRC_EX_CONFIG_SUPER_TILED_ENABLED                            0x1
+
+/* Source super tiled address computation control. */
+#define GCREG_SRC_EX_CONFIG_MINOR_TILED                                    8 : 8
+#define GCREG_SRC_EX_CONFIG_MINOR_TILED_End                                    8
+#define GCREG_SRC_EX_CONFIG_MINOR_TILED_Start                                  8
+#define GCREG_SRC_EX_CONFIG_MINOR_TILED_Type                                 U01
+#define   GCREG_SRC_EX_CONFIG_MINOR_TILED_DISABLED                           0x0
+#define   GCREG_SRC_EX_CONFIG_MINOR_TILED_ENABLED                            0x1
+
+/*******************************************************************************
+** State gcregSrcExAddress
+*/
+
+/* 32-bit aligned base address of the source extra surface. */
+
+#define gcregSrcExAddressRegAddrs                                         0x04C1
+#define GCREG_SRC_EX_ADDRESS_MSB                                              15
+#define GCREG_SRC_EX_ADDRESS_LSB                                               0
+#define GCREG_SRC_EX_ADDRESS_BLK                                               0
+#define GCREG_SRC_EX_ADDRESS_Count                                             1
+#define GCREG_SRC_EX_ADDRESS_FieldMask                                0xFFFFFFFF
+#define GCREG_SRC_EX_ADDRESS_ReadMask                                 0xFFFFFFFC
+#define GCREG_SRC_EX_ADDRESS_WriteMask                                0xFFFFFFFC
+#define GCREG_SRC_EX_ADDRESS_ResetValue                               0x00000000
+
+#define GCREG_SRC_EX_ADDRESS_ADDRESS                                      31 : 0
+#define GCREG_SRC_EX_ADDRESS_ADDRESS_End                                      30
+#define GCREG_SRC_EX_ADDRESS_ADDRESS_Start                                     0
+#define GCREG_SRC_EX_ADDRESS_ADDRESS_Type                                    U31
+
+/*******************************************************************************
+** State gcregDEMultiSource
+*/
+
+/* MutiSource control register. */
+
+#define gcregDEMultiSourceRegAddrs                                        0x04C2
+#define GCREG_DE_MULTI_SOURCE_MSB                                             15
+#define GCREG_DE_MULTI_SOURCE_LSB                                              0
+#define GCREG_DE_MULTI_SOURCE_BLK                                              0
+#define GCREG_DE_MULTI_SOURCE_Count                                            1
+#define GCREG_DE_MULTI_SOURCE_FieldMask                               0x00070707
+#define GCREG_DE_MULTI_SOURCE_ReadMask                                0x00070707
+#define GCREG_DE_MULTI_SOURCE_WriteMask                               0x00070707
+#define GCREG_DE_MULTI_SOURCE_ResetValue                              0x00000000
+
+/* Number of source surfaces minus 1. */
+#define GCREG_DE_MULTI_SOURCE_MAX_SOURCE                                   2 : 0
+#define GCREG_DE_MULTI_SOURCE_MAX_SOURCE_End                                   2
+#define GCREG_DE_MULTI_SOURCE_MAX_SOURCE_Start                                 0
+#define GCREG_DE_MULTI_SOURCE_MAX_SOURCE_Type                                U03
+
+/* Number of pixels for horizontal block walker. */
+#define GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK                            10 : 8
+#define GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_End                            10
+#define GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_Start                           8
+#define GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_Type                          U03
+#define   GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL16                     0x0
+#define   GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL32                     0x1
+#define   GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL64                     0x2
+#define   GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL128                    0x3
+#define   GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL256                    0x4
+#define   GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL512                    0x5
+
+/* Number of lines for vertical block walker. */
+#define GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK                             18 : 16
+#define GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_End                              18
+#define GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_Start                            16
+#define GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_Type                            U03
+#define   GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE1                         0x0
+#define   GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE2                         0x1
+#define   GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE4                         0x2
+#define   GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE8                         0x3
+#define   GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE16                        0x4
+#define   GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE32                        0x5
+#define   GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE64                        0x6
+#define   GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE128                       0x7
+
+struct gcregmultisource {
+	/* gcregDEMultiSourceRegAddrs:GCREG_DE_MULTI_SOURCE_MAX_SOURCE */
+	unsigned int srccount:3;
+
+	/* gcregDEMultiSourceRegAddrs:reserved */
+	unsigned int _reserved_3_7:5;
+
+	/* gcregDEMultiSourceRegAddrs:GCREG_DE_MULTI_SOURCE_HORIZONTAL_BLOCK */
+	unsigned int horblock:3;
+
+	/* gcregDEMultiSourceRegAddrs:reserved */
+	unsigned int _reserved_11_15:5;
+
+	/* gcregDEMultiSourceRegAddrs:GCREG_DE_MULTI_SOURCE_VERTICAL_BLOCK */
+	unsigned int verblock:3;
+
+	/* gcregDEMultiSourceRegAddrs:reserved */
+	unsigned int _reserved_19_31:13;
+};
+
+/*******************************************************************************
+** State gcregDEYUVConversion
+*/
+
+/* Configure the YUV to YUV conversion. */
+
+#define gcregDEYUVConversionRegAddrs                                      0x04C3
+#define GCREG_DEYUV_CONVERSION_MSB                                            15
+#define GCREG_DEYUV_CONVERSION_LSB                                             0
+#define GCREG_DEYUV_CONVERSION_BLK                                             0
+#define GCREG_DEYUV_CONVERSION_Count                                           1
+#define GCREG_DEYUV_CONVERSION_FieldMask                              0xFFFFFFFF
+#define GCREG_DEYUV_CONVERSION_ReadMask                               0xFFFFFFFF
+#define GCREG_DEYUV_CONVERSION_WriteMask                              0xFFFFFFFF
+#define GCREG_DEYUV_CONVERSION_ResetValue                             0x00000000
+
+/* Select the number of planes we need to process. */
+#define GCREG_DEYUV_CONVERSION_ENABLE                                      1 : 0
+#define GCREG_DEYUV_CONVERSION_ENABLE_End                                      1
+#define GCREG_DEYUV_CONVERSION_ENABLE_Start                                    0
+#define GCREG_DEYUV_CONVERSION_ENABLE_Type                                   U02
+/* YUV to YUV conversion is turned off. */
+#define   GCREG_DEYUV_CONVERSION_ENABLE_OFF                                  0x0
+/* YUV to YUV conversion is writing to 1 plane. */
+#define   GCREG_DEYUV_CONVERSION_ENABLE_PLANE1                               0x1
+/* YUV to YUV conversion is writing to 2 planes. */
+#define   GCREG_DEYUV_CONVERSION_ENABLE_PLANE2                               0x2
+/* YUV to YUV conversion is writing to 3 planes. */
+#define   GCREG_DEYUV_CONVERSION_ENABLE_PLANE3                               0x3
+
+/* Number of channels to process - 1 for plane 1. */
+#define GCREG_DEYUV_CONVERSION_PLANE1_COUNT                                3 : 2
+#define GCREG_DEYUV_CONVERSION_PLANE1_COUNT_End                                3
+#define GCREG_DEYUV_CONVERSION_PLANE1_COUNT_Start                              2
+#define GCREG_DEYUV_CONVERSION_PLANE1_COUNT_Type                             U02
+
+/* Number of channels to process - 1 for plane 2. */
+#define GCREG_DEYUV_CONVERSION_PLANE2_COUNT                                5 : 4
+#define GCREG_DEYUV_CONVERSION_PLANE2_COUNT_End                                5
+#define GCREG_DEYUV_CONVERSION_PLANE2_COUNT_Start                              4
+#define GCREG_DEYUV_CONVERSION_PLANE2_COUNT_Type                             U02
+
+/* Number of channels to process - 1 for plane 3. */
+#define GCREG_DEYUV_CONVERSION_PLANE3_COUNT                                7 : 6
+#define GCREG_DEYUV_CONVERSION_PLANE3_COUNT_End                                7
+#define GCREG_DEYUV_CONVERSION_PLANE3_COUNT_Start                              6
+#define GCREG_DEYUV_CONVERSION_PLANE3_COUNT_Type                             U02
+
+/* Select which color channel to pick for B channel for plane 1. */
+#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_B                            9 : 8
+#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_B_End                            9
+#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_B_Start                          8
+#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_B_Type                         U02
+#define   GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_B_BLUE                       0x0
+#define   GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_B_GREEN                      0x1
+#define   GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_B_RED                        0x2
+#define   GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_B_ALPHA                      0x3
+
+/* Select which color channel to pick for G channel for plane 1. */
+#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_G                          11 : 10
+#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_G_End                           11
+#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_G_Start                         10
+#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_G_Type                         U02
+#define   GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_G_BLUE                       0x0
+#define   GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_G_GREEN                      0x1
+#define   GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_G_RED                        0x2
+#define   GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_G_ALPHA                      0x3
+
+/* Select which color channel to pick for R channel for plane 1. */
+#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_R                          13 : 12
+#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_R_End                           13
+#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_R_Start                         12
+#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_R_Type                         U02
+#define   GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_R_BLUE                       0x0
+#define   GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_R_GREEN                      0x1
+#define   GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_R_RED                        0x2
+#define   GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_R_ALPHA                      0x3
+
+/* Select which color channel to pick for A channel for plane 1. */
+#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_A                          15 : 14
+#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_A_End                           15
+#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_A_Start                         14
+#define GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_A_Type                         U02
+#define   GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_A_BLUE                       0x0
+#define   GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_A_GREEN                      0x1
+#define   GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_A_RED                        0x2
+#define   GCREG_DEYUV_CONVERSION_PLANE1_SWIZZLE_A_ALPHA                      0x3
+
+/* Select which color channel to pick for B channel for plane 2. */
+#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_B                          17 : 16
+#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_B_End                           17
+#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_B_Start                         16
+#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_B_Type                         U02
+#define   GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_B_BLUE                       0x0
+#define   GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_B_GREEN                      0x1
+#define   GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_B_RED                        0x2
+#define   GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_B_ALPHA                      0x3
+
+/* Select which color channel to pick for G channel for plane 2. */
+#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_G                          19 : 18
+#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_G_End                           19
+#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_G_Start                         18
+#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_G_Type                         U02
+#define   GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_G_BLUE                       0x0
+#define   GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_G_GREEN                      0x1
+#define   GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_G_RED                        0x2
+#define   GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_G_ALPHA                      0x3
+
+/* Select which color channel to pick for R channel for plane 2. */
+#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_R                          21 : 20
+#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_R_End                           21
+#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_R_Start                         20
+#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_R_Type                         U02
+#define   GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_R_BLUE                       0x0
+#define   GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_R_GREEN                      0x1
+#define   GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_R_RED                        0x2
+#define   GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_R_ALPHA                      0x3
+
+/* Select which color channel to pick for A channel for plane 2. */
+#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_A                          23 : 22
+#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_A_End                           23
+#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_A_Start                         22
+#define GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_A_Type                         U02
+#define   GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_A_BLUE                       0x0
+#define   GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_A_GREEN                      0x1
+#define   GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_A_RED                        0x2
+#define   GCREG_DEYUV_CONVERSION_PLANE2_SWIZZLE_A_ALPHA                      0x3
+
+/* Select which color channel to pick for B channel for plane 3. */
+#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_B                          25 : 24
+#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_B_End                           25
+#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_B_Start                         24
+#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_B_Type                         U02
+#define   GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_B_BLUE                       0x0
+#define   GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_B_GREEN                      0x1
+#define   GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_B_RED                        0x2
+#define   GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_B_ALPHA                      0x3
+
+/* Select which color channel to pick for G channel for plane 3. */
+#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_G                          27 : 26
+#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_G_End                           27
+#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_G_Start                         26
+#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_G_Type                         U02
+#define   GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_G_BLUE                       0x0
+#define   GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_G_GREEN                      0x1
+#define   GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_G_RED                        0x2
+#define   GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_G_ALPHA                      0x3
+
+/* Select which color channel to pick for R channel for plane 3. */
+#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_R                          29 : 28
+#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_R_End                           29
+#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_R_Start                         28
+#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_R_Type                         U02
+#define   GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_R_BLUE                       0x0
+#define   GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_R_GREEN                      0x1
+#define   GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_R_RED                        0x2
+#define   GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_R_ALPHA                      0x3
+
+/* Select which color channel to pick for A channel for plane 3. */
+#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_A                          31 : 30
+#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_A_End                           31
+#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_A_Start                         30
+#define GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_A_Type                         U02
+#define   GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_A_BLUE                       0x0
+#define   GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_A_GREEN                      0x1
+#define   GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_A_RED                        0x2
+#define   GCREG_DEYUV_CONVERSION_PLANE3_SWIZZLE_A_ALPHA                      0x3
+
+/*******************************************************************************
+** State gcregDEPlane2Address
+*/
+
+/* Address for plane 2 if gcregDEYUVConversion.
+** Enable is set to Plane2 or Plane3.
+*/
+
+#define gcregDEPlane2AddressRegAddrs                                      0x04C4
+#define GCREG_DE_PLANE2_ADDRESS_Address                                  0x01310
+#define GCREG_DE_PLANE2_ADDRESS_MSB                                           15
+#define GCREG_DE_PLANE2_ADDRESS_LSB                                            0
+#define GCREG_DE_PLANE2_ADDRESS_BLK                                            0
+#define GCREG_DE_PLANE2_ADDRESS_Count                                          1
+#define GCREG_DE_PLANE2_ADDRESS_FieldMask                             0xFFFFFFFF
+#define GCREG_DE_PLANE2_ADDRESS_ReadMask                              0xFFFFFFFC
+#define GCREG_DE_PLANE2_ADDRESS_WriteMask                             0xFFFFFFFC
+#define GCREG_DE_PLANE2_ADDRESS_ResetValue                            0x00000000
+
+#define GCREG_DE_PLANE2_ADDRESS_ADDRESS                                   31 : 0
+#define GCREG_DE_PLANE2_ADDRESS_ADDRESS_End                                   30
+#define GCREG_DE_PLANE2_ADDRESS_ADDRESS_Start                                  0
+#define GCREG_DE_PLANE2_ADDRESS_ADDRESS_Type                                 U31
+
+/*******************************************************************************
+** State gcregDEPlane2Stride
+*/
+
+/* Stride for plane 2 if gcregDEYUVConversion.
+** Enable is set to Plane2 or Plane3.
+*/
+
+#define gcregDEPlane2StrideRegAddrs                                       0x04C5
+#define GCREG_DE_PLANE2_STRIDE_MSB                                            15
+#define GCREG_DE_PLANE2_STRIDE_LSB                                             0
+#define GCREG_DE_PLANE2_STRIDE_BLK                                             0
+#define GCREG_DE_PLANE2_STRIDE_Count                                           1
+#define GCREG_DE_PLANE2_STRIDE_FieldMask                              0x0003FFFF
+#define GCREG_DE_PLANE2_STRIDE_ReadMask                               0x0003FFFC
+#define GCREG_DE_PLANE2_STRIDE_WriteMask                              0x0003FFFC
+#define GCREG_DE_PLANE2_STRIDE_ResetValue                             0x00000000
+
+#define GCREG_DE_PLANE2_STRIDE_STRIDE                                     17 : 0
+#define GCREG_DE_PLANE2_STRIDE_STRIDE_End                                     17
+#define GCREG_DE_PLANE2_STRIDE_STRIDE_Start                                    0
+#define GCREG_DE_PLANE2_STRIDE_STRIDE_Type                                   U18
+
+/*******************************************************************************
+** State gcregDEPlane3Address
+*/
+
+/* Address for plane 3 if gcregDEYUVConversion.
+** Enable is set to Plane3.
+*/
+
+#define gcregDEPlane3AddressRegAddrs                                      0x04C6
+#define GCREG_DE_PLANE3_ADDRESS_MSB                                           15
+#define GCREG_DE_PLANE3_ADDRESS_LSB                                            0
+#define GCREG_DE_PLANE3_ADDRESS_BLK                                            0
+#define GCREG_DE_PLANE3_ADDRESS_Count                                          1
+#define GCREG_DE_PLANE3_ADDRESS_FieldMask                             0xFFFFFFFF
+#define GCREG_DE_PLANE3_ADDRESS_ReadMask                              0xFFFFFFFC
+#define GCREG_DE_PLANE3_ADDRESS_WriteMask                             0xFFFFFFFC
+#define GCREG_DE_PLANE3_ADDRESS_ResetValue                            0x00000000
+
+#define GCREG_DE_PLANE3_ADDRESS_ADDRESS                                   31 : 0
+#define GCREG_DE_PLANE3_ADDRESS_ADDRESS_End                                   30
+#define GCREG_DE_PLANE3_ADDRESS_ADDRESS_Start                                  0
+#define GCREG_DE_PLANE3_ADDRESS_ADDRESS_Type                                 U31
+
+/*******************************************************************************
+** State gcregDEPlane3Stride
+*/
+
+/* Stride for plane 3 if gcregDEYUVConversion.
+** Enable is set to Plane3.
+*/
+
+#define gcregDEPlane3StrideRegAddrs                                       0x04C7
+#define GCREG_DE_PLANE3_STRIDE_MSB                                            15
+#define GCREG_DE_PLANE3_STRIDE_LSB                                             0
+#define GCREG_DE_PLANE3_STRIDE_BLK                                             0
+#define GCREG_DE_PLANE3_STRIDE_Count                                           1
+#define GCREG_DE_PLANE3_STRIDE_FieldMask                              0x0003FFFF
+#define GCREG_DE_PLANE3_STRIDE_ReadMask                               0x0003FFFC
+#define GCREG_DE_PLANE3_STRIDE_WriteMask                              0x0003FFFC
+#define GCREG_DE_PLANE3_STRIDE_ResetValue                             0x00000000
+
+#define GCREG_DE_PLANE3_STRIDE_STRIDE                                     17 : 0
+#define GCREG_DE_PLANE3_STRIDE_STRIDE_End                                     17
+#define GCREG_DE_PLANE3_STRIDE_STRIDE_Start                                    0
+#define GCREG_DE_PLANE3_STRIDE_STRIDE_Type                                   U18
+
+/*******************************************************************************
+** State gcregDEStallDE
+*/
+
+#define gcregDEStallDERegAddrs                                            0x04C8
+#define GCREG_DE_STALL_DE_MSB                                                 15
+#define GCREG_DE_STALL_DE_LSB                                                  0
+#define GCREG_DE_STALL_DE_BLK                                                  0
+#define GCREG_DE_STALL_DE_Count                                                1
+#define GCREG_DE_STALL_DE_FieldMask                                   0x00000001
+#define GCREG_DE_STALL_DE_ReadMask                                    0x00000001
+#define GCREG_DE_STALL_DE_WriteMask                                   0x00000001
+#define GCREG_DE_STALL_DE_ResetValue                                  0x00000000
+
+/* Stall de enable. */
+#define GCREG_DE_STALL_DE_ENABLE                                           0 : 0
+#define GCREG_DE_STALL_DE_ENABLE_End                                           0
+#define GCREG_DE_STALL_DE_ENABLE_Start                                         0
+#define GCREG_DE_STALL_DE_ENABLE_Type                                        U01
+#define   GCREG_DE_STALL_DE_ENABLE_DISABLED                                  0x0
+#define   GCREG_DE_STALL_DE_ENABLE_ENABLED                                   0x1
+
+/*******************************************************************************
+** State gcregBlock4SrcAddress
+*/
+
+/* 32-bit aligned base address of the source surface. */
+
+#define gcregBlock4SrcAddressRegAddrs                                     0x4A00
+#define GCREG_BLOCK4_SRC_ADDRESS_MSB                                          15
+#define GCREG_BLOCK4_SRC_ADDRESS_LSB                                           2
+#define GCREG_BLOCK4_SRC_ADDRESS_BLK                                           0
+#define GCREG_BLOCK4_SRC_ADDRESS_Count                                         4
+#define GCREG_BLOCK4_SRC_ADDRESS_FieldMask                            0xFFFFFFFF
+#define GCREG_BLOCK4_SRC_ADDRESS_ReadMask                             0xFFFFFFFC
+#define GCREG_BLOCK4_SRC_ADDRESS_WriteMask                            0xFFFFFFFC
+#define GCREG_BLOCK4_SRC_ADDRESS_ResetValue                           0x00000000
+
+#define GCREG_BLOCK4_SRC_ADDRESS_ADDRESS                                  31 : 0
+#define GCREG_BLOCK4_SRC_ADDRESS_ADDRESS_End                                  30
+#define GCREG_BLOCK4_SRC_ADDRESS_ADDRESS_Start                                 0
+#define GCREG_BLOCK4_SRC_ADDRESS_ADDRESS_Type                                U31
+
+/*******************************************************************************
+** State gcregBlock4SrcStride
+*/
+
+/* Stride of the source surface in bytes. To calculate the stride multiply
+** the surface width in pixels by the number of  bytes per pixel.
+*/
+
+#define gcregBlock4SrcStrideRegAddrs                                      0x4A04
+#define GCREG_BLOCK4_SRC_STRIDE_MSB                                           15
+#define GCREG_BLOCK4_SRC_STRIDE_LSB                                            2
+#define GCREG_BLOCK4_SRC_STRIDE_BLK                                            0
+#define GCREG_BLOCK4_SRC_STRIDE_Count                                          4
+#define GCREG_BLOCK4_SRC_STRIDE_FieldMask                             0x0003FFFF
+#define GCREG_BLOCK4_SRC_STRIDE_ReadMask                              0x0003FFFC
+#define GCREG_BLOCK4_SRC_STRIDE_WriteMask                             0x0003FFFC
+#define GCREG_BLOCK4_SRC_STRIDE_ResetValue                            0x00000000
+
+#define GCREG_BLOCK4_SRC_STRIDE_STRIDE                                    17 : 0
+#define GCREG_BLOCK4_SRC_STRIDE_STRIDE_End                                    17
+#define GCREG_BLOCK4_SRC_STRIDE_STRIDE_Start                                   0
+#define GCREG_BLOCK4_SRC_STRIDE_STRIDE_Type                                  U18
+
+/*******************************************************************************
+** State gcregBlock4SrcRotationConfig
+*/
+
+/* 90 degree rotation configuration for the source surface. Width field
+** specifies the width of the surface in pixels.
+*/
+
+#define gcregBlock4SrcRotationConfigRegAddrs                              0x4A08
+#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_MSB                                  15
+#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_LSB                                   2
+#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_BLK                                   0
+#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_Count                                 4
+#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_FieldMask                    0x0001FFFF
+#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_ReadMask                     0x0001FFFF
+#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_WriteMask                    0x0001FFFF
+#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_ResetValue                   0x00000000
+
+#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_WIDTH                            15 : 0
+#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_WIDTH_End                            15
+#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_WIDTH_Start                           0
+#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_WIDTH_Type                          U16
+
+#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_ROTATION                        16 : 16
+#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_ROTATION_End                         16
+#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_ROTATION_Start                       16
+#define GCREG_BLOCK4_SRC_ROTATION_CONFIG_ROTATION_Type                       U01
+#define   GCREG_BLOCK4_SRC_ROTATION_CONFIG_ROTATION_DISABLE                  0x0
+#define   GCREG_BLOCK4_SRC_ROTATION_CONFIG_ROTATION_ENABLE                   0x1
+
+/*******************************************************************************
+** State gcregBlock4SrcConfig
+*/
+
+/* Source surface configuration register. */
+
+#define gcregBlock4SrcConfigRegAddrs                                      0x4A0C
+#define GCREG_BLOCK4_SRC_CONFIG_MSB                                           15
+#define GCREG_BLOCK4_SRC_CONFIG_LSB                                            2
+#define GCREG_BLOCK4_SRC_CONFIG_BLK                                            0
+#define GCREG_BLOCK4_SRC_CONFIG_Count                                          4
+#define GCREG_BLOCK4_SRC_CONFIG_FieldMask                             0xDF30B1C0
+#define GCREG_BLOCK4_SRC_CONFIG_ReadMask                              0xDF30B1C0
+#define GCREG_BLOCK4_SRC_CONFIG_WriteMask                             0xDF30B1C0
+#define GCREG_BLOCK4_SRC_CONFIG_ResetValue                            0x00000000
+
+/* Control source endianess. */
+#define GCREG_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL                           31 : 30
+#define GCREG_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL_End                            31
+#define GCREG_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL_Start                          30
+#define GCREG_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL_Type                          U02
+#define   GCREG_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL_NO_SWAP                     0x0
+#define   GCREG_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL_SWAP_WORD                   0x1
+#define   GCREG_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL_SWAP_DWORD                  0x2
+
+/* Defines the pixel format of the source surface. */
+#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT                            28 : 24
+#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_End                             28
+#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_Start                           24
+#define GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_Type                           U05
+#define   GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_X4R4G4B4                    0x00
+#define   GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_A4R4G4B4                    0x01
+#define   GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_X1R5G5B5                    0x02
+#define   GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_A1R5G5B5                    0x03
+#define   GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_R5G6B5                      0x04
+#define   GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_X8R8G8B8                    0x05
+#define   GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_A8R8G8B8                    0x06
+#define   GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_YUY2                        0x07
+#define   GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_UYVY                        0x08
+#define   GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_INDEX8                      0x09
+#define   GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_MONOCHROME                  0x0A
+#define   GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_YV12                        0x0F
+#define   GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_A8                          0x10
+#define   GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_NV12                        0x11
+#define   GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_NV16                        0x12
+#define   GCREG_BLOCK4_SRC_CONFIG_SOURCE_FORMAT_RG16                        0x13
+
+/* Color channel swizzles. */
+#define GCREG_BLOCK4_SRC_CONFIG_SWIZZLE                                  21 : 20
+#define GCREG_BLOCK4_SRC_CONFIG_SWIZZLE_End                                   21
+#define GCREG_BLOCK4_SRC_CONFIG_SWIZZLE_Start                                 20
+#define GCREG_BLOCK4_SRC_CONFIG_SWIZZLE_Type                                 U02
+#define   GCREG_BLOCK4_SRC_CONFIG_SWIZZLE_ARGB                               0x0
+#define   GCREG_BLOCK4_SRC_CONFIG_SWIZZLE_RGBA                               0x1
+#define   GCREG_BLOCK4_SRC_CONFIG_SWIZZLE_ABGR                               0x2
+#define   GCREG_BLOCK4_SRC_CONFIG_SWIZZLE_BGRA                               0x3
+
+/* Mono expansion: if 0, transparency color will be 0, otherwise transparency **
+** color will be 1.                                                           */
+#define GCREG_BLOCK4_SRC_CONFIG_MONO_TRANSPARENCY                        15 : 15
+#define GCREG_BLOCK4_SRC_CONFIG_MONO_TRANSPARENCY_End                         15
+#define GCREG_BLOCK4_SRC_CONFIG_MONO_TRANSPARENCY_Start                       15
+#define GCREG_BLOCK4_SRC_CONFIG_MONO_TRANSPARENCY_Type                       U01
+#define   GCREG_BLOCK4_SRC_CONFIG_MONO_TRANSPARENCY_BACKGROUND               0x0
+#define   GCREG_BLOCK4_SRC_CONFIG_MONO_TRANSPARENCY_FOREGROUND               0x1
+
+/* Mono expansion or masked blit: stream packing in pixels. Determines how    **
+** many horizontal pixels are there per each 32-bit chunk. For example, if    **
+** set to Packed8, each 32-bit chunk is 8-pixel wide, which also means that   **
+** it defines 4 vertical lines of pixels.                                     */
+#define GCREG_BLOCK4_SRC_CONFIG_PACK                                     13 : 12
+#define GCREG_BLOCK4_SRC_CONFIG_PACK_End                                      13
+#define GCREG_BLOCK4_SRC_CONFIG_PACK_Start                                    12
+#define GCREG_BLOCK4_SRC_CONFIG_PACK_Type                                    U02
+#define   GCREG_BLOCK4_SRC_CONFIG_PACK_PACKED8                               0x0
+#define   GCREG_BLOCK4_SRC_CONFIG_PACK_PACKED16                              0x1
+#define   GCREG_BLOCK4_SRC_CONFIG_PACK_PACKED32                              0x2
+#define   GCREG_BLOCK4_SRC_CONFIG_PACK_UNPACKED                              0x3
+
+/* Source data location: set to STREAM for mono expansion blits or masked     **
+** blits. For mono expansion blits the complete bitmap comes from the command **
+** stream. For masked blits the source data comes from the memory and the     **
+** mask from the command stream.                                              */
+#define GCREG_BLOCK4_SRC_CONFIG_LOCATION                                   8 : 8
+#define GCREG_BLOCK4_SRC_CONFIG_LOCATION_End                                   8
+#define GCREG_BLOCK4_SRC_CONFIG_LOCATION_Start                                 8
+#define GCREG_BLOCK4_SRC_CONFIG_LOCATION_Type                                U01
+#define   GCREG_BLOCK4_SRC_CONFIG_LOCATION_MEMORY                            0x0
+#define   GCREG_BLOCK4_SRC_CONFIG_LOCATION_STREAM                            0x1
+
+/* Source linear/tiled address computation control. */
+#define GCREG_BLOCK4_SRC_CONFIG_TILED                                      7 : 7
+#define GCREG_BLOCK4_SRC_CONFIG_TILED_End                                      7
+#define GCREG_BLOCK4_SRC_CONFIG_TILED_Start                                    7
+#define GCREG_BLOCK4_SRC_CONFIG_TILED_Type                                   U01
+#define   GCREG_BLOCK4_SRC_CONFIG_TILED_DISABLED                             0x0
+#define   GCREG_BLOCK4_SRC_CONFIG_TILED_ENABLED                              0x1
+
+/* If set to ABSOLUTE, the source coordinates are treated as absolute         **
+** coordinates inside the source surface. If set to RELATIVE, the source      **
+** coordinates are treated as the offsets from the destination coordinates    **
+** with the source size equal to the size of the destination.                 */
+#define GCREG_BLOCK4_SRC_CONFIG_SRC_RELATIVE                               6 : 6
+#define GCREG_BLOCK4_SRC_CONFIG_SRC_RELATIVE_End                               6
+#define GCREG_BLOCK4_SRC_CONFIG_SRC_RELATIVE_Start                             6
+#define GCREG_BLOCK4_SRC_CONFIG_SRC_RELATIVE_Type                            U01
+#define   GCREG_BLOCK4_SRC_CONFIG_SRC_RELATIVE_ABSOLUTE                      0x0
+#define   GCREG_BLOCK4_SRC_CONFIG_SRC_RELATIVE_RELATIVE                      0x1
+
+/*******************************************************************************
+** State gcregBlock4SrcOrigin
+*/
+
+/* Absolute or relative (see SRC_RELATIVE field of gcregBlock4SrcConfig
+** register) X and Y coordinates in pixels of the top left corner of the
+** source rectangle within the source surface.
+*/
+
+#define gcregBlock4SrcOriginRegAddrs                                      0x4A10
+#define GCREG_BLOCK4_SRC_ORIGIN_MSB                                           15
+#define GCREG_BLOCK4_SRC_ORIGIN_LSB                                            2
+#define GCREG_BLOCK4_SRC_ORIGIN_BLK                                            0
+#define GCREG_BLOCK4_SRC_ORIGIN_Count                                          4
+#define GCREG_BLOCK4_SRC_ORIGIN_FieldMask                             0xFFFFFFFF
+#define GCREG_BLOCK4_SRC_ORIGIN_ReadMask                              0xFFFFFFFF
+#define GCREG_BLOCK4_SRC_ORIGIN_WriteMask                             0xFFFFFFFF
+#define GCREG_BLOCK4_SRC_ORIGIN_ResetValue                            0x00000000
+
+#define GCREG_BLOCK4_SRC_ORIGIN_Y                                        31 : 16
+#define GCREG_BLOCK4_SRC_ORIGIN_Y_End                                         31
+#define GCREG_BLOCK4_SRC_ORIGIN_Y_Start                                       16
+#define GCREG_BLOCK4_SRC_ORIGIN_Y_Type                                       U16
+
+#define GCREG_BLOCK4_SRC_ORIGIN_X                                         15 : 0
+#define GCREG_BLOCK4_SRC_ORIGIN_X_End                                         15
+#define GCREG_BLOCK4_SRC_ORIGIN_X_Start                                        0
+#define GCREG_BLOCK4_SRC_ORIGIN_X_Type                                       U16
+
+/*******************************************************************************
+** State gcregBlock4SrcSize
+*/
+
+/* Width and height of the source rectangle in pixels. If the source is
+** relative (see SRC_RELATIVE field of gcregBlock4SrcConfig register) or a
+** regular bitblt is being performed without stretching, this register is
+** ignored and the source size is assumed to be the same as the destination.
+*/
+
+#define gcregBlock4SrcSizeRegAddrs                                        0x4A14
+#define GCREG_BLOCK4_SRC_SIZE_MSB                                             15
+#define GCREG_BLOCK4_SRC_SIZE_LSB                                              2
+#define GCREG_BLOCK4_SRC_SIZE_BLK                                              0
+#define GCREG_BLOCK4_SRC_SIZE_Count                                            4
+#define GCREG_BLOCK4_SRC_SIZE_FieldMask                               0xFFFFFFFF
+#define GCREG_BLOCK4_SRC_SIZE_ReadMask                                0xFFFFFFFF
+#define GCREG_BLOCK4_SRC_SIZE_WriteMask                               0xFFFFFFFF
+#define GCREG_BLOCK4_SRC_SIZE_ResetValue                              0x00000000
+
+#define GCREG_BLOCK4_SRC_SIZE_Y                                          31 : 16
+#define GCREG_BLOCK4_SRC_SIZE_Y_End                                           31
+#define GCREG_BLOCK4_SRC_SIZE_Y_Start                                         16
+#define GCREG_BLOCK4_SRC_SIZE_Y_Type                                         U16
+
+#define GCREG_BLOCK4_SRC_SIZE_X                                           15 : 0
+#define GCREG_BLOCK4_SRC_SIZE_X_End                                           15
+#define GCREG_BLOCK4_SRC_SIZE_X_Start                                          0
+#define GCREG_BLOCK4_SRC_SIZE_X_Type                                         U16
+
+/*******************************************************************************
+** State gcregBlock4SrcColorBg
+*/
+
+/* Select the color where source becomes transparent. It must be programmed
+** in A8R8G8B8 format.
+*/
+
+#define gcregBlock4SrcColorBgRegAddrs                                     0x4A18
+#define GCREG_BLOCK4_SRC_COLOR_BG_MSB                                         15
+#define GCREG_BLOCK4_SRC_COLOR_BG_LSB                                          2
+#define GCREG_BLOCK4_SRC_COLOR_BG_BLK                                          0
+#define GCREG_BLOCK4_SRC_COLOR_BG_Count                                        4
+#define GCREG_BLOCK4_SRC_COLOR_BG_FieldMask                           0xFFFFFFFF
+#define GCREG_BLOCK4_SRC_COLOR_BG_ReadMask                            0xFFFFFFFF
+#define GCREG_BLOCK4_SRC_COLOR_BG_WriteMask                           0xFFFFFFFF
+#define GCREG_BLOCK4_SRC_COLOR_BG_ResetValue                          0x00000000
+
+#define GCREG_BLOCK4_SRC_COLOR_BG_ALPHA                                  31 : 24
+#define GCREG_BLOCK4_SRC_COLOR_BG_ALPHA_End                                   31
+#define GCREG_BLOCK4_SRC_COLOR_BG_ALPHA_Start                                 24
+#define GCREG_BLOCK4_SRC_COLOR_BG_ALPHA_Type                                 U08
+
+#define GCREG_BLOCK4_SRC_COLOR_BG_RED                                    23 : 16
+#define GCREG_BLOCK4_SRC_COLOR_BG_RED_End                                     23
+#define GCREG_BLOCK4_SRC_COLOR_BG_RED_Start                                   16
+#define GCREG_BLOCK4_SRC_COLOR_BG_RED_Type                                   U08
+
+#define GCREG_BLOCK4_SRC_COLOR_BG_GREEN                                   15 : 8
+#define GCREG_BLOCK4_SRC_COLOR_BG_GREEN_End                                   15
+#define GCREG_BLOCK4_SRC_COLOR_BG_GREEN_Start                                  8
+#define GCREG_BLOCK4_SRC_COLOR_BG_GREEN_Type                                 U08
+
+#define GCREG_BLOCK4_SRC_COLOR_BG_BLUE                                     7 : 0
+#define GCREG_BLOCK4_SRC_COLOR_BG_BLUE_End                                     7
+#define GCREG_BLOCK4_SRC_COLOR_BG_BLUE_Start                                   0
+#define GCREG_BLOCK4_SRC_COLOR_BG_BLUE_Type                                  U08
+
+/*******************************************************************************
+** State gcregBlock4Rop
+*/
+
+/* Raster operation foreground and background codes. Even though ROP is not
+** used in CLEAR, HOR_FILTER_BLT, VER_FILTER_BLT and alpha-eanbled BIT_BLTs,
+** ROP code still has to be programmed, because the engine makes the decision
+** whether source, destination and pattern are involved in the current
+** operation and the correct decision is essential for the engine to complete
+** the operation as expected.
+*/
+
+#define gcregBlock4RopRegAddrs                                            0x4A1C
+#define GCREG_BLOCK4_ROP_MSB                                                  15
+#define GCREG_BLOCK4_ROP_LSB                                                   2
+#define GCREG_BLOCK4_ROP_BLK                                                   0
+#define GCREG_BLOCK4_ROP_Count                                                 4
+#define GCREG_BLOCK4_ROP_FieldMask                                    0x0030FFFF
+#define GCREG_BLOCK4_ROP_ReadMask                                     0x0030FFFF
+#define GCREG_BLOCK4_ROP_WriteMask                                    0x0030FFFF
+#define GCREG_BLOCK4_ROP_ResetValue                                   0x00000000
+
+/* ROP type: ROP2, ROP3 or ROP4 */
+#define GCREG_BLOCK4_ROP_TYPE                                            21 : 20
+#define GCREG_BLOCK4_ROP_TYPE_End                                             21
+#define GCREG_BLOCK4_ROP_TYPE_Start                                           20
+#define GCREG_BLOCK4_ROP_TYPE_Type                                           U02
+#define   GCREG_BLOCK4_ROP_TYPE_ROP2_PATTERN                                 0x0
+#define   GCREG_BLOCK4_ROP_TYPE_ROP2_SOURCE                                  0x1
+#define   GCREG_BLOCK4_ROP_TYPE_ROP3                                         0x2
+#define   GCREG_BLOCK4_ROP_TYPE_ROP4                                         0x3
+
+/* Background ROP code is used for transparent pixels. */
+#define GCREG_BLOCK4_ROP_ROP_BG                                           15 : 8
+#define GCREG_BLOCK4_ROP_ROP_BG_End                                           15
+#define GCREG_BLOCK4_ROP_ROP_BG_Start                                          8
+#define GCREG_BLOCK4_ROP_ROP_BG_Type                                         U08
+
+/* Background ROP code is used for opaque pixels. */
+#define GCREG_BLOCK4_ROP_ROP_FG                                            7 : 0
+#define GCREG_BLOCK4_ROP_ROP_FG_End                                            7
+#define GCREG_BLOCK4_ROP_ROP_FG_Start                                          0
+#define GCREG_BLOCK4_ROP_ROP_FG_Type                                         U08
+
+/*******************************************************************************
+** State gcregBlock4AlphaControl
+*/
+
+#define gcregBlock4AlphaControlRegAddrs                                   0x4A20
+#define GCREG_BLOCK4_ALPHA_CONTROL_MSB                                        15
+#define GCREG_BLOCK4_ALPHA_CONTROL_LSB                                         2
+#define GCREG_BLOCK4_ALPHA_CONTROL_BLK                                         0
+#define GCREG_BLOCK4_ALPHA_CONTROL_Count                                       4
+#define GCREG_BLOCK4_ALPHA_CONTROL_FieldMask                          0x00000001
+#define GCREG_BLOCK4_ALPHA_CONTROL_ReadMask                           0x00000001
+#define GCREG_BLOCK4_ALPHA_CONTROL_WriteMask                          0x00000001
+#define GCREG_BLOCK4_ALPHA_CONTROL_ResetValue                         0x00000000
+
+#define GCREG_BLOCK4_ALPHA_CONTROL_ENABLE                                  0 : 0
+#define GCREG_BLOCK4_ALPHA_CONTROL_ENABLE_End                                  0
+#define GCREG_BLOCK4_ALPHA_CONTROL_ENABLE_Start                                0
+#define GCREG_BLOCK4_ALPHA_CONTROL_ENABLE_Type                               U01
+#define   GCREG_BLOCK4_ALPHA_CONTROL_ENABLE_OFF                              0x0
+#define   GCREG_BLOCK4_ALPHA_CONTROL_ENABLE_ON                               0x1
+
+/*******************************************************************************
+** State gcregBlock4AlphaModes
+*/
+
+#define gcregBlock4AlphaModesRegAddrs                                     0x4A24
+#define GCREG_BLOCK4_ALPHA_MODES_MSB                                          15
+#define GCREG_BLOCK4_ALPHA_MODES_LSB                                           2
+#define GCREG_BLOCK4_ALPHA_MODES_BLK                                           0
+#define GCREG_BLOCK4_ALPHA_MODES_Count                                         4
+#define GCREG_BLOCK4_ALPHA_MODES_FieldMask                            0xFF003311
+#define GCREG_BLOCK4_ALPHA_MODES_ReadMask                             0xFF003311
+#define GCREG_BLOCK4_ALPHA_MODES_WriteMask                            0xFF003311
+#define GCREG_BLOCK4_ALPHA_MODES_ResetValue                           0x00000000
+
+#define GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_MODE                            0 : 0
+#define GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_MODE_End                            0
+#define GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_MODE_Start                          0
+#define GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_MODE_Type                         U01
+#define   GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_MODE_NORMAL                     0x0
+#define   GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_MODE_INVERSED                   0x1
+
+#define GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_MODE                            4 : 4
+#define GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_MODE_End                            4
+#define GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_MODE_Start                          4
+#define GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_MODE_Type                         U01
+#define   GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_MODE_NORMAL                     0x0
+#define   GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_MODE_INVERSED                   0x1
+
+#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE                     9 : 8
+#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_End                     9
+#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_Start                   8
+#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_Type                  U02
+#define   GCREG_BLOCK4_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_NORMAL              0x0
+#define   GCREG_BLOCK4_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_GLOBAL              0x1
+#define   GCREG_BLOCK4_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_SCALED              0x2
+
+#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE                   13 : 12
+#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_End                    13
+#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_Start                  12
+#define GCREG_BLOCK4_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_Type                  U02
+#define   GCREG_BLOCK4_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_NORMAL              0x0
+#define   GCREG_BLOCK4_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_GLOBAL              0x1
+#define   GCREG_BLOCK4_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_SCALED              0x2
+
+#define GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE                       26 : 24
+#define GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_End                        26
+#define GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_Start                      24
+#define GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_Type                      U03
+#define   GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_ZERO                    0x0
+#define   GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_ONE                     0x1
+#define   GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_NORMAL                  0x2
+#define   GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_INVERSED                0x3
+#define   GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_COLOR                   0x4
+#define   GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_COLOR_INVERSED          0x5
+#define   GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_SATURATED_ALPHA         0x6
+#define   GCREG_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE_SATURATED_DEST_ALPHA    0x7
+
+/* Src Blending factor is calculate from Src alpha. */
+#define GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_FACTOR                        27 : 27
+#define GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_FACTOR_End                         27
+#define GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_FACTOR_Start                       27
+#define GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_FACTOR_Type                       U01
+#define   GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_FACTOR_DISABLED                 0x0
+#define   GCREG_BLOCK4_ALPHA_MODES_SRC_ALPHA_FACTOR_ENABLED                  0x1
+
+#define GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE                       30 : 28
+#define GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_End                        30
+#define GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_Start                      28
+#define GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_Type                      U03
+#define   GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_ZERO                    0x0
+#define   GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_ONE                     0x1
+#define   GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_NORMAL                  0x2
+#define   GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_INVERSED                0x3
+#define   GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_COLOR                   0x4
+#define   GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_COLOR_INVERSED          0x5
+#define   GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_SATURATED_ALPHA         0x6
+#define   GCREG_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE_SATURATED_DEST_ALPHA    0x7
+
+/* Dst Blending factor is calculate from Dst alpha. */
+#define GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_FACTOR                        31 : 31
+#define GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_FACTOR_End                         31
+#define GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_FACTOR_Start                       31
+#define GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_FACTOR_Type                       U01
+#define   GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_FACTOR_DISABLED                 0x0
+#define   GCREG_BLOCK4_ALPHA_MODES_DST_ALPHA_FACTOR_ENABLED                  0x1
+
+/*******************************************************************************
+** State gcregBlock4AddressU
+*/
+
+/* 32-bit aligned base address of the source U plane. */
+
+#define gcregBlock4AddressURegAddrs                                       0x4A28
+#define GCREG_BLOCK4_ADDRESS_U_MSB                                            15
+#define GCREG_BLOCK4_ADDRESS_U_LSB                                             2
+#define GCREG_BLOCK4_ADDRESS_U_BLK                                             0
+#define GCREG_BLOCK4_ADDRESS_U_Count                                           4
+#define GCREG_BLOCK4_ADDRESS_U_FieldMask                              0xFFFFFFFF
+#define GCREG_BLOCK4_ADDRESS_U_ReadMask                               0xFFFFFFFC
+#define GCREG_BLOCK4_ADDRESS_U_WriteMask                              0xFFFFFFFC
+#define GCREG_BLOCK4_ADDRESS_U_ResetValue                             0x00000000
+
+#define GCREG_BLOCK4_ADDRESS_U_ADDRESS                                    31 : 0
+#define GCREG_BLOCK4_ADDRESS_U_ADDRESS_End                                    30
+#define GCREG_BLOCK4_ADDRESS_U_ADDRESS_Start                                   0
+#define GCREG_BLOCK4_ADDRESS_U_ADDRESS_Type                                  U31
+
+/*******************************************************************************
+** State gcregBlock4StrideU
+*/
+
+/* Stride of the source U plane in bytes. */
+
+#define gcregBlock4StrideURegAddrs                                        0x4A2C
+#define GCREG_BLOCK4_STRIDE_U_MSB                                             15
+#define GCREG_BLOCK4_STRIDE_U_LSB                                              2
+#define GCREG_BLOCK4_STRIDE_U_BLK                                              0
+#define GCREG_BLOCK4_STRIDE_U_Count                                            4
+#define GCREG_BLOCK4_STRIDE_U_FieldMask                               0x0003FFFF
+#define GCREG_BLOCK4_STRIDE_U_ReadMask                                0x0003FFFC
+#define GCREG_BLOCK4_STRIDE_U_WriteMask                               0x0003FFFC
+#define GCREG_BLOCK4_STRIDE_U_ResetValue                              0x00000000
+
+#define GCREG_BLOCK4_STRIDE_U_STRIDE                                      17 : 0
+#define GCREG_BLOCK4_STRIDE_U_STRIDE_End                                      17
+#define GCREG_BLOCK4_STRIDE_U_STRIDE_Start                                     0
+#define GCREG_BLOCK4_STRIDE_U_STRIDE_Type                                    U18
+
+/*******************************************************************************
+** State gcregBlock4AddressV
+*/
+
+/* 32-bit aligned base address of the source V plane. */
+
+#define gcregBlock4AddressVRegAddrs                                       0x4A30
+#define GCREG_BLOCK4_ADDRESS_V_MSB                                            15
+#define GCREG_BLOCK4_ADDRESS_V_LSB                                             2
+#define GCREG_BLOCK4_ADDRESS_V_BLK                                             0
+#define GCREG_BLOCK4_ADDRESS_V_Count                                           4
+#define GCREG_BLOCK4_ADDRESS_V_FieldMask                              0xFFFFFFFF
+#define GCREG_BLOCK4_ADDRESS_V_ReadMask                               0xFFFFFFFC
+#define GCREG_BLOCK4_ADDRESS_V_WriteMask                              0xFFFFFFFC
+#define GCREG_BLOCK4_ADDRESS_V_ResetValue                             0x00000000
+
+#define GCREG_BLOCK4_ADDRESS_V_ADDRESS                                    31 : 0
+#define GCREG_BLOCK4_ADDRESS_V_ADDRESS_End                                    30
+#define GCREG_BLOCK4_ADDRESS_V_ADDRESS_Start                                   0
+#define GCREG_BLOCK4_ADDRESS_V_ADDRESS_Type                                  U31
+
+/*******************************************************************************
+** State gcregBlock4StrideV
+*/
+
+/* Stride of the source V plane in bytes. */
+
+#define gcregBlock4StrideVRegAddrs                                        0x4A34
+#define GCREG_BLOCK4_STRIDE_V_MSB                                             15
+#define GCREG_BLOCK4_STRIDE_V_LSB                                              2
+#define GCREG_BLOCK4_STRIDE_V_BLK                                              0
+#define GCREG_BLOCK4_STRIDE_V_Count                                            4
+#define GCREG_BLOCK4_STRIDE_V_FieldMask                               0x0003FFFF
+#define GCREG_BLOCK4_STRIDE_V_ReadMask                                0x0003FFFC
+#define GCREG_BLOCK4_STRIDE_V_WriteMask                               0x0003FFFC
+#define GCREG_BLOCK4_STRIDE_V_ResetValue                              0x00000000
+
+#define GCREG_BLOCK4_STRIDE_V_STRIDE                                      17 : 0
+#define GCREG_BLOCK4_STRIDE_V_STRIDE_End                                      17
+#define GCREG_BLOCK4_STRIDE_V_STRIDE_Start                                     0
+#define GCREG_BLOCK4_STRIDE_V_STRIDE_Type                                    U18
+
+/*******************************************************************************
+** State gcregBlock4SrcRotationHeight
+*/
+
+/* 180/270 degree rotation configuration for the Source surface. Height field
+** specifies the height of the surface in pixels.
+*/
+
+#define gcregBlock4SrcRotationHeightRegAddrs                              0x4A38
+#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_MSB                                  15
+#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_LSB                                   2
+#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_BLK                                   0
+#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_Count                                 4
+#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_FieldMask                    0x0000FFFF
+#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_ReadMask                     0x0000FFFF
+#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_WriteMask                    0x0000FFFF
+#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_ResetValue                   0x00000000
+
+#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_HEIGHT                           15 : 0
+#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_HEIGHT_End                           15
+#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_HEIGHT_Start                          0
+#define GCREG_BLOCK4_SRC_ROTATION_HEIGHT_HEIGHT_Type                         U16
+
+/*******************************************************************************
+** State gcregBlock4RotAngle
+*/
+
+/* 0/90/180/270 degree rotation configuration for the Source surface. Height
+** field specifies the height of the surface in pixels.
+*/
+
+#define gcregBlock4RotAngleRegAddrs                                       0x4A3C
+#define GCREG_BLOCK4_ROT_ANGLE_MSB                                            15
+#define GCREG_BLOCK4_ROT_ANGLE_LSB                                             2
+#define GCREG_BLOCK4_ROT_ANGLE_BLK                                             0
+#define GCREG_BLOCK4_ROT_ANGLE_Count                                           4
+#define GCREG_BLOCK4_ROT_ANGLE_FieldMask                              0x000BB33F
+#define GCREG_BLOCK4_ROT_ANGLE_ReadMask                               0x000BB33F
+#define GCREG_BLOCK4_ROT_ANGLE_WriteMask                              0x000BB33F
+#define GCREG_BLOCK4_ROT_ANGLE_ResetValue                             0x00000000
+
+#define GCREG_BLOCK4_ROT_ANGLE_SRC                                         2 : 0
+#define GCREG_BLOCK4_ROT_ANGLE_SRC_End                                         2
+#define GCREG_BLOCK4_ROT_ANGLE_SRC_Start                                       0
+#define GCREG_BLOCK4_ROT_ANGLE_SRC_Type                                      U03
+#define   GCREG_BLOCK4_ROT_ANGLE_SRC_ROT0                                    0x0
+#define   GCREG_BLOCK4_ROT_ANGLE_SRC_FLIP_X                                  0x1
+#define   GCREG_BLOCK4_ROT_ANGLE_SRC_FLIP_Y                                  0x2
+#define   GCREG_BLOCK4_ROT_ANGLE_SRC_ROT90                                   0x4
+#define   GCREG_BLOCK4_ROT_ANGLE_SRC_ROT180                                  0x5
+#define   GCREG_BLOCK4_ROT_ANGLE_SRC_ROT270                                  0x6
+
+#define GCREG_BLOCK4_ROT_ANGLE_DST                                         5 : 3
+#define GCREG_BLOCK4_ROT_ANGLE_DST_End                                         5
+#define GCREG_BLOCK4_ROT_ANGLE_DST_Start                                       3
+#define GCREG_BLOCK4_ROT_ANGLE_DST_Type                                      U03
+#define   GCREG_BLOCK4_ROT_ANGLE_DST_ROT0                                    0x0
+#define   GCREG_BLOCK4_ROT_ANGLE_DST_FLIP_X                                  0x1
+#define   GCREG_BLOCK4_ROT_ANGLE_DST_FLIP_Y                                  0x2
+#define   GCREG_BLOCK4_ROT_ANGLE_DST_ROT90                                   0x4
+#define   GCREG_BLOCK4_ROT_ANGLE_DST_ROT180                                  0x5
+#define   GCREG_BLOCK4_ROT_ANGLE_DST_ROT270                                  0x6
+
+#define GCREG_BLOCK4_ROT_ANGLE_MASK_SRC                                    8 : 8
+#define GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_End                                    8
+#define GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_Start                                  8
+#define GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_Type                                 U01
+#define   GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_ENABLED                            0x0
+#define   GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_MASKED                             0x1
+
+#define GCREG_BLOCK4_ROT_ANGLE_MASK_DST                                    9 : 9
+#define GCREG_BLOCK4_ROT_ANGLE_MASK_DST_End                                    9
+#define GCREG_BLOCK4_ROT_ANGLE_MASK_DST_Start                                  9
+#define GCREG_BLOCK4_ROT_ANGLE_MASK_DST_Type                                 U01
+#define   GCREG_BLOCK4_ROT_ANGLE_MASK_DST_ENABLED                            0x0
+#define   GCREG_BLOCK4_ROT_ANGLE_MASK_DST_MASKED                             0x1
+
+#define GCREG_BLOCK4_ROT_ANGLE_SRC_MIRROR                                13 : 12
+#define GCREG_BLOCK4_ROT_ANGLE_SRC_MIRROR_End                                 13
+#define GCREG_BLOCK4_ROT_ANGLE_SRC_MIRROR_Start                               12
+#define GCREG_BLOCK4_ROT_ANGLE_SRC_MIRROR_Type                               U02
+#define   GCREG_BLOCK4_ROT_ANGLE_SRC_MIRROR_NONE                             0x0
+#define   GCREG_BLOCK4_ROT_ANGLE_SRC_MIRROR_MIRROR_X                         0x1
+#define   GCREG_BLOCK4_ROT_ANGLE_SRC_MIRROR_MIRROR_Y                         0x2
+#define   GCREG_BLOCK4_ROT_ANGLE_SRC_MIRROR_MIRROR_XY                        0x3
+
+#define GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_MIRROR                           15 : 15
+#define GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_MIRROR_End                            15
+#define GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_MIRROR_Start                          15
+#define GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_MIRROR_Type                          U01
+#define   GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_MIRROR_ENABLED                     0x0
+#define   GCREG_BLOCK4_ROT_ANGLE_MASK_SRC_MIRROR_MASKED                      0x1
+
+#define GCREG_BLOCK4_ROT_ANGLE_DST_MIRROR                                17 : 16
+#define GCREG_BLOCK4_ROT_ANGLE_DST_MIRROR_End                                 17
+#define GCREG_BLOCK4_ROT_ANGLE_DST_MIRROR_Start                               16
+#define GCREG_BLOCK4_ROT_ANGLE_DST_MIRROR_Type                               U02
+#define   GCREG_BLOCK4_ROT_ANGLE_DST_MIRROR_NONE                             0x0
+#define   GCREG_BLOCK4_ROT_ANGLE_DST_MIRROR_MIRROR_X                         0x1
+#define   GCREG_BLOCK4_ROT_ANGLE_DST_MIRROR_MIRROR_Y                         0x2
+#define   GCREG_BLOCK4_ROT_ANGLE_DST_MIRROR_MIRROR_XY                        0x3
+
+#define GCREG_BLOCK4_ROT_ANGLE_MASK_DST_MIRROR                           19 : 19
+#define GCREG_BLOCK4_ROT_ANGLE_MASK_DST_MIRROR_End                            19
+#define GCREG_BLOCK4_ROT_ANGLE_MASK_DST_MIRROR_Start                          19
+#define GCREG_BLOCK4_ROT_ANGLE_MASK_DST_MIRROR_Type                          U01
+#define   GCREG_BLOCK4_ROT_ANGLE_MASK_DST_MIRROR_ENABLED                     0x0
+#define   GCREG_BLOCK4_ROT_ANGLE_MASK_DST_MIRROR_MASKED                      0x1
+
+/*******************************************************************************
+** State gcregBlock4GlobalSrcColor
+*/
+
+/* Defines the global source color and alpha values. */
+
+#define gcregBlock4GlobalSrcColorRegAddrs                                 0x4A40
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_MSB                                     15
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_LSB                                      2
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_BLK                                      0
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_Count                                    4
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_FieldMask                       0xFFFFFFFF
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_ReadMask                        0xFFFFFFFF
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_WriteMask                       0xFFFFFFFF
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_ResetValue                      0x00000000
+
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_ALPHA                              31 : 24
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_ALPHA_End                               31
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_ALPHA_Start                             24
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_ALPHA_Type                             U08
+
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_RED                                23 : 16
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_RED_End                                 23
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_RED_Start                               16
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_RED_Type                               U08
+
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_GREEN                               15 : 8
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_GREEN_End                               15
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_GREEN_Start                              8
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_GREEN_Type                             U08
+
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_BLUE                                 7 : 0
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_BLUE_End                                 7
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_BLUE_Start                               0
+#define GCREG_BLOCK4_GLOBAL_SRC_COLOR_BLUE_Type                              U08
+
+/*******************************************************************************
+** State gcregBlock4GlobalDestColor
+*/
+
+/* Defines the global destination color and alpha values. */
+
+#define gcregBlock4GlobalDestColorRegAddrs                                0x4A44
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_MSB                                    15
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_LSB                                     2
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_BLK                                     0
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_Count                                   4
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_FieldMask                      0xFFFFFFFF
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_ReadMask                       0xFFFFFFFF
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_WriteMask                      0xFFFFFFFF
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_ResetValue                     0x00000000
+
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_ALPHA                             31 : 24
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_ALPHA_End                              31
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_ALPHA_Start                            24
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_ALPHA_Type                            U08
+
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_RED                               23 : 16
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_RED_End                                23
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_RED_Start                              16
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_RED_Type                              U08
+
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_GREEN                              15 : 8
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_GREEN_End                              15
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_GREEN_Start                             8
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_GREEN_Type                            U08
+
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_BLUE                                7 : 0
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_BLUE_End                                7
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_BLUE_Start                              0
+#define GCREG_BLOCK4_GLOBAL_DEST_COLOR_BLUE_Type                             U08
+
+/*******************************************************************************
+** State gcregBlock4ColorMultiplyModes
+*/
+
+/* Color modes to multiply Source or Destination pixel color by alpha
+** channel. Alpha can be from global color source or current pixel.
+*/
+
+#define gcregBlock4ColorMultiplyModesRegAddrs                             0x4A48
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_MSB                                 15
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_LSB                                  2
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_BLK                                  0
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_Count                                4
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_FieldMask                   0x00100311
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_ReadMask                    0x00100311
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_WriteMask                   0x00100311
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_ResetValue                  0x00000000
+
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY                  0 : 0
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_End                  0
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_Start                0
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_Type               U01
+#define   GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_DISABLE          0x0
+#define   GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_ENABLE           0x1
+
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY                  4 : 4
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_End                  4
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_Start                4
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_Type               U01
+#define   GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_DISABLE          0x0
+#define   GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_ENABLE           0x1
+
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY           9 : 8
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_End           9
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_Start         8
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_Type        U02
+#define   GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_DISABLE   0x0
+#define   GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_ALPHA     0x1
+#define   GCREG_BLOCK4_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_COLOR     0x2
+
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY                 20 : 20
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_End                  20
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_Start                20
+#define GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_Type                U01
+#define   GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_DISABLE           0x0
+#define   GCREG_BLOCK4_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_ENABLE            0x1
+
+/*******************************************************************************
+** State gcregBlock4Transparency
+*/
+
+#define gcregBlock4TransparencyRegAddrs                                   0x4A4C
+#define GCREG_BLOCK4_TRANSPARENCY_MSB                                         15
+#define GCREG_BLOCK4_TRANSPARENCY_LSB                                          2
+#define GCREG_BLOCK4_TRANSPARENCY_BLK                                          0
+#define GCREG_BLOCK4_TRANSPARENCY_Count                                        4
+#define GCREG_BLOCK4_TRANSPARENCY_FieldMask                           0xB3331333
+#define GCREG_BLOCK4_TRANSPARENCY_ReadMask                            0xB3331333
+#define GCREG_BLOCK4_TRANSPARENCY_WriteMask                           0xB3331333
+#define GCREG_BLOCK4_TRANSPARENCY_ResetValue                          0x00000000
+
+/* Source transparency mode. */
+#define GCREG_BLOCK4_TRANSPARENCY_SOURCE                                   1 : 0
+#define GCREG_BLOCK4_TRANSPARENCY_SOURCE_End                                   1
+#define GCREG_BLOCK4_TRANSPARENCY_SOURCE_Start                                 0
+#define GCREG_BLOCK4_TRANSPARENCY_SOURCE_Type                                U02
+#define   GCREG_BLOCK4_TRANSPARENCY_SOURCE_OPAQUE                            0x0
+#define   GCREG_BLOCK4_TRANSPARENCY_SOURCE_MASK                              0x1
+#define   GCREG_BLOCK4_TRANSPARENCY_SOURCE_KEY                               0x2
+
+/* Pattern transparency mode. KEY transparency mode is reserved. */
+#define GCREG_BLOCK4_TRANSPARENCY_PATTERN                                  5 : 4
+#define GCREG_BLOCK4_TRANSPARENCY_PATTERN_End                                  5
+#define GCREG_BLOCK4_TRANSPARENCY_PATTERN_Start                                4
+#define GCREG_BLOCK4_TRANSPARENCY_PATTERN_Type                               U02
+#define   GCREG_BLOCK4_TRANSPARENCY_PATTERN_OPAQUE                           0x0
+#define   GCREG_BLOCK4_TRANSPARENCY_PATTERN_MASK                             0x1
+#define   GCREG_BLOCK4_TRANSPARENCY_PATTERN_KEY                              0x2
+
+/* Destination transparency mode. MASK transparency mode is reserved. */
+#define GCREG_BLOCK4_TRANSPARENCY_DESTINATION                              9 : 8
+#define GCREG_BLOCK4_TRANSPARENCY_DESTINATION_End                              9
+#define GCREG_BLOCK4_TRANSPARENCY_DESTINATION_Start                            8
+#define GCREG_BLOCK4_TRANSPARENCY_DESTINATION_Type                           U02
+#define   GCREG_BLOCK4_TRANSPARENCY_DESTINATION_OPAQUE                       0x0
+#define   GCREG_BLOCK4_TRANSPARENCY_DESTINATION_MASK                         0x1
+#define   GCREG_BLOCK4_TRANSPARENCY_DESTINATION_KEY                          0x2
+
+/* Mask field for Source/Pattern/Destination fields. */
+#define GCREG_BLOCK4_TRANSPARENCY_MASK_TRANSPARENCY                      12 : 12
+#define GCREG_BLOCK4_TRANSPARENCY_MASK_TRANSPARENCY_End                       12
+#define GCREG_BLOCK4_TRANSPARENCY_MASK_TRANSPARENCY_Start                     12
+#define GCREG_BLOCK4_TRANSPARENCY_MASK_TRANSPARENCY_Type                     U01
+#define   GCREG_BLOCK4_TRANSPARENCY_MASK_TRANSPARENCY_ENABLED                0x0
+#define   GCREG_BLOCK4_TRANSPARENCY_MASK_TRANSPARENCY_MASKED                 0x1
+
+/* Source usage override. */
+#define GCREG_BLOCK4_TRANSPARENCY_USE_SRC_OVERRIDE                       17 : 16
+#define GCREG_BLOCK4_TRANSPARENCY_USE_SRC_OVERRIDE_End                        17
+#define GCREG_BLOCK4_TRANSPARENCY_USE_SRC_OVERRIDE_Start                      16
+#define GCREG_BLOCK4_TRANSPARENCY_USE_SRC_OVERRIDE_Type                      U02
+#define   GCREG_BLOCK4_TRANSPARENCY_USE_SRC_OVERRIDE_DEFAULT                 0x0
+#define   GCREG_BLOCK4_TRANSPARENCY_USE_SRC_OVERRIDE_USE_ENABLE              0x1
+#define   GCREG_BLOCK4_TRANSPARENCY_USE_SRC_OVERRIDE_USE_DISABLE             0x2
+
+/* Pattern usage override. */
+#define GCREG_BLOCK4_TRANSPARENCY_USE_PAT_OVERRIDE                       21 : 20
+#define GCREG_BLOCK4_TRANSPARENCY_USE_PAT_OVERRIDE_End                        21
+#define GCREG_BLOCK4_TRANSPARENCY_USE_PAT_OVERRIDE_Start                      20
+#define GCREG_BLOCK4_TRANSPARENCY_USE_PAT_OVERRIDE_Type                      U02
+#define   GCREG_BLOCK4_TRANSPARENCY_USE_PAT_OVERRIDE_DEFAULT                 0x0
+#define   GCREG_BLOCK4_TRANSPARENCY_USE_PAT_OVERRIDE_USE_ENABLE              0x1
+#define   GCREG_BLOCK4_TRANSPARENCY_USE_PAT_OVERRIDE_USE_DISABLE             0x2
+
+/* Destination usage override. */
+#define GCREG_BLOCK4_TRANSPARENCY_USE_DST_OVERRIDE                       25 : 24
+#define GCREG_BLOCK4_TRANSPARENCY_USE_DST_OVERRIDE_End                        25
+#define GCREG_BLOCK4_TRANSPARENCY_USE_DST_OVERRIDE_Start                      24
+#define GCREG_BLOCK4_TRANSPARENCY_USE_DST_OVERRIDE_Type                      U02
+#define   GCREG_BLOCK4_TRANSPARENCY_USE_DST_OVERRIDE_DEFAULT                 0x0
+#define   GCREG_BLOCK4_TRANSPARENCY_USE_DST_OVERRIDE_USE_ENABLE              0x1
+#define   GCREG_BLOCK4_TRANSPARENCY_USE_DST_OVERRIDE_USE_DISABLE             0x2
+
+/* 2D resource usage override mask field. */
+#define GCREG_BLOCK4_TRANSPARENCY_MASK_RESOURCE_OVERRIDE                 28 : 28
+#define GCREG_BLOCK4_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_End                  28
+#define GCREG_BLOCK4_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_Start                28
+#define GCREG_BLOCK4_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_Type                U01
+#define   GCREG_BLOCK4_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_ENABLED           0x0
+#define   GCREG_BLOCK4_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_MASKED            0x1
+
+/* DFB Color Key. */
+#define GCREG_BLOCK4_TRANSPARENCY_DFB_COLOR_KEY                          29 : 29
+#define GCREG_BLOCK4_TRANSPARENCY_DFB_COLOR_KEY_End                           29
+#define GCREG_BLOCK4_TRANSPARENCY_DFB_COLOR_KEY_Start                         29
+#define GCREG_BLOCK4_TRANSPARENCY_DFB_COLOR_KEY_Type                         U01
+#define   GCREG_BLOCK4_TRANSPARENCY_DFB_COLOR_KEY_DISABLED                   0x0
+#define   GCREG_BLOCK4_TRANSPARENCY_DFB_COLOR_KEY_ENABLED                    0x1
+
+#define GCREG_BLOCK4_TRANSPARENCY_MASK_DFB_COLOR_KEY                     31 : 31
+#define GCREG_BLOCK4_TRANSPARENCY_MASK_DFB_COLOR_KEY_End                      31
+#define GCREG_BLOCK4_TRANSPARENCY_MASK_DFB_COLOR_KEY_Start                    31
+#define GCREG_BLOCK4_TRANSPARENCY_MASK_DFB_COLOR_KEY_Type                    U01
+#define   GCREG_BLOCK4_TRANSPARENCY_MASK_DFB_COLOR_KEY_ENABLED               0x0
+#define   GCREG_BLOCK4_TRANSPARENCY_MASK_DFB_COLOR_KEY_MASKED                0x1
+
+/*******************************************************************************
+** State gcregBlock4Control
+*/
+
+/* General purpose control register. */
+
+#define gcregBlock4ControlRegAddrs                                        0x4A50
+#define GCREG_BLOCK4_CONTROL_MSB                                              15
+#define GCREG_BLOCK4_CONTROL_LSB                                               2
+#define GCREG_BLOCK4_CONTROL_BLK                                               0
+#define GCREG_BLOCK4_CONTROL_Count                                             4
+#define GCREG_BLOCK4_CONTROL_FieldMask                                0x00000999
+#define GCREG_BLOCK4_CONTROL_ReadMask                                 0x00000999
+#define GCREG_BLOCK4_CONTROL_WriteMask                                0x00000999
+#define GCREG_BLOCK4_CONTROL_ResetValue                               0x00000000
+
+#define GCREG_BLOCK4_CONTROL_YUV                                           0 : 0
+#define GCREG_BLOCK4_CONTROL_YUV_End                                           0
+#define GCREG_BLOCK4_CONTROL_YUV_Start                                         0
+#define GCREG_BLOCK4_CONTROL_YUV_Type                                        U01
+#define   GCREG_BLOCK4_CONTROL_YUV_601                                       0x0
+#define   GCREG_BLOCK4_CONTROL_YUV_709                                       0x1
+
+#define GCREG_BLOCK4_CONTROL_MASK_YUV                                      3 : 3
+#define GCREG_BLOCK4_CONTROL_MASK_YUV_End                                      3
+#define GCREG_BLOCK4_CONTROL_MASK_YUV_Start                                    3
+#define GCREG_BLOCK4_CONTROL_MASK_YUV_Type                                   U01
+#define   GCREG_BLOCK4_CONTROL_MASK_YUV_ENABLED                              0x0
+#define   GCREG_BLOCK4_CONTROL_MASK_YUV_MASKED                               0x1
+
+#define GCREG_BLOCK4_CONTROL_UV_SWIZZLE                                    4 : 4
+#define GCREG_BLOCK4_CONTROL_UV_SWIZZLE_End                                    4
+#define GCREG_BLOCK4_CONTROL_UV_SWIZZLE_Start                                  4
+#define GCREG_BLOCK4_CONTROL_UV_SWIZZLE_Type                                 U01
+#define   GCREG_BLOCK4_CONTROL_UV_SWIZZLE_UV                                 0x0
+#define   GCREG_BLOCK4_CONTROL_UV_SWIZZLE_VU                                 0x1
+
+#define GCREG_BLOCK4_CONTROL_MASK_UV_SWIZZLE                               7 : 7
+#define GCREG_BLOCK4_CONTROL_MASK_UV_SWIZZLE_End                               7
+#define GCREG_BLOCK4_CONTROL_MASK_UV_SWIZZLE_Start                             7
+#define GCREG_BLOCK4_CONTROL_MASK_UV_SWIZZLE_Type                            U01
+#define   GCREG_BLOCK4_CONTROL_MASK_UV_SWIZZLE_ENABLED                       0x0
+#define   GCREG_BLOCK4_CONTROL_MASK_UV_SWIZZLE_MASKED                        0x1
+
+/* YUV to RGB convert enable */
+#define GCREG_BLOCK4_CONTROL_YUVRGB                                        8 : 8
+#define GCREG_BLOCK4_CONTROL_YUVRGB_End                                        8
+#define GCREG_BLOCK4_CONTROL_YUVRGB_Start                                      8
+#define GCREG_BLOCK4_CONTROL_YUVRGB_Type                                     U01
+#define   GCREG_BLOCK4_CONTROL_YUVRGB_DISABLED                               0x0
+#define   GCREG_BLOCK4_CONTROL_YUVRGB_ENABLED                                0x1
+
+#define GCREG_BLOCK4_CONTROL_MASK_YUVRGB                                 11 : 11
+#define GCREG_BLOCK4_CONTROL_MASK_YUVRGB_End                                  11
+#define GCREG_BLOCK4_CONTROL_MASK_YUVRGB_Start                                11
+#define GCREG_BLOCK4_CONTROL_MASK_YUVRGB_Type                                U01
+#define   GCREG_BLOCK4_CONTROL_MASK_YUVRGB_ENABLED                           0x0
+#define   GCREG_BLOCK4_CONTROL_MASK_YUVRGB_MASKED                            0x1
+
+/*******************************************************************************
+** State gcregBlock4SrcColorKeyHigh
+*/
+
+/* Defines the source transparency color in source format. */
+
+#define gcregBlock4SrcColorKeyHighRegAddrs                                0x4A54
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_MSB                                   15
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_LSB                                    2
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_BLK                                    0
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_Count                                  4
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_FieldMask                     0xFFFFFFFF
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_ReadMask                      0xFFFFFFFF
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_WriteMask                     0xFFFFFFFF
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_ResetValue                    0x00000000
+
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_ALPHA                            31 : 24
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_ALPHA_End                             31
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_ALPHA_Start                           24
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_ALPHA_Type                           U08
+
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_RED                              23 : 16
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_RED_End                               23
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_RED_Start                             16
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_RED_Type                             U08
+
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_GREEN                             15 : 8
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_GREEN_End                             15
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_GREEN_Start                            8
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_GREEN_Type                           U08
+
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_BLUE                               7 : 0
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_BLUE_End                               7
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_BLUE_Start                             0
+#define GCREG_BLOCK4_SRC_COLOR_KEY_HIGH_BLUE_Type                            U08
+
+/*******************************************************************************
+** State gcregBlock4SrcExConfig
+*/
+
+#define gcregBlock4SrcExConfigRegAddrs                                    0x4A58
+#define GCREG_BLOCK4_SRC_EX_CONFIG_MSB                                        15
+#define GCREG_BLOCK4_SRC_EX_CONFIG_LSB                                         2
+#define GCREG_BLOCK4_SRC_EX_CONFIG_BLK                                         0
+#define GCREG_BLOCK4_SRC_EX_CONFIG_Count                                       4
+#define GCREG_BLOCK4_SRC_EX_CONFIG_FieldMask                          0x00000109
+#define GCREG_BLOCK4_SRC_EX_CONFIG_ReadMask                           0x00000109
+#define GCREG_BLOCK4_SRC_EX_CONFIG_WriteMask                          0x00000109
+#define GCREG_BLOCK4_SRC_EX_CONFIG_ResetValue                         0x00000000
+
+/* Source multi tiled address computation control. */
+#define GCREG_BLOCK4_SRC_EX_CONFIG_MULTI_TILED                             0 : 0
+#define GCREG_BLOCK4_SRC_EX_CONFIG_MULTI_TILED_End                             0
+#define GCREG_BLOCK4_SRC_EX_CONFIG_MULTI_TILED_Start                           0
+#define GCREG_BLOCK4_SRC_EX_CONFIG_MULTI_TILED_Type                          U01
+#define   GCREG_BLOCK4_SRC_EX_CONFIG_MULTI_TILED_DISABLED                    0x0
+#define   GCREG_BLOCK4_SRC_EX_CONFIG_MULTI_TILED_ENABLED                     0x1
+
+/* Source super tiled address computation control. */
+#define GCREG_BLOCK4_SRC_EX_CONFIG_SUPER_TILED                             3 : 3
+#define GCREG_BLOCK4_SRC_EX_CONFIG_SUPER_TILED_End                             3
+#define GCREG_BLOCK4_SRC_EX_CONFIG_SUPER_TILED_Start                           3
+#define GCREG_BLOCK4_SRC_EX_CONFIG_SUPER_TILED_Type                          U01
+#define   GCREG_BLOCK4_SRC_EX_CONFIG_SUPER_TILED_DISABLED                    0x0
+#define   GCREG_BLOCK4_SRC_EX_CONFIG_SUPER_TILED_ENABLED                     0x1
+
+/* Source super tiled address computation control. */
+#define GCREG_BLOCK4_SRC_EX_CONFIG_MINOR_TILED                             8 : 8
+#define GCREG_BLOCK4_SRC_EX_CONFIG_MINOR_TILED_End                             8
+#define GCREG_BLOCK4_SRC_EX_CONFIG_MINOR_TILED_Start                           8
+#define GCREG_BLOCK4_SRC_EX_CONFIG_MINOR_TILED_Type                          U01
+#define   GCREG_BLOCK4_SRC_EX_CONFIG_MINOR_TILED_DISABLED                    0x0
+#define   GCREG_BLOCK4_SRC_EX_CONFIG_MINOR_TILED_ENABLED                     0x1
+
+/*******************************************************************************
+** State gcregBlock4SrcExAddress
+*/
+
+/* 32-bit aligned base address of the source extra surface. */
+
+#define gcregBlock4SrcExAddressRegAddrs                                   0x4A5C
+#define GCREG_BLOCK4_SRC_EX_ADDRESS_MSB                                       15
+#define GCREG_BLOCK4_SRC_EX_ADDRESS_LSB                                        2
+#define GCREG_BLOCK4_SRC_EX_ADDRESS_BLK                                        0
+#define GCREG_BLOCK4_SRC_EX_ADDRESS_Count                                      4
+#define GCREG_BLOCK4_SRC_EX_ADDRESS_FieldMask                         0xFFFFFFFF
+#define GCREG_BLOCK4_SRC_EX_ADDRESS_ReadMask                          0xFFFFFFFC
+#define GCREG_BLOCK4_SRC_EX_ADDRESS_WriteMask                         0xFFFFFFFC
+#define GCREG_BLOCK4_SRC_EX_ADDRESS_ResetValue                        0x00000000
+
+#define GCREG_BLOCK4_SRC_EX_ADDRESS_ADDRESS                               31 : 0
+#define GCREG_BLOCK4_SRC_EX_ADDRESS_ADDRESS_End                               30
+#define GCREG_BLOCK4_SRC_EX_ADDRESS_ADDRESS_Start                              0
+#define GCREG_BLOCK4_SRC_EX_ADDRESS_ADDRESS_Type                             U31
+
+/*******************************************************************************
+** State gcregBlock8SrcAddressEx
+*/
+
+/* 32-bit aligned base address of the source surface. */
+
+#define gcregBlock8SrcAddressRegAddrs                                     0x4A80
+#define GCREG_BLOCK8_SRC_ADDRESS_MSB                                          15
+#define GCREG_BLOCK8_SRC_ADDRESS_LSB                                           3
+#define GCREG_BLOCK8_SRC_ADDRESS_BLK                                           0
+#define GCREG_BLOCK8_SRC_ADDRESS_Count                                         8
+#define GCREG_BLOCK8_SRC_ADDRESS_FieldMask                            0xFFFFFFFF
+#define GCREG_BLOCK8_SRC_ADDRESS_ReadMask                             0xFFFFFFFC
+#define GCREG_BLOCK8_SRC_ADDRESS_WriteMask                            0xFFFFFFFC
+#define GCREG_BLOCK8_SRC_ADDRESS_ResetValue                           0x00000000
+
+#define GCREG_BLOCK8_SRC_ADDRESS_ADDRESS                                  31 : 0
+#define GCREG_BLOCK8_SRC_ADDRESS_ADDRESS_End                                  30
+#define GCREG_BLOCK8_SRC_ADDRESS_ADDRESS_Start                                 0
+#define GCREG_BLOCK8_SRC_ADDRESS_ADDRESS_Type                                U31
+
+/*******************************************************************************
+** State gcregBlock8SrcStride
+*/
+
+/* Stride of the source surface in bytes. To calculate the stride multiply
+** the surface width in pixels by the number of  bytes per pixel.
+*/
+
+#define gcregBlock8SrcStrideRegAddrs                                      0x4A88
+#define GCREG_BLOCK8_SRC_STRIDE_MSB                                           15
+#define GCREG_BLOCK8_SRC_STRIDE_LSB                                            3
+#define GCREG_BLOCK8_SRC_STRIDE_BLK                                            0
+#define GCREG_BLOCK8_SRC_STRIDE_Count                                          8
+#define GCREG_BLOCK8_SRC_STRIDE_FieldMask                             0x0003FFFF
+#define GCREG_BLOCK8_SRC_STRIDE_ReadMask                              0x0003FFFC
+#define GCREG_BLOCK8_SRC_STRIDE_WriteMask                             0x0003FFFC
+#define GCREG_BLOCK8_SRC_STRIDE_ResetValue                            0x00000000
+
+#define GCREG_BLOCK8_SRC_STRIDE_STRIDE                                    17 : 0
+#define GCREG_BLOCK8_SRC_STRIDE_STRIDE_End                                    17
+#define GCREG_BLOCK8_SRC_STRIDE_STRIDE_Start                                   0
+#define GCREG_BLOCK8_SRC_STRIDE_STRIDE_Type                                  U18
+
+/*******************************************************************************
+** State gcregBlock8SrcRotationConfig
+*/
+
+/* 90 degree rotation configuration for the source surface. Width field
+** specifies the width of the surface in pixels.
+*/
+
+#define gcregBlock8SrcRotationConfigRegAddrs                              0x4A90
+#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_MSB                                  15
+#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_LSB                                   3
+#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_BLK                                   0
+#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_Count                                 8
+#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_FieldMask                    0x0001FFFF
+#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_ReadMask                     0x0001FFFF
+#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_WriteMask                    0x0001FFFF
+#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_ResetValue                   0x00000000
+
+#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_WIDTH                            15 : 0
+#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_WIDTH_End                            15
+#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_WIDTH_Start                           0
+#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_WIDTH_Type                          U16
+
+#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_ROTATION                        16 : 16
+#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_ROTATION_End                         16
+#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_ROTATION_Start                       16
+#define GCREG_BLOCK8_SRC_ROTATION_CONFIG_ROTATION_Type                       U01
+#define   GCREG_BLOCK8_SRC_ROTATION_CONFIG_ROTATION_NORMAL                   0x0
+#define   GCREG_BLOCK8_SRC_ROTATION_CONFIG_ROTATION_ROTATED                  0x1
+
+/*******************************************************************************
+** State gcregBlock8SrcConfig
+*/
+
+/* Source surface configuration register. */
+
+#define gcregBlock8SrcConfigRegAddrs                                      0x4A98
+#define GCREG_BLOCK8_SRC_CONFIG_MSB                                           15
+#define GCREG_BLOCK8_SRC_CONFIG_LSB                                            3
+#define GCREG_BLOCK8_SRC_CONFIG_BLK                                            0
+#define GCREG_BLOCK8_SRC_CONFIG_Count                                          8
+#define GCREG_BLOCK8_SRC_CONFIG_FieldMask                             0xDF30B1C0
+#define GCREG_BLOCK8_SRC_CONFIG_ReadMask                              0xDF30B1C0
+#define GCREG_BLOCK8_SRC_CONFIG_WriteMask                             0xDF30B1C0
+#define GCREG_BLOCK8_SRC_CONFIG_ResetValue                            0x00000000
+
+/* Control source endianess. */
+#define GCREG_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL                           31 : 30
+#define GCREG_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL_End                            31
+#define GCREG_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL_Start                          30
+#define GCREG_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL_Type                          U02
+#define   GCREG_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL_NO_SWAP                     0x0
+#define   GCREG_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL_SWAP_WORD                   0x1
+#define   GCREG_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL_SWAP_DWORD                  0x2
+
+/* Defines the pixel format of the source surface. */
+#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT                            28 : 24
+#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_End                             28
+#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_Start                           24
+#define GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_Type                           U05
+#define   GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_X4R4G4B4                    0x00
+#define   GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_A4R4G4B4                    0x01
+#define   GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_X1R5G5B5                    0x02
+#define   GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_A1R5G5B5                    0x03
+#define   GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_R5G6B5                      0x04
+#define   GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_X8R8G8B8                    0x05
+#define   GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_A8R8G8B8                    0x06
+#define   GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_YUY2                        0x07
+#define   GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_UYVY                        0x08
+#define   GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_INDEX8                      0x09
+#define   GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_MONOCHROME                  0x0A
+#define   GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_YV12                        0x0F
+#define   GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_A8                          0x10
+#define   GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_NV12                        0x11
+#define   GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_NV16                        0x12
+#define   GCREG_BLOCK8_SRC_CONFIG_SOURCE_FORMAT_RG16                        0x13
+
+/* Color channel swizzles. */
+#define GCREG_BLOCK8_SRC_CONFIG_SWIZZLE                                  21 : 20
+#define GCREG_BLOCK8_SRC_CONFIG_SWIZZLE_End                                   21
+#define GCREG_BLOCK8_SRC_CONFIG_SWIZZLE_Start                                 20
+#define GCREG_BLOCK8_SRC_CONFIG_SWIZZLE_Type                                 U02
+#define   GCREG_BLOCK8_SRC_CONFIG_SWIZZLE_ARGB                               0x0
+#define   GCREG_BLOCK8_SRC_CONFIG_SWIZZLE_RGBA                               0x1
+#define   GCREG_BLOCK8_SRC_CONFIG_SWIZZLE_ABGR                               0x2
+#define   GCREG_BLOCK8_SRC_CONFIG_SWIZZLE_BGRA                               0x3
+
+/* Mono expansion: if 0, transparency color will be 0, otherwise transparency **
+** color will be 1.                                                           */
+#define GCREG_BLOCK8_SRC_CONFIG_MONO_TRANSPARENCY                        15 : 15
+#define GCREG_BLOCK8_SRC_CONFIG_MONO_TRANSPARENCY_End                         15
+#define GCREG_BLOCK8_SRC_CONFIG_MONO_TRANSPARENCY_Start                       15
+#define GCREG_BLOCK8_SRC_CONFIG_MONO_TRANSPARENCY_Type                       U01
+#define   GCREG_BLOCK8_SRC_CONFIG_MONO_TRANSPARENCY_BACKGROUND               0x0
+#define   GCREG_BLOCK8_SRC_CONFIG_MONO_TRANSPARENCY_FOREGROUND               0x1
+
+/* Mono expansion or masked blit: stream packing in pixels. Determines how    **
+** many horizontal pixels are there per each 32-bit chunk. For example, if    **
+** set to Packed8, each 32-bit chunk is 8-pixel wide, which also means that   **
+** it defines 4 vertical lines of pixels.                                     */
+#define GCREG_BLOCK8_SRC_CONFIG_PACK                                     13 : 12
+#define GCREG_BLOCK8_SRC_CONFIG_PACK_End                                      13
+#define GCREG_BLOCK8_SRC_CONFIG_PACK_Start                                    12
+#define GCREG_BLOCK8_SRC_CONFIG_PACK_Type                                    U02
+#define   GCREG_BLOCK8_SRC_CONFIG_PACK_PACKED8                               0x0
+#define   GCREG_BLOCK8_SRC_CONFIG_PACK_PACKED16                              0x1
+#define   GCREG_BLOCK8_SRC_CONFIG_PACK_PACKED32                              0x2
+#define   GCREG_BLOCK8_SRC_CONFIG_PACK_UNPACKED                              0x3
+
+/* Source data location: set to STREAM for mono expansion blits or masked     **
+** blits. For mono expansion blits the complete bitmap comes from the command **
+** stream. For masked blits the source data comes from the memory and the     **
+** mask from the command stream.                                              */
+#define GCREG_BLOCK8_SRC_CONFIG_LOCATION                                   8 : 8
+#define GCREG_BLOCK8_SRC_CONFIG_LOCATION_End                                   8
+#define GCREG_BLOCK8_SRC_CONFIG_LOCATION_Start                                 8
+#define GCREG_BLOCK8_SRC_CONFIG_LOCATION_Type                                U01
+#define   GCREG_BLOCK8_SRC_CONFIG_LOCATION_MEMORY                            0x0
+#define   GCREG_BLOCK8_SRC_CONFIG_LOCATION_STREAM                            0x1
+
+/* Source linear/tiled address computation control. */
+#define GCREG_BLOCK8_SRC_CONFIG_TILED                                      7 : 7
+#define GCREG_BLOCK8_SRC_CONFIG_TILED_End                                      7
+#define GCREG_BLOCK8_SRC_CONFIG_TILED_Start                                    7
+#define GCREG_BLOCK8_SRC_CONFIG_TILED_Type                                   U01
+#define   GCREG_BLOCK8_SRC_CONFIG_TILED_DISABLED                             0x0
+#define   GCREG_BLOCK8_SRC_CONFIG_TILED_ENABLED                              0x1
+
+/* If set to ABSOLUTE, the source coordinates are treated as absolute         **
+** coordinates inside the source surface. If set to RELATIVE, the source      **
+** coordinates are treated as the offsets from the destination coordinates    **
+** with the source size equal to the size of the destination.                 */
+#define GCREG_BLOCK8_SRC_CONFIG_SRC_RELATIVE                               6 : 6
+#define GCREG_BLOCK8_SRC_CONFIG_SRC_RELATIVE_End                               6
+#define GCREG_BLOCK8_SRC_CONFIG_SRC_RELATIVE_Start                             6
+#define GCREG_BLOCK8_SRC_CONFIG_SRC_RELATIVE_Type                            U01
+#define   GCREG_BLOCK8_SRC_CONFIG_SRC_RELATIVE_ABSOLUTE                      0x0
+#define   GCREG_BLOCK8_SRC_CONFIG_SRC_RELATIVE_RELATIVE                      0x1
+
+/*******************************************************************************
+** State gcregBlock8SrcOrigin
+*/
+
+/* Absolute or relative (see SRC_RELATIVE field of gcregBlock8SrcConfig
+** register) X and Y coordinates in pixels of the top left corner of the
+** source rectangle within the source surface.
+*/
+
+#define gcregBlock8SrcOriginRegAddrs                                      0x4AA0
+#define GCREG_BLOCK8_SRC_ORIGIN_MSB                                           15
+#define GCREG_BLOCK8_SRC_ORIGIN_LSB                                            3
+#define GCREG_BLOCK8_SRC_ORIGIN_BLK                                            0
+#define GCREG_BLOCK8_SRC_ORIGIN_Count                                          8
+#define GCREG_BLOCK8_SRC_ORIGIN_FieldMask                             0xFFFFFFFF
+#define GCREG_BLOCK8_SRC_ORIGIN_ReadMask                              0xFFFFFFFF
+#define GCREG_BLOCK8_SRC_ORIGIN_WriteMask                             0xFFFFFFFF
+#define GCREG_BLOCK8_SRC_ORIGIN_ResetValue                            0x00000000
+
+#define GCREG_BLOCK8_SRC_ORIGIN_Y                                        31 : 16
+#define GCREG_BLOCK8_SRC_ORIGIN_Y_End                                         31
+#define GCREG_BLOCK8_SRC_ORIGIN_Y_Start                                       16
+#define GCREG_BLOCK8_SRC_ORIGIN_Y_Type                                       U16
+
+#define GCREG_BLOCK8_SRC_ORIGIN_X                                         15 : 0
+#define GCREG_BLOCK8_SRC_ORIGIN_X_End                                         15
+#define GCREG_BLOCK8_SRC_ORIGIN_X_Start                                        0
+#define GCREG_BLOCK8_SRC_ORIGIN_X_Type                                       U16
+
+/*******************************************************************************
+** State gcregBlock8SrcSize
+*/
+
+/* Width and height of the source rectangle in pixels. If the source is
+** relative (see SRC_RELATIVE field of gcregBlock8SrcConfig register) or a
+** regular bitblt is being performed without stretching, this register is
+** ignored and the source size is assumed to be the same as the destination.
+*/
+
+#define gcregBlock8SrcSizeRegAddrs                                        0x4AA8
+#define GCREG_BLOCK8_SRC_SIZE_MSB                                             15
+#define GCREG_BLOCK8_SRC_SIZE_LSB                                              3
+#define GCREG_BLOCK8_SRC_SIZE_BLK                                              0
+#define GCREG_BLOCK8_SRC_SIZE_Count                                            8
+#define GCREG_BLOCK8_SRC_SIZE_FieldMask                               0xFFFFFFFF
+#define GCREG_BLOCK8_SRC_SIZE_ReadMask                                0xFFFFFFFF
+#define GCREG_BLOCK8_SRC_SIZE_WriteMask                               0xFFFFFFFF
+#define GCREG_BLOCK8_SRC_SIZE_ResetValue                              0x00000000
+
+#define GCREG_BLOCK8_SRC_SIZE_Y                                          31 : 16
+#define GCREG_BLOCK8_SRC_SIZE_Y_End                                           31
+#define GCREG_BLOCK8_SRC_SIZE_Y_Start                                         16
+#define GCREG_BLOCK8_SRC_SIZE_Y_Type                                         U16
+
+#define GCREG_BLOCK8_SRC_SIZE_X                                           15 : 0
+#define GCREG_BLOCK8_SRC_SIZE_X_End                                           15
+#define GCREG_BLOCK8_SRC_SIZE_X_Start                                          0
+#define GCREG_BLOCK8_SRC_SIZE_X_Type                                         U16
+
+/*******************************************************************************
+** State gcregBlock8SrcColorBg
+*/
+
+/* Select the color where source becomes transparent. It must be programmed
+** in A8R8G8B8 format.
+*/
+
+#define gcregBlock8SrcColorBgRegAddrs                                     0x4AB0
+#define GCREG_BLOCK8_SRC_COLOR_BG_MSB                                         15
+#define GCREG_BLOCK8_SRC_COLOR_BG_LSB                                          3
+#define GCREG_BLOCK8_SRC_COLOR_BG_BLK                                          0
+#define GCREG_BLOCK8_SRC_COLOR_BG_Count                                        8
+#define GCREG_BLOCK8_SRC_COLOR_BG_FieldMask                           0xFFFFFFFF
+#define GCREG_BLOCK8_SRC_COLOR_BG_ReadMask                            0xFFFFFFFF
+#define GCREG_BLOCK8_SRC_COLOR_BG_WriteMask                           0xFFFFFFFF
+#define GCREG_BLOCK8_SRC_COLOR_BG_ResetValue                          0x00000000
+
+#define GCREG_BLOCK8_SRC_COLOR_BG_ALPHA                                  31 : 24
+#define GCREG_BLOCK8_SRC_COLOR_BG_ALPHA_End                                   31
+#define GCREG_BLOCK8_SRC_COLOR_BG_ALPHA_Start                                 24
+#define GCREG_BLOCK8_SRC_COLOR_BG_ALPHA_Type                                 U08
+
+#define GCREG_BLOCK8_SRC_COLOR_BG_RED                                    23 : 16
+#define GCREG_BLOCK8_SRC_COLOR_BG_RED_End                                     23
+#define GCREG_BLOCK8_SRC_COLOR_BG_RED_Start                                   16
+#define GCREG_BLOCK8_SRC_COLOR_BG_RED_Type                                   U08
+
+#define GCREG_BLOCK8_SRC_COLOR_BG_GREEN                                   15 : 8
+#define GCREG_BLOCK8_SRC_COLOR_BG_GREEN_End                                   15
+#define GCREG_BLOCK8_SRC_COLOR_BG_GREEN_Start                                  8
+#define GCREG_BLOCK8_SRC_COLOR_BG_GREEN_Type                                 U08
+
+#define GCREG_BLOCK8_SRC_COLOR_BG_BLUE                                     7 : 0
+#define GCREG_BLOCK8_SRC_COLOR_BG_BLUE_End                                     7
+#define GCREG_BLOCK8_SRC_COLOR_BG_BLUE_Start                                   0
+#define GCREG_BLOCK8_SRC_COLOR_BG_BLUE_Type                                  U08
+
+/*******************************************************************************
+** State gcregBlock8Rop
+*/
+
+/* Raster operation foreground and background codes. Even though ROP is not
+** used in CLEAR, HOR_FILTER_BLT, VER_FILTER_BLT and alpha-eanbled BIT_BLTs,
+** ROP code still has to be programmed, because the engine makes the decision
+** whether source, destination and pattern are involved in the current
+** operation and the correct decision is essential for the engine to complete
+** the operation as expected.
+*/
+
+#define gcregBlock8RopRegAddrs                                            0x4AB8
+#define GCREG_BLOCK8_ROP_MSB                                                  15
+#define GCREG_BLOCK8_ROP_LSB                                                   3
+#define GCREG_BLOCK8_ROP_BLK                                                   0
+#define GCREG_BLOCK8_ROP_Count                                                 8
+#define GCREG_BLOCK8_ROP_FieldMask                                    0x0030FFFF
+#define GCREG_BLOCK8_ROP_ReadMask                                     0x0030FFFF
+#define GCREG_BLOCK8_ROP_WriteMask                                    0x0030FFFF
+#define GCREG_BLOCK8_ROP_ResetValue                                   0x00000000
+
+/* ROP type: ROP2, ROP3 or ROP4 */
+#define GCREG_BLOCK8_ROP_TYPE                                            21 : 20
+#define GCREG_BLOCK8_ROP_TYPE_End                                             21
+#define GCREG_BLOCK8_ROP_TYPE_Start                                           20
+#define GCREG_BLOCK8_ROP_TYPE_Type                                           U02
+#define   GCREG_BLOCK8_ROP_TYPE_ROP2_PATTERN                                 0x0
+#define   GCREG_BLOCK8_ROP_TYPE_ROP2_SOURCE                                  0x1
+#define   GCREG_BLOCK8_ROP_TYPE_ROP3                                         0x2
+#define   GCREG_BLOCK8_ROP_TYPE_ROP4                                         0x3
+
+/* Background ROP code is used for transparent pixels. */
+#define GCREG_BLOCK8_ROP_ROP_BG                                           15 : 8
+#define GCREG_BLOCK8_ROP_ROP_BG_End                                           15
+#define GCREG_BLOCK8_ROP_ROP_BG_Start                                          8
+#define GCREG_BLOCK8_ROP_ROP_BG_Type                                         U08
+
+/* Background ROP code is used for opaque pixels. */
+#define GCREG_BLOCK8_ROP_ROP_FG                                            7 : 0
+#define GCREG_BLOCK8_ROP_ROP_FG_End                                            7
+#define GCREG_BLOCK8_ROP_ROP_FG_Start                                          0
+#define GCREG_BLOCK8_ROP_ROP_FG_Type                                         U08
+
+/*******************************************************************************
+** State gcregBlock8AlphaControl
+*/
+
+#define gcregBlock8AlphaControlRegAddrs                                   0x4AC0
+#define GCREG_BLOCK8_ALPHA_CONTROL_MSB                                        15
+#define GCREG_BLOCK8_ALPHA_CONTROL_LSB                                         3
+#define GCREG_BLOCK8_ALPHA_CONTROL_BLK                                         0
+#define GCREG_BLOCK8_ALPHA_CONTROL_Count                                       8
+#define GCREG_BLOCK8_ALPHA_CONTROL_FieldMask                          0x00000001
+#define GCREG_BLOCK8_ALPHA_CONTROL_ReadMask                           0x00000001
+#define GCREG_BLOCK8_ALPHA_CONTROL_WriteMask                          0x00000001
+#define GCREG_BLOCK8_ALPHA_CONTROL_ResetValue                         0x00000000
+
+#define GCREG_BLOCK8_ALPHA_CONTROL_ENABLE                                  0 : 0
+#define GCREG_BLOCK8_ALPHA_CONTROL_ENABLE_End                                  0
+#define GCREG_BLOCK8_ALPHA_CONTROL_ENABLE_Start                                0
+#define GCREG_BLOCK8_ALPHA_CONTROL_ENABLE_Type                               U01
+#define   GCREG_BLOCK8_ALPHA_CONTROL_ENABLE_OFF                              0x0
+#define   GCREG_BLOCK8_ALPHA_CONTROL_ENABLE_ON                               0x1
+
+/*******************************************************************************
+** State gcregBlock8AlphaModes
+*/
+
+#define gcregBlock8AlphaModesRegAddrs                                     0x4AC8
+#define GCREG_BLOCK8_ALPHA_MODES_MSB                                          15
+#define GCREG_BLOCK8_ALPHA_MODES_LSB                                           3
+#define GCREG_BLOCK8_ALPHA_MODES_BLK                                           0
+#define GCREG_BLOCK8_ALPHA_MODES_Count                                         8
+#define GCREG_BLOCK8_ALPHA_MODES_FieldMask                            0xFF003311
+#define GCREG_BLOCK8_ALPHA_MODES_ReadMask                             0xFF003311
+#define GCREG_BLOCK8_ALPHA_MODES_WriteMask                            0xFF003311
+#define GCREG_BLOCK8_ALPHA_MODES_ResetValue                           0x00000000
+
+#define GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_MODE                            0 : 0
+#define GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_MODE_End                            0
+#define GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_MODE_Start                          0
+#define GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_MODE_Type                         U01
+#define   GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_MODE_NORMAL                     0x0
+#define   GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_MODE_INVERSED                   0x1
+
+#define GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_MODE                            4 : 4
+#define GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_MODE_End                            4
+#define GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_MODE_Start                          4
+#define GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_MODE_Type                         U01
+#define   GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_MODE_NORMAL                     0x0
+#define   GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_MODE_INVERSED                   0x1
+
+#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE                     9 : 8
+#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_End                     9
+#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_Start                   8
+#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_Type                  U02
+#define   GCREG_BLOCK8_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_NORMAL              0x0
+#define   GCREG_BLOCK8_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_GLOBAL              0x1
+#define   GCREG_BLOCK8_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_SCALED              0x2
+
+#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE                   13 : 12
+#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_End                    13
+#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_Start                  12
+#define GCREG_BLOCK8_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_Type                  U02
+#define   GCREG_BLOCK8_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_NORMAL              0x0
+#define   GCREG_BLOCK8_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_GLOBAL              0x1
+#define   GCREG_BLOCK8_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_SCALED              0x2
+
+#define GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE                       26 : 24
+#define GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_End                        26
+#define GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_Start                      24
+#define GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_Type                      U03
+#define   GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_ZERO                    0x0
+#define   GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_ONE                     0x1
+#define   GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_NORMAL                  0x2
+#define   GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_INVERSED                0x3
+#define   GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_COLOR                   0x4
+#define   GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_COLOR_INVERSED          0x5
+#define   GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_SATURATED_ALPHA         0x6
+#define   GCREG_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE_SATURATED_DEST_ALPHA    0x7
+
+/* Src Blending factor is calculate from Src alpha. */
+#define GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_FACTOR                        27 : 27
+#define GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_FACTOR_End                         27
+#define GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_FACTOR_Start                       27
+#define GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_FACTOR_Type                       U01
+#define   GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_FACTOR_DISABLED                 0x0
+#define   GCREG_BLOCK8_ALPHA_MODES_SRC_ALPHA_FACTOR_ENABLED                  0x1
+
+#define GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE                       30 : 28
+#define GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_End                        30
+#define GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_Start                      28
+#define GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_Type                      U03
+#define   GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_ZERO                    0x0
+#define   GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_ONE                     0x1
+#define   GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_NORMAL                  0x2
+#define   GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_INVERSED                0x3
+#define   GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_COLOR                   0x4
+#define   GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_COLOR_INVERSED          0x5
+#define   GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_SATURATED_ALPHA         0x6
+#define   GCREG_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE_SATURATED_DEST_ALPHA    0x7
+
+/* Dst Blending factor is calculate from Dst alpha. */
+#define GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_FACTOR                        31 : 31
+#define GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_FACTOR_End                         31
+#define GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_FACTOR_Start                       31
+#define GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_FACTOR_Type                       U01
+#define   GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_FACTOR_DISABLED                 0x0
+#define   GCREG_BLOCK8_ALPHA_MODES_DST_ALPHA_FACTOR_ENABLED                  0x1
+
+/*******************************************************************************
+** State gcregBlock8AddressU
+*/
+
+/* 32-bit aligned base address of the source U plane. */
+
+#define gcregBlock8AddressURegAddrs                                       0x4AD0
+#define GCREG_BLOCK8_ADDRESS_U_MSB                                            15
+#define GCREG_BLOCK8_ADDRESS_U_LSB                                             3
+#define GCREG_BLOCK8_ADDRESS_U_BLK                                             0
+#define GCREG_BLOCK8_ADDRESS_U_Count                                           8
+#define GCREG_BLOCK8_ADDRESS_U_FieldMask                              0xFFFFFFFF
+#define GCREG_BLOCK8_ADDRESS_U_ReadMask                               0xFFFFFFFC
+#define GCREG_BLOCK8_ADDRESS_U_WriteMask                              0xFFFFFFFC
+#define GCREG_BLOCK8_ADDRESS_U_ResetValue                             0x00000000
+
+#define GCREG_BLOCK8_ADDRESS_U_ADDRESS                                    31 : 0
+#define GCREG_BLOCK8_ADDRESS_U_ADDRESS_End                                    30
+#define GCREG_BLOCK8_ADDRESS_U_ADDRESS_Start                                   0
+#define GCREG_BLOCK8_ADDRESS_U_ADDRESS_Type                                  U31
+
+/*******************************************************************************
+** State gcregBlock8StrideU
+*/
+
+/* Stride of the source U plane in bytes. */
+
+#define gcregBlock8StrideURegAddrs                                        0x4AD8
+#define GCREG_BLOCK8_STRIDE_U_MSB                                             15
+#define GCREG_BLOCK8_STRIDE_U_LSB                                              3
+#define GCREG_BLOCK8_STRIDE_U_BLK                                              0
+#define GCREG_BLOCK8_STRIDE_U_Count                                            8
+#define GCREG_BLOCK8_STRIDE_U_FieldMask                               0x0003FFFF
+#define GCREG_BLOCK8_STRIDE_U_ReadMask                                0x0003FFFC
+#define GCREG_BLOCK8_STRIDE_U_WriteMask                               0x0003FFFC
+#define GCREG_BLOCK8_STRIDE_U_ResetValue                              0x00000000
+
+#define GCREG_BLOCK8_STRIDE_U_STRIDE                                      17 : 0
+#define GCREG_BLOCK8_STRIDE_U_STRIDE_End                                      17
+#define GCREG_BLOCK8_STRIDE_U_STRIDE_Start                                     0
+#define GCREG_BLOCK8_STRIDE_U_STRIDE_Type                                    U18
+
+/*******************************************************************************
+** State gcregBlock8AddressV
+*/
+
+/* 32-bit aligned base address of the source V plane. */
+
+#define gcregBlock8AddressVRegAddrs                                       0x4AE0
+#define GCREG_BLOCK8_ADDRESS_V_MSB                                            15
+#define GCREG_BLOCK8_ADDRESS_V_LSB                                             3
+#define GCREG_BLOCK8_ADDRESS_V_BLK                                             0
+#define GCREG_BLOCK8_ADDRESS_V_Count                                           8
+#define GCREG_BLOCK8_ADDRESS_V_FieldMask                              0xFFFFFFFF
+#define GCREG_BLOCK8_ADDRESS_V_ReadMask                               0xFFFFFFFC
+#define GCREG_BLOCK8_ADDRESS_V_WriteMask                              0xFFFFFFFC
+#define GCREG_BLOCK8_ADDRESS_V_ResetValue                             0x00000000
+
+#define GCREG_BLOCK8_ADDRESS_V_ADDRESS                                    31 : 0
+#define GCREG_BLOCK8_ADDRESS_V_ADDRESS_End                                    30
+#define GCREG_BLOCK8_ADDRESS_V_ADDRESS_Start                                   0
+#define GCREG_BLOCK8_ADDRESS_V_ADDRESS_Type                                  U31
+
+/*******************************************************************************
+** State gcregBlock8StrideV
+*/
+
+/* Stride of the source V plane in bytes. */
+
+#define gcregBlock8StrideVRegAddrs                                        0x4AE8
+#define GCREG_BLOCK8_STRIDE_V_MSB                                             15
+#define GCREG_BLOCK8_STRIDE_V_LSB                                              3
+#define GCREG_BLOCK8_STRIDE_V_BLK                                              0
+#define GCREG_BLOCK8_STRIDE_V_Count                                            8
+#define GCREG_BLOCK8_STRIDE_V_FieldMask                               0x0003FFFF
+#define GCREG_BLOCK8_STRIDE_V_ReadMask                                0x0003FFFC
+#define GCREG_BLOCK8_STRIDE_V_WriteMask                               0x0003FFFC
+#define GCREG_BLOCK8_STRIDE_V_ResetValue                              0x00000000
+
+#define GCREG_BLOCK8_STRIDE_V_STRIDE                                      17 : 0
+#define GCREG_BLOCK8_STRIDE_V_STRIDE_End                                      17
+#define GCREG_BLOCK8_STRIDE_V_STRIDE_Start                                     0
+#define GCREG_BLOCK8_STRIDE_V_STRIDE_Type                                    U18
+
+/*******************************************************************************
+** State gcregBlock8SrcRotationHeight
+*/
+
+/* 180/270 degree rotation configuration for the Source surface. Height field
+** specifies the height of the surface in pixels.
+*/
+
+#define gcregBlock8SrcRotationHeightRegAddrs                              0x4AF0
+#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_MSB                                  15
+#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_LSB                                   3
+#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_BLK                                   0
+#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_Count                                 8
+#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_FieldMask                    0x0000FFFF
+#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_ReadMask                     0x0000FFFF
+#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_WriteMask                    0x0000FFFF
+#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_ResetValue                   0x00000000
+
+#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_HEIGHT                           15 : 0
+#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_HEIGHT_End                           15
+#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_HEIGHT_Start                          0
+#define GCREG_BLOCK8_SRC_ROTATION_HEIGHT_HEIGHT_Type                         U16
+
+/*******************************************************************************
+** State gcregBlock8RotAngle
+*/
+
+/* 0/90/180/270 degree rotation configuration for the Source surface. Height
+** field specifies the height of the surface in pixels.
+*/
+
+#define gcregBlock8RotAngleRegAddrs                                       0x4AF8
+#define GCREG_BLOCK8_ROT_ANGLE_MSB                                            15
+#define GCREG_BLOCK8_ROT_ANGLE_LSB                                             3
+#define GCREG_BLOCK8_ROT_ANGLE_BLK                                             0
+#define GCREG_BLOCK8_ROT_ANGLE_Count                                           8
+#define GCREG_BLOCK8_ROT_ANGLE_FieldMask                              0x000BB33F
+#define GCREG_BLOCK8_ROT_ANGLE_ReadMask                               0x000BB33F
+#define GCREG_BLOCK8_ROT_ANGLE_WriteMask                              0x000BB33F
+#define GCREG_BLOCK8_ROT_ANGLE_ResetValue                             0x00000000
+
+#define GCREG_BLOCK8_ROT_ANGLE_SRC                                         2 : 0
+#define GCREG_BLOCK8_ROT_ANGLE_SRC_End                                         2
+#define GCREG_BLOCK8_ROT_ANGLE_SRC_Start                                       0
+#define GCREG_BLOCK8_ROT_ANGLE_SRC_Type                                      U03
+#define   GCREG_BLOCK8_ROT_ANGLE_SRC_ROT0                                    0x0
+#define   GCREG_BLOCK8_ROT_ANGLE_SRC_FLIP_X                                  0x1
+#define   GCREG_BLOCK8_ROT_ANGLE_SRC_FLIP_Y                                  0x2
+#define   GCREG_BLOCK8_ROT_ANGLE_SRC_ROT90                                   0x4
+#define   GCREG_BLOCK8_ROT_ANGLE_SRC_ROT180                                  0x5
+#define   GCREG_BLOCK8_ROT_ANGLE_SRC_ROT270                                  0x6
+
+#define GCREG_BLOCK8_ROT_ANGLE_DST                                         5 : 3
+#define GCREG_BLOCK8_ROT_ANGLE_DST_End                                         5
+#define GCREG_BLOCK8_ROT_ANGLE_DST_Start                                       3
+#define GCREG_BLOCK8_ROT_ANGLE_DST_Type                                      U03
+#define   GCREG_BLOCK8_ROT_ANGLE_DST_ROT0                                    0x0
+#define   GCREG_BLOCK8_ROT_ANGLE_DST_FLIP_X                                  0x1
+#define   GCREG_BLOCK8_ROT_ANGLE_DST_FLIP_Y                                  0x2
+#define   GCREG_BLOCK8_ROT_ANGLE_DST_ROT90                                   0x4
+#define   GCREG_BLOCK8_ROT_ANGLE_DST_ROT180                                  0x5
+#define   GCREG_BLOCK8_ROT_ANGLE_DST_ROT270                                  0x6
+
+#define GCREG_BLOCK8_ROT_ANGLE_MASK_SRC                                    8 : 8
+#define GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_End                                    8
+#define GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_Start                                  8
+#define GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_Type                                 U01
+#define   GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_ENABLED                            0x0
+#define   GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_MASKED                             0x1
+
+#define GCREG_BLOCK8_ROT_ANGLE_MASK_DST                                    9 : 9
+#define GCREG_BLOCK8_ROT_ANGLE_MASK_DST_End                                    9
+#define GCREG_BLOCK8_ROT_ANGLE_MASK_DST_Start                                  9
+#define GCREG_BLOCK8_ROT_ANGLE_MASK_DST_Type                                 U01
+#define   GCREG_BLOCK8_ROT_ANGLE_MASK_DST_ENABLED                            0x0
+#define   GCREG_BLOCK8_ROT_ANGLE_MASK_DST_MASKED                             0x1
+
+#define GCREG_BLOCK8_ROT_ANGLE_SRC_MIRROR                                13 : 12
+#define GCREG_BLOCK8_ROT_ANGLE_SRC_MIRROR_End                                 13
+#define GCREG_BLOCK8_ROT_ANGLE_SRC_MIRROR_Start                               12
+#define GCREG_BLOCK8_ROT_ANGLE_SRC_MIRROR_Type                               U02
+#define   GCREG_BLOCK8_ROT_ANGLE_SRC_MIRROR_NONE                             0x0
+#define   GCREG_BLOCK8_ROT_ANGLE_SRC_MIRROR_MIRROR_X                         0x1
+#define   GCREG_BLOCK8_ROT_ANGLE_SRC_MIRROR_MIRROR_Y                         0x2
+#define   GCREG_BLOCK8_ROT_ANGLE_SRC_MIRROR_MIRROR_XY                        0x3
+
+#define GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_MIRROR                           15 : 15
+#define GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_MIRROR_End                            15
+#define GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_MIRROR_Start                          15
+#define GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_MIRROR_Type                          U01
+#define   GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_MIRROR_ENABLED                     0x0
+#define   GCREG_BLOCK8_ROT_ANGLE_MASK_SRC_MIRROR_MASKED                      0x1
+
+#define GCREG_BLOCK8_ROT_ANGLE_DST_MIRROR                                17 : 16
+#define GCREG_BLOCK8_ROT_ANGLE_DST_MIRROR_End                                 17
+#define GCREG_BLOCK8_ROT_ANGLE_DST_MIRROR_Start                               16
+#define GCREG_BLOCK8_ROT_ANGLE_DST_MIRROR_Type                               U02
+#define   GCREG_BLOCK8_ROT_ANGLE_DST_MIRROR_NONE                             0x0
+#define   GCREG_BLOCK8_ROT_ANGLE_DST_MIRROR_MIRROR_X                         0x1
+#define   GCREG_BLOCK8_ROT_ANGLE_DST_MIRROR_MIRROR_Y                         0x2
+#define   GCREG_BLOCK8_ROT_ANGLE_DST_MIRROR_MIRROR_XY                        0x3
+
+#define GCREG_BLOCK8_ROT_ANGLE_MASK_DST_MIRROR                           19 : 19
+#define GCREG_BLOCK8_ROT_ANGLE_MASK_DST_MIRROR_End                            19
+#define GCREG_BLOCK8_ROT_ANGLE_MASK_DST_MIRROR_Start                          19
+#define GCREG_BLOCK8_ROT_ANGLE_MASK_DST_MIRROR_Type                          U01
+#define   GCREG_BLOCK8_ROT_ANGLE_MASK_DST_MIRROR_ENABLED                     0x0
+#define   GCREG_BLOCK8_ROT_ANGLE_MASK_DST_MIRROR_MASKED                      0x1
+
+/*******************************************************************************
+** State gcregBlock8GlobalSrcColor
+*/
+
+/* Defines the global source color and alpha values. */
+
+#define gcregBlock8GlobalSrcColorRegAddrs                                 0x4B00
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_MSB                                     15
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_LSB                                      3
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_BLK                                      0
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_Count                                    8
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_FieldMask                       0xFFFFFFFF
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_ReadMask                        0xFFFFFFFF
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_WriteMask                       0xFFFFFFFF
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_ResetValue                      0x00000000
+
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_ALPHA                              31 : 24
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_ALPHA_End                               31
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_ALPHA_Start                             24
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_ALPHA_Type                             U08
+
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_RED                                23 : 16
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_RED_End                                 23
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_RED_Start                               16
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_RED_Type                               U08
+
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_GREEN                               15 : 8
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_GREEN_End                               15
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_GREEN_Start                              8
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_GREEN_Type                             U08
+
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_BLUE                                 7 : 0
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_BLUE_End                                 7
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_BLUE_Start                               0
+#define GCREG_BLOCK8_GLOBAL_SRC_COLOR_BLUE_Type                              U08
+
+/*******************************************************************************
+** State gcregBlock8GlobalDestColor
+*/
+
+/* Defines the global destination color and alpha values. */
+
+#define gcregBlock8GlobalDestColorRegAddrs                                0x4B08
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_MSB                                    15
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_LSB                                     3
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_BLK                                     0
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_Count                                   8
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_FieldMask                      0xFFFFFFFF
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_ReadMask                       0xFFFFFFFF
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_WriteMask                      0xFFFFFFFF
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_ResetValue                     0x00000000
+
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_ALPHA                             31 : 24
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_ALPHA_End                              31
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_ALPHA_Start                            24
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_ALPHA_Type                            U08
+
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_RED                               23 : 16
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_RED_End                                23
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_RED_Start                              16
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_RED_Type                              U08
+
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_GREEN                              15 : 8
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_GREEN_End                              15
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_GREEN_Start                             8
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_GREEN_Type                            U08
+
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_BLUE                                7 : 0
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_BLUE_End                                7
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_BLUE_Start                              0
+#define GCREG_BLOCK8_GLOBAL_DEST_COLOR_BLUE_Type                             U08
+
+/*******************************************************************************
+** State gcregBlock8ColorMultiplyModes
+*/
+
+/* Color modes to multiply Source or Destination pixel color by alpha
+** channel. Alpha can be from global color source or current pixel.
+*/
+
+#define gcregBlock8ColorMultiplyModesRegAddrs                             0x4B10
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_MSB                                 15
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_LSB                                  3
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_BLK                                  0
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_Count                                8
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_FieldMask                   0x00100311
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_ReadMask                    0x00100311
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_WriteMask                   0x00100311
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_ResetValue                  0x00000000
+
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY                  0 : 0
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_End                  0
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_Start                0
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_Type               U01
+#define   GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_DISABLE          0x0
+#define   GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_ENABLE           0x1
+
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY                  4 : 4
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_End                  4
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_Start                4
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_Type               U01
+#define   GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_DISABLE          0x0
+#define   GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_ENABLE           0x1
+
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY           9 : 8
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_End           9
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_Start         8
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_Type        U02
+#define   GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_DISABLE   0x0
+#define   GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_ALPHA     0x1
+#define   GCREG_BLOCK8_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_COLOR     0x2
+
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY                 20 : 20
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_End                  20
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_Start                20
+#define GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_Type                U01
+#define   GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_DISABLE           0x0
+#define   GCREG_BLOCK8_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_ENABLE            0x1
+
+/*******************************************************************************
+** State gcregBlock8Transparency
+*/
+
+#define gcregBlock8TransparencyRegAddrs                                   0x4B18
+#define GCREG_BLOCK8_TRANSPARENCY_MSB                                         15
+#define GCREG_BLOCK8_TRANSPARENCY_LSB                                          3
+#define GCREG_BLOCK8_TRANSPARENCY_BLK                                          0
+#define GCREG_BLOCK8_TRANSPARENCY_Count                                        8
+#define GCREG_BLOCK8_TRANSPARENCY_FieldMask                           0xB3331333
+#define GCREG_BLOCK8_TRANSPARENCY_ReadMask                            0xB3331333
+#define GCREG_BLOCK8_TRANSPARENCY_WriteMask                           0xB3331333
+#define GCREG_BLOCK8_TRANSPARENCY_ResetValue                          0x00000000
+
+/* Source transparency mode. */
+#define GCREG_BLOCK8_TRANSPARENCY_SOURCE                                   1 : 0
+#define GCREG_BLOCK8_TRANSPARENCY_SOURCE_End                                   1
+#define GCREG_BLOCK8_TRANSPARENCY_SOURCE_Start                                 0
+#define GCREG_BLOCK8_TRANSPARENCY_SOURCE_Type                                U02
+#define   GCREG_BLOCK8_TRANSPARENCY_SOURCE_OPAQUE                            0x0
+#define   GCREG_BLOCK8_TRANSPARENCY_SOURCE_MASK                              0x1
+#define   GCREG_BLOCK8_TRANSPARENCY_SOURCE_KEY                               0x2
+
+/* Pattern transparency mode. KEY transparency mode is reserved. */
+#define GCREG_BLOCK8_TRANSPARENCY_PATTERN                                  5 : 4
+#define GCREG_BLOCK8_TRANSPARENCY_PATTERN_End                                  5
+#define GCREG_BLOCK8_TRANSPARENCY_PATTERN_Start                                4
+#define GCREG_BLOCK8_TRANSPARENCY_PATTERN_Type                               U02
+#define   GCREG_BLOCK8_TRANSPARENCY_PATTERN_OPAQUE                           0x0
+#define   GCREG_BLOCK8_TRANSPARENCY_PATTERN_MASK                             0x1
+#define   GCREG_BLOCK8_TRANSPARENCY_PATTERN_KEY                              0x2
+
+/* Destination transparency mode. MASK transparency mode is reserved. */
+#define GCREG_BLOCK8_TRANSPARENCY_DESTINATION                              9 : 8
+#define GCREG_BLOCK8_TRANSPARENCY_DESTINATION_End                              9
+#define GCREG_BLOCK8_TRANSPARENCY_DESTINATION_Start                            8
+#define GCREG_BLOCK8_TRANSPARENCY_DESTINATION_Type                           U02
+#define   GCREG_BLOCK8_TRANSPARENCY_DESTINATION_OPAQUE                       0x0
+#define   GCREG_BLOCK8_TRANSPARENCY_DESTINATION_MASK                         0x1
+#define   GCREG_BLOCK8_TRANSPARENCY_DESTINATION_KEY                          0x2
+
+/* Mask field for Source/Pattern/Destination fields. */
+#define GCREG_BLOCK8_TRANSPARENCY_MASK_TRANSPARENCY                      12 : 12
+#define GCREG_BLOCK8_TRANSPARENCY_MASK_TRANSPARENCY_End                       12
+#define GCREG_BLOCK8_TRANSPARENCY_MASK_TRANSPARENCY_Start                     12
+#define GCREG_BLOCK8_TRANSPARENCY_MASK_TRANSPARENCY_Type                     U01
+#define   GCREG_BLOCK8_TRANSPARENCY_MASK_TRANSPARENCY_ENABLED                0x0
+#define   GCREG_BLOCK8_TRANSPARENCY_MASK_TRANSPARENCY_MASKED                 0x1
+
+/* Source usage override. */
+#define GCREG_BLOCK8_TRANSPARENCY_USE_SRC_OVERRIDE                       17 : 16
+#define GCREG_BLOCK8_TRANSPARENCY_USE_SRC_OVERRIDE_End                        17
+#define GCREG_BLOCK8_TRANSPARENCY_USE_SRC_OVERRIDE_Start                      16
+#define GCREG_BLOCK8_TRANSPARENCY_USE_SRC_OVERRIDE_Type                      U02
+#define   GCREG_BLOCK8_TRANSPARENCY_USE_SRC_OVERRIDE_DEFAULT                 0x0
+#define   GCREG_BLOCK8_TRANSPARENCY_USE_SRC_OVERRIDE_USE_ENABLE              0x1
+#define   GCREG_BLOCK8_TRANSPARENCY_USE_SRC_OVERRIDE_USE_DISABLE             0x2
+
+/* Pattern usage override. */
+#define GCREG_BLOCK8_TRANSPARENCY_USE_PAT_OVERRIDE                       21 : 20
+#define GCREG_BLOCK8_TRANSPARENCY_USE_PAT_OVERRIDE_End                        21
+#define GCREG_BLOCK8_TRANSPARENCY_USE_PAT_OVERRIDE_Start                      20
+#define GCREG_BLOCK8_TRANSPARENCY_USE_PAT_OVERRIDE_Type                      U02
+#define   GCREG_BLOCK8_TRANSPARENCY_USE_PAT_OVERRIDE_DEFAULT                 0x0
+#define   GCREG_BLOCK8_TRANSPARENCY_USE_PAT_OVERRIDE_USE_ENABLE              0x1
+#define   GCREG_BLOCK8_TRANSPARENCY_USE_PAT_OVERRIDE_USE_DISABLE             0x2
+
+/* Destination usage override. */
+#define GCREG_BLOCK8_TRANSPARENCY_USE_DST_OVERRIDE                       25 : 24
+#define GCREG_BLOCK8_TRANSPARENCY_USE_DST_OVERRIDE_End                        25
+#define GCREG_BLOCK8_TRANSPARENCY_USE_DST_OVERRIDE_Start                      24
+#define GCREG_BLOCK8_TRANSPARENCY_USE_DST_OVERRIDE_Type                      U02
+#define   GCREG_BLOCK8_TRANSPARENCY_USE_DST_OVERRIDE_DEFAULT                 0x0
+#define   GCREG_BLOCK8_TRANSPARENCY_USE_DST_OVERRIDE_USE_ENABLE              0x1
+#define   GCREG_BLOCK8_TRANSPARENCY_USE_DST_OVERRIDE_USE_DISABLE             0x2
+
+/* 2D resource usage override mask field. */
+#define GCREG_BLOCK8_TRANSPARENCY_MASK_RESOURCE_OVERRIDE                 28 : 28
+#define GCREG_BLOCK8_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_End                  28
+#define GCREG_BLOCK8_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_Start                28
+#define GCREG_BLOCK8_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_Type                U01
+#define   GCREG_BLOCK8_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_ENABLED           0x0
+#define   GCREG_BLOCK8_TRANSPARENCY_MASK_RESOURCE_OVERRIDE_MASKED            0x1
+
+/* DFB Color Key. */
+#define GCREG_BLOCK8_TRANSPARENCY_DFB_COLOR_KEY                          29 : 29
+#define GCREG_BLOCK8_TRANSPARENCY_DFB_COLOR_KEY_End                           29
+#define GCREG_BLOCK8_TRANSPARENCY_DFB_COLOR_KEY_Start                         29
+#define GCREG_BLOCK8_TRANSPARENCY_DFB_COLOR_KEY_Type                         U01
+#define   GCREG_BLOCK8_TRANSPARENCY_DFB_COLOR_KEY_DISABLED                   0x0
+#define   GCREG_BLOCK8_TRANSPARENCY_DFB_COLOR_KEY_ENABLED                    0x1
+
+#define GCREG_BLOCK8_TRANSPARENCY_MASK_DFB_COLOR_KEY                     31 : 31
+#define GCREG_BLOCK8_TRANSPARENCY_MASK_DFB_COLOR_KEY_End                      31
+#define GCREG_BLOCK8_TRANSPARENCY_MASK_DFB_COLOR_KEY_Start                    31
+#define GCREG_BLOCK8_TRANSPARENCY_MASK_DFB_COLOR_KEY_Type                    U01
+#define   GCREG_BLOCK8_TRANSPARENCY_MASK_DFB_COLOR_KEY_ENABLED               0x0
+#define   GCREG_BLOCK8_TRANSPARENCY_MASK_DFB_COLOR_KEY_MASKED                0x1
+
+/*******************************************************************************
+** State gcregBlock8Control
+*/
+
+/* General purpose control register. */
+
+#define gcregBlock8ControlRegAddrs                                        0x4B20
+#define GCREG_BLOCK8_CONTROL_MSB                                              15
+#define GCREG_BLOCK8_CONTROL_LSB                                               3
+#define GCREG_BLOCK8_CONTROL_BLK                                               0
+#define GCREG_BLOCK8_CONTROL_Count                                             8
+#define GCREG_BLOCK8_CONTROL_FieldMask                                0x00000999
+#define GCREG_BLOCK8_CONTROL_ReadMask                                 0x00000999
+#define GCREG_BLOCK8_CONTROL_WriteMask                                0x00000999
+#define GCREG_BLOCK8_CONTROL_ResetValue                               0x00000000
+
+#define GCREG_BLOCK8_CONTROL_YUV                                           0 : 0
+#define GCREG_BLOCK8_CONTROL_YUV_End                                           0
+#define GCREG_BLOCK8_CONTROL_YUV_Start                                         0
+#define GCREG_BLOCK8_CONTROL_YUV_Type                                        U01
+#define   GCREG_BLOCK8_CONTROL_YUV_601                                       0x0
+#define   GCREG_BLOCK8_CONTROL_YUV_709                                       0x1
+
+#define GCREG_BLOCK8_CONTROL_MASK_YUV                                      3 : 3
+#define GCREG_BLOCK8_CONTROL_MASK_YUV_End                                      3
+#define GCREG_BLOCK8_CONTROL_MASK_YUV_Start                                    3
+#define GCREG_BLOCK8_CONTROL_MASK_YUV_Type                                   U01
+#define   GCREG_BLOCK8_CONTROL_MASK_YUV_ENABLED                              0x0
+#define   GCREG_BLOCK8_CONTROL_MASK_YUV_MASKED                               0x1
+
+#define GCREG_BLOCK8_CONTROL_UV_SWIZZLE                                    4 : 4
+#define GCREG_BLOCK8_CONTROL_UV_SWIZZLE_End                                    4
+#define GCREG_BLOCK8_CONTROL_UV_SWIZZLE_Start                                  4
+#define GCREG_BLOCK8_CONTROL_UV_SWIZZLE_Type                                 U01
+#define   GCREG_BLOCK8_CONTROL_UV_SWIZZLE_UV                                 0x0
+#define   GCREG_BLOCK8_CONTROL_UV_SWIZZLE_VU                                 0x1
+
+#define GCREG_BLOCK8_CONTROL_MASK_UV_SWIZZLE                               7 : 7
+#define GCREG_BLOCK8_CONTROL_MASK_UV_SWIZZLE_End                               7
+#define GCREG_BLOCK8_CONTROL_MASK_UV_SWIZZLE_Start                             7
+#define GCREG_BLOCK8_CONTROL_MASK_UV_SWIZZLE_Type                            U01
+#define   GCREG_BLOCK8_CONTROL_MASK_UV_SWIZZLE_ENABLED                       0x0
+#define   GCREG_BLOCK8_CONTROL_MASK_UV_SWIZZLE_MASKED                        0x1
+
+/* YUV to RGB convert enable */
+#define GCREG_BLOCK8_CONTROL_YUVRGB                                        8 : 8
+#define GCREG_BLOCK8_CONTROL_YUVRGB_End                                        8
+#define GCREG_BLOCK8_CONTROL_YUVRGB_Start                                      8
+#define GCREG_BLOCK8_CONTROL_YUVRGB_Type                                     U01
+#define   GCREG_BLOCK8_CONTROL_YUVRGB_DISABLED                               0x0
+#define   GCREG_BLOCK8_CONTROL_YUVRGB_ENABLED                                0x1
+
+#define GCREG_BLOCK8_CONTROL_MASK_YUVRGB                                 11 : 11
+#define GCREG_BLOCK8_CONTROL_MASK_YUVRGB_End                                  11
+#define GCREG_BLOCK8_CONTROL_MASK_YUVRGB_Start                                11
+#define GCREG_BLOCK8_CONTROL_MASK_YUVRGB_Type                                U01
+#define   GCREG_BLOCK8_CONTROL_MASK_YUVRGB_ENABLED                           0x0
+#define   GCREG_BLOCK8_CONTROL_MASK_YUVRGB_MASKED                            0x1
+
+/*******************************************************************************
+** State gcregBlock8SrcColorKeyHigh
+*/
+
+/* Defines the source transparency color in source format. */
+
+#define gcregBlock8SrcColorKeyHighRegAddrs                                0x4B28
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_MSB                                   15
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_LSB                                    3
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_BLK                                    0
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_Count                                  8
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_FieldMask                     0xFFFFFFFF
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_ReadMask                      0xFFFFFFFF
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_WriteMask                     0xFFFFFFFF
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_ResetValue                    0x00000000
+
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_ALPHA                            31 : 24
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_ALPHA_End                             31
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_ALPHA_Start                           24
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_ALPHA_Type                           U08
+
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_RED                              23 : 16
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_RED_End                               23
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_RED_Start                             16
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_RED_Type                             U08
+
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_GREEN                             15 : 8
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_GREEN_End                             15
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_GREEN_Start                            8
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_GREEN_Type                           U08
+
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_BLUE                               7 : 0
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_BLUE_End                               7
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_BLUE_Start                             0
+#define GCREG_BLOCK8_SRC_COLOR_KEY_HIGH_BLUE_Type                            U08
+
+/*******************************************************************************
+** State gcregBlock8SrcExConfig
+*/
+
+#define gcregBlock8SrcExConfigRegAddrs                                    0x4B30
+#define GCREG_BLOCK8_SRC_EX_CONFIG_MSB                                        15
+#define GCREG_BLOCK8_SRC_EX_CONFIG_LSB                                         3
+#define GCREG_BLOCK8_SRC_EX_CONFIG_BLK                                         0
+#define GCREG_BLOCK8_SRC_EX_CONFIG_Count                                       8
+#define GCREG_BLOCK8_SRC_EX_CONFIG_FieldMask                          0x00000109
+#define GCREG_BLOCK8_SRC_EX_CONFIG_ReadMask                           0x00000109
+#define GCREG_BLOCK8_SRC_EX_CONFIG_WriteMask                          0x00000109
+#define GCREG_BLOCK8_SRC_EX_CONFIG_ResetValue                         0x00000000
+
+/* Source multi tiled address computation control. */
+#define GCREG_BLOCK8_SRC_EX_CONFIG_MULTI_TILED                             0 : 0
+#define GCREG_BLOCK8_SRC_EX_CONFIG_MULTI_TILED_End                             0
+#define GCREG_BLOCK8_SRC_EX_CONFIG_MULTI_TILED_Start                           0
+#define GCREG_BLOCK8_SRC_EX_CONFIG_MULTI_TILED_Type                          U01
+#define   GCREG_BLOCK8_SRC_EX_CONFIG_MULTI_TILED_DISABLED                    0x0
+#define   GCREG_BLOCK8_SRC_EX_CONFIG_MULTI_TILED_ENABLED                     0x1
+
+/* Source super tiled address computation control. */
+#define GCREG_BLOCK8_SRC_EX_CONFIG_SUPER_TILED                             3 : 3
+#define GCREG_BLOCK8_SRC_EX_CONFIG_SUPER_TILED_End                             3
+#define GCREG_BLOCK8_SRC_EX_CONFIG_SUPER_TILED_Start                           3
+#define GCREG_BLOCK8_SRC_EX_CONFIG_SUPER_TILED_Type                          U01
+#define   GCREG_BLOCK8_SRC_EX_CONFIG_SUPER_TILED_DISABLED                    0x0
+#define   GCREG_BLOCK8_SRC_EX_CONFIG_SUPER_TILED_ENABLED                     0x1
+
+/* Source super tiled address computation control. */
+#define GCREG_BLOCK8_SRC_EX_CONFIG_MINOR_TILED                             8 : 8
+#define GCREG_BLOCK8_SRC_EX_CONFIG_MINOR_TILED_End                             8
+#define GCREG_BLOCK8_SRC_EX_CONFIG_MINOR_TILED_Start                           8
+#define GCREG_BLOCK8_SRC_EX_CONFIG_MINOR_TILED_Type                          U01
+#define   GCREG_BLOCK8_SRC_EX_CONFIG_MINOR_TILED_DISABLED                    0x0
+#define   GCREG_BLOCK8_SRC_EX_CONFIG_MINOR_TILED_ENABLED                     0x1
+
+/*******************************************************************************
+** State gcregBlock8SrcExAddress
+*/
+
+/* 32-bit aligned base address of the source extra surface. */
+
+#define gcregBlock8SrcExAddressRegAddrs                                   0x4B38
+#define GCREG_BLOCK8_SRC_EX_ADDRESS_MSB                                       15
+#define GCREG_BLOCK8_SRC_EX_ADDRESS_LSB                                        3
+#define GCREG_BLOCK8_SRC_EX_ADDRESS_BLK                                        0
+#define GCREG_BLOCK8_SRC_EX_ADDRESS_Count                                      8
+#define GCREG_BLOCK8_SRC_EX_ADDRESS_FieldMask                         0xFFFFFFFF
+#define GCREG_BLOCK8_SRC_EX_ADDRESS_ReadMask                          0xFFFFFFFC
+#define GCREG_BLOCK8_SRC_EX_ADDRESS_WriteMask                         0xFFFFFFFC
+#define GCREG_BLOCK8_SRC_EX_ADDRESS_ResetValue                        0x00000000
+
+#define GCREG_BLOCK8_SRC_EX_ADDRESS_ADDRESS                               31 : 0
+#define GCREG_BLOCK8_SRC_EX_ADDRESS_ADDRESS_End                               30
+#define GCREG_BLOCK8_SRC_EX_ADDRESS_ADDRESS_Start                              0
+#define GCREG_BLOCK8_SRC_EX_ADDRESS_ADDRESS_Type                             U31
+
+/*******************************************************************************
+** Generic defines
+*/
+
+#define GCREG_FORMAT_SUB_SAMPLE_MODE_YUV_MODE422                             0x0
+#define GCREG_FORMAT_SUB_SAMPLE_MODE_YUV_MODE420                             0x1
+
+#define GCREG_DE_SWIZZLE_ARGB                                                0x0
+#define GCREG_DE_SWIZZLE_RGBA                                                0x1
+#define GCREG_DE_SWIZZLE_ABGR                                                0x2
+#define GCREG_DE_SWIZZLE_BGRA                                                0x3
+
+#define GCREG_DE_FORMAT_X4R4G4B4                                            0x00
+#define GCREG_DE_FORMAT_A4R4G4B4                                            0x01
+#define GCREG_DE_FORMAT_X1R5G5B5                                            0x02
+#define GCREG_DE_FORMAT_A1R5G5B5                                            0x03
+#define GCREG_DE_FORMAT_R5G6B5                                              0x04
+#define GCREG_DE_FORMAT_X8R8G8B8                                            0x05
+#define GCREG_DE_FORMAT_A8R8G8B8                                            0x06
+#define GCREG_DE_FORMAT_YUY2                                                0x07
+#define GCREG_DE_FORMAT_UYVY                                                0x08
+#define GCREG_DE_FORMAT_INDEX8                                              0x09
+#define GCREG_DE_FORMAT_MONOCHROME                                          0x0A
+#define GCREG_DE_FORMAT_YV12                                                0x0F
+#define GCREG_DE_FORMAT_A8                                                  0x10
+#define GCREG_DE_FORMAT_NV12                                                0x11
+#define GCREG_DE_FORMAT_NV16                                                0x12
+#define GCREG_DE_FORMAT_RG16                                                0x13
+
+/* ~~~~~~~~~~~~~ */
+
+#define GCREG_ALPHA_MODE_NORMAL                                              0x0
+#define GCREG_ALPHA_MODE_INVERSED                                            0x1
+
+#define GCREG_GLOBAL_ALPHA_MODE_NORMAL                                       0x0
+#define GCREG_GLOBAL_ALPHA_MODE_GLOBAL                                       0x1
+#define GCREG_GLOBAL_ALPHA_MODE_SCALED                                       0x2
+
+#define GCREG_COLOR_MODE_NORMAL                                              0x0
+#define GCREG_COLOR_MODE_MULTIPLY                                            0x1
+
+#define GCREG_BLENDING_MODE_ZERO                                             0x0
+#define GCREG_BLENDING_MODE_ONE                                              0x1
+#define GCREG_BLENDING_MODE_NORMAL                                           0x2
+#define GCREG_BLENDING_MODE_INVERSED                                         0x3
+#define GCREG_BLENDING_MODE_COLOR                                            0x4
+#define GCREG_BLENDING_MODE_COLOR_INVERSED                                   0x5
+#define GCREG_BLENDING_MODE_SATURATED_ALPHA                                  0x6
+#define GCREG_BLENDING_MODE_SATURATED_DEST_ALPHA                             0x7
+
+/* ~~~~~~~~~~~~~ */
+
+#define GCREG_FACTOR_INVERSE_DISABLE                                         0x0
+#define GCREG_FACTOR_INVERSE_ENABLE                                          0x1
+
+/* ~~~~~~~~~~~~~ */
+
+#define GCREG_RESOURCE_USAGE_OVERRIDE_DEFAULT                                0x0
+#define GCREG_RESOURCE_USAGE_OVERRIDE_USE_ENABLE                             0x1
+#define GCREG_RESOURCE_USAGE_OVERRIDE_USE_DISABLE                            0x2
+
+/*******************************************************************************
+** Modular operations: pipesel
+*/
+
+static const struct gccmdldstate gcmopipesel_pipesel_ldst =
+	GCLDSTATE(gcregPipeSelectRegAddrs, 1);
+
+struct gcmopipesel {
+	/* gcregPipeSelectRegAddrs */
+	struct gccmdldstate pipesel_ldst;
+
+		/* gcregPipeSelectRegAddrs */
+		union {
+			struct gcregpipeselect reg;
+			unsigned int raw;
+		} pipesel;
+};
+
+/*******************************************************************************
+** Modular operations: signal
+*/
+
+static const struct gccmdldstate gcmosignal_signal_ldst =
+	GCLDSTATE(gcregEventRegAddrs, 1);
+
+struct gcmosignal {
+	/* gcregEventRegAddrs */
+	struct gccmdldstate signal_ldst;
+
+		/* gcregEventRegAddrs */
+		union {
+			struct gcregevent reg;
+			unsigned int raw;
+		} signal;
+};
+
+/*******************************************************************************
+** Modular operations: flush
+*/
+
+static const struct gccmdldstate gcmoflush_flush_ldst =
+	GCLDSTATE(gcregFlushRegAddrs, 1);
+
+struct gcmoflush {
+	/* gcregFlushRegAddrs */
+	struct gccmdldstate flush_ldst;
+
+		/* gcregFlushRegAddrs */
+		union {
+			struct gcregflush reg;
+			unsigned int raw;
+		} flush;
+};
+
+/*******************************************************************************
+** Modular operations: semaphore
+*/
+
+static const struct gccmdldstate gcmosema_sema_ldst =
+	GCLDSTATE(gcregSemaphoreRegAddrs, 1);
+
+struct gcmosema {
+	/* gcregSemaphoreRegAddrs */
+	struct gccmdldstate sema_ldst;
+
+		/* gcregSemaphoreRegAddrs */
+		union {
+			struct gcregsemaphore reg;
+			unsigned int raw;
+		} sema;
+};
+
+/*******************************************************************************
+** Modular operations: mmuinit
+*/
+
+static const struct gccmdldstate gcmommuinit_safe_ldst =
+	GCLDSTATE(gcregMMUSafeAddressRegAddrs, 2);
+
+struct gcmommuinit {
+	/* gcregMMUSafeAddressRegAddrs */
+	struct gccmdldstate safe_ldst;
+
+		/* gcregMMUSafeAddressRegAddrs */
+		unsigned int safe;
+
+		/* gcregMMUConfigurationRegAddrs */
+		unsigned int mtlb;
+
+		/* Alignment filler. */
+		unsigned int _filler;
+};
+
+/*******************************************************************************
+** Modular operations: mmumaster
+*/
+
+static const struct gccmdldstate gcmommumaster_master_ldst =
+	GCLDSTATE(gcregMMUConfigurationRegAddrs, 1);
+
+struct gcmommumaster {
+	/* gcregMMUConfigurationRegAddrs */
+	struct gccmdldstate master_ldst;
+
+		/* gcregMMUConfigurationRegAddrs */
+		unsigned int master;
+};
+
+/*******************************************************************************
+** Modular operations: mmuflush
+*/
+
+static const struct gccmdldstate gcmommuflush_mmuflush_ldst =
+	GCLDSTATE(gcregMMUConfigurationRegAddrs, 1);
+
+struct gcmommuflush {
+	/* PE cache flush. */
+	struct gcmoflush peflush;
+
+	/* Semaphore/stall after PE flush. */
+	struct gcmosema peflushsema;
+	struct gccmdstall peflushstall;
+
+	/* Link to flush FE FIFO. */
+	struct gccmdlink feflush;
+
+	/* MMU flush. */
+	struct gccmdldstate mmuflush_ldst;
+
+		/* gcregMMUConfigurationRegAddrs */
+		union {
+			struct gcregmmuconfiguration reg;
+			unsigned int raw;
+		} mmuflush;
+
+	/* Semaphore/stall after MMU flush. */
+	struct gcmosema mmuflushsema;
+	struct gccmdstall mmuflushstall;
+
+	/* Link to the user buffer. */
+	struct gccmdlink link;
+};
+
+/*******************************************************************************
+** Modular operations: clip
+*/
+
+static const struct gccmdldstate gcmoclip_lt_ldst =
+	GCLDSTATE(gcregClipTopLeftRegAddrs, 2);
+
+struct gcmoclip {
+	/* gcregClipTopLeftRegAddrs */
+	struct gccmdldstate lt_ldst;
+
+		/* gcregClipTopLeftRegAddrs */
+		union {
+			struct gcregcliplt reg;
+			unsigned int raw;
+		} lt;
+
+		/* gcregClipBottomRight */
+		union {
+			struct gcregcliprb reg;
+			unsigned int raw;
+		} rb;
+
+		/* Alignment filler. */
+		unsigned int _filler;
+};
+
+/*******************************************************************************
+** Modular operations: dst
+*/
+
+static const struct gccmdldstate gcmodst_address_ldst =
+	GCLDSTATE(gcregDestAddressRegAddrs, 4);
+
+static const struct gccmdldstate gcmodst_rotationheight_ldst =
+	GCLDSTATE(gcregDstRotationHeightRegAddrs, 1);
+
+struct gcmodst {
+	/* gcregDestAddressRegAddrs */
+	struct gccmdldstate address_ldst;
+
+		/* gcregDestAddressRegAddrs */
+		unsigned int address;
+
+		/* gcregDestStrideRegAddrs */
+		unsigned int stride;
+
+		/* gcregDestRotationConfigRegAddrs */
+		union {
+			struct gcregdstrotationconfig reg;
+			unsigned int raw;
+		} rotation;
+
+		/* gcregDestConfigRegAddrs */
+		union {
+			struct gcregdstconfig reg;
+			unsigned int raw;
+		} config;
+
+		/* Alignment filler. */
+		unsigned int _filler;
+
+	/* gcregDstRotationHeightRegAddrs */
+	struct gccmdldstate rotationheight_ldst;
+
+		/* gcregDstRotationHeightRegAddrs */
+		union {
+			struct gcregdstrotationheight reg;
+			unsigned int raw;
+		} rotationheight;
+
+	struct gcmoclip clip;
+};
+
+/*******************************************************************************
+** Modular operations: src
+*/
+
+static const struct gccmdldstate gcmosrc_address_ldst[4] = {
+	GCLDSTATE(gcregBlock4SrcAddressRegAddrs + 0, 1),
+	GCLDSTATE(gcregBlock4SrcAddressRegAddrs + 1, 1),
+	GCLDSTATE(gcregBlock4SrcAddressRegAddrs + 2, 1),
+	GCLDSTATE(gcregBlock4SrcAddressRegAddrs + 3, 1),
+};
+
+static const struct gccmdldstate gcmosrc_stride_ldst[4] = {
+	GCLDSTATE(gcregBlock4SrcStrideRegAddrs + 0, 1),
+	GCLDSTATE(gcregBlock4SrcStrideRegAddrs + 1, 1),
+	GCLDSTATE(gcregBlock4SrcStrideRegAddrs + 2, 1),
+	GCLDSTATE(gcregBlock4SrcStrideRegAddrs + 3, 1),
+};
+
+static const struct gccmdldstate gcmosrc_rotation_ldst[4] = {
+	GCLDSTATE(gcregBlock4SrcRotationConfigRegAddrs + 0, 1),
+	GCLDSTATE(gcregBlock4SrcRotationConfigRegAddrs + 1, 1),
+	GCLDSTATE(gcregBlock4SrcRotationConfigRegAddrs + 2, 1),
+	GCLDSTATE(gcregBlock4SrcRotationConfigRegAddrs + 3, 1),
+};
+
+static const struct gccmdldstate gcmosrc_config_ldst[4] = {
+	GCLDSTATE(gcregBlock4SrcConfigRegAddrs + 0, 1),
+	GCLDSTATE(gcregBlock4SrcConfigRegAddrs + 1, 1),
+	GCLDSTATE(gcregBlock4SrcConfigRegAddrs + 2, 1),
+	GCLDSTATE(gcregBlock4SrcConfigRegAddrs + 3, 1),
+};
+
+static const struct gccmdldstate gcmosrc_origin_ldst[4] = {
+	GCLDSTATE(gcregBlock4SrcOriginRegAddrs + 0, 1),
+	GCLDSTATE(gcregBlock4SrcOriginRegAddrs + 1, 1),
+	GCLDSTATE(gcregBlock4SrcOriginRegAddrs + 2, 1),
+	GCLDSTATE(gcregBlock4SrcOriginRegAddrs + 3, 1),
+};
+
+static const struct gccmdldstate gcmosrc_size_ldst[4] = {
+	GCLDSTATE(gcregBlock4SrcSizeRegAddrs + 0, 1),
+	GCLDSTATE(gcregBlock4SrcSizeRegAddrs + 1, 1),
+	GCLDSTATE(gcregBlock4SrcSizeRegAddrs + 2, 1),
+	GCLDSTATE(gcregBlock4SrcSizeRegAddrs + 3, 1),
+};
+
+static const struct gccmdldstate gcmosrc_rotationheight_ldst[4] = {
+	GCLDSTATE(gcregBlock4SrcRotationHeightRegAddrs + 0, 1),
+	GCLDSTATE(gcregBlock4SrcRotationHeightRegAddrs + 1, 1),
+	GCLDSTATE(gcregBlock4SrcRotationHeightRegAddrs + 2, 1),
+	GCLDSTATE(gcregBlock4SrcRotationHeightRegAddrs + 3, 1),
+};
+
+static const struct gccmdldstate gcmosrc_rop_ldst[4] = {
+	GCLDSTATE(gcregBlock4RopRegAddrs + 0, 1),
+	GCLDSTATE(gcregBlock4RopRegAddrs + 1, 1),
+	GCLDSTATE(gcregBlock4RopRegAddrs + 2, 1),
+	GCLDSTATE(gcregBlock4RopRegAddrs + 3, 1),
+};
+
+static const struct gccmdldstate gcmosrc_mult_ldst[4] = {
+	GCLDSTATE(gcregBlock4ColorMultiplyModesRegAddrs + 0, 1),
+	GCLDSTATE(gcregBlock4ColorMultiplyModesRegAddrs + 1, 1),
+	GCLDSTATE(gcregBlock4ColorMultiplyModesRegAddrs + 2, 1),
+	GCLDSTATE(gcregBlock4ColorMultiplyModesRegAddrs + 3, 1),
+};
+
+static const struct gccmdldstate gcmosrc_alphacontrol_ldst[4] = {
+	GCLDSTATE(gcregBlock4AlphaControlRegAddrs + 0, 1),
+	GCLDSTATE(gcregBlock4AlphaControlRegAddrs + 1, 1),
+	GCLDSTATE(gcregBlock4AlphaControlRegAddrs + 2, 1),
+	GCLDSTATE(gcregBlock4AlphaControlRegAddrs + 3, 1),
+};
+
+static const struct gccmdldstate gcmosrc_alphamodes_ldst[4] = {
+	GCLDSTATE(gcregBlock4AlphaModesRegAddrs + 0, 1),
+	GCLDSTATE(gcregBlock4AlphaModesRegAddrs + 1, 1),
+	GCLDSTATE(gcregBlock4AlphaModesRegAddrs + 2, 1),
+	GCLDSTATE(gcregBlock4AlphaModesRegAddrs + 3, 1),
+};
+
+static const struct gccmdldstate gcmosrc_srcglobal_ldst[4] = {
+	GCLDSTATE(gcregBlock4GlobalSrcColorRegAddrs + 0, 1),
+	GCLDSTATE(gcregBlock4GlobalSrcColorRegAddrs + 1, 1),
+	GCLDSTATE(gcregBlock4GlobalSrcColorRegAddrs + 2, 1),
+	GCLDSTATE(gcregBlock4GlobalSrcColorRegAddrs + 3, 1),
+};
+
+static const struct gccmdldstate gcmosrc_dstglobal_ldst[4] = {
+	GCLDSTATE(gcregBlock4GlobalDestColorRegAddrs + 0, 1),
+	GCLDSTATE(gcregBlock4GlobalDestColorRegAddrs + 1, 1),
+	GCLDSTATE(gcregBlock4GlobalDestColorRegAddrs + 2, 1),
+	GCLDSTATE(gcregBlock4GlobalDestColorRegAddrs + 3, 1),
+};
+
+struct gcmosrc {
+	/* gcregBlock4SrcAddressRegAddrs */
+	struct gccmdldstate address_ldst;
+
+		/* gcregBlock4SrcAddressRegAddrs */
+		unsigned int address;
+
+	/* gcregBlock4SrcStrideRegAddrs */
+	struct gccmdldstate stride_ldst;
+
+		/* gcregBlock4SrcStrideRegAddrs */
+		unsigned int stride;
+
+	/* gcregBlock4SrcRotationConfigRegAddrs */
+	struct gccmdldstate rotation_ldst;
+
+		/* gcregBlock4SrcRotationConfigRegAddrs */
+		union {
+			struct gcregsrcrotationconfig reg;
+			unsigned int raw;
+		} rotation;
+
+	/* gcregBlock4SrcConfigRegAddrs */
+	struct gccmdldstate config_ldst;
+
+		/* gcregBlock4SrcConfigRegAddrs */
+		union {
+			struct gcregsrcconfig reg;
+			unsigned int raw;
+		} config;
+
+	/* gcregBlock4SrcOriginRegAddrs */
+	struct gccmdldstate origin_ldst;
+
+		/* gcregBlock4SrcOriginRegAddrs */
+		union {
+			struct gcregsrcorigin reg;
+			unsigned int raw;
+		} origin;
+
+	/* gcregBlock4SrcSizeRegAddrs */
+	struct gccmdldstate size_ldst;
+
+		/* gcregBlock4SrcSizeRegAddrs */
+		union {
+			struct gcregsrcsize reg;
+			unsigned int raw;
+		} size;
+
+	/* gcregBlock4SrcRotationHeightRegAddrs */
+	struct gccmdldstate rotationheight_ldst;
+
+		/* gcregBlock4SrcRotationHeightRegAddrs */
+		union {
+			struct gcregsrcrotationheight reg;
+			unsigned int raw;
+		} rotationheight;
+
+	/* gcregBlock4RopRegAddrs */
+	struct gccmdldstate rop_ldst;
+
+		/* gcregBlock4RopRegAddrs */
+		union {
+			struct gcregrop reg;
+			unsigned int raw;
+		} rop;
+
+	/* gcregBlock4ColorMultiplyModesRegAddrs */
+	struct gccmdldstate mult_ldst;
+
+		/* gcregBlock4ColorMultiplyModesRegAddrs */
+		union {
+			struct gcregcolormultiplymodes reg;
+			unsigned int raw;
+		} mult;
+
+	/* gcregBlock4AlphaControlRegAddrs */
+	struct gccmdldstate alphacontrol_ldst;
+
+		/* gcregBlock4AlphaControlRegAddrs */
+		union {
+			struct gcregalphacontrol reg;
+			unsigned int raw;
+		} alphacontrol;
+
+	/* gcregBlock4AlphaModesRegAddrs */
+	struct gccmdldstate alphamodes_ldst;
+
+		/* gcregBlock4AlphaModesRegAddrs */
+		union {
+			struct gcregalphamodes reg;
+			unsigned int raw;
+		} alphamodes;
+
+	/* gcregBlock4GlobalSrcColorRegAddrs */
+	struct gccmdldstate srcglobal_ldst;
+
+		/* gcregBlock4GlobalSrcColorRegAddrs */
+		union {
+			struct gcregglobalsrccolor reg;
+			unsigned int raw;
+		} srcglobal;
+
+	/* gcregBlock4GlobalDestColorRegAddrs */
+	struct gccmdldstate dstglobal_ldst;
+
+		/* gcregBlock4GlobalDestColorRegAddrs */
+		union {
+			struct gcregglobaldstcolor reg;
+			unsigned int raw;
+		} dstglobal;
+};
+
+/*******************************************************************************
+** Modular operations: multisrc
+*/
+
+static const struct gccmdldstate gcmomultisrc_control_ldst =
+	GCLDSTATE(gcregDEMultiSourceRegAddrs, 1);
+
+struct gcmomultisrc {
+	/* gcregDEMultiSourceRegAddrs */
+	struct gccmdldstate control_ldst;
+
+		/* gcregDEMultiSourceRegAddrs */
+		union {
+			struct gcregmultisource reg;
+			unsigned int raw;
+		} control;
+};
+
+/*******************************************************************************
+** Modular operations: startde
+*/
+
+struct gcmostart {
+	/* Start DE command. */
+	struct gccmdstartde startde;
+	struct gccmdstartderect rect;
+
+	/* PE cache flush. */
+	struct gcmoflush flush;
+};
+
+/*******************************************************************************
+** Modular operations: fillsrc
+*/
+
+static const struct gccmdldstate gcmofillsrc_rotation_ldst =
+	GCLDSTATE(gcregSrcRotationConfigRegAddrs, 2);
+
+static const struct gccmdldstate gcmofillsrc_rotationheight_ldst =
+	GCLDSTATE(gcregSrcRotationHeightRegAddrs, 1);
+
+static const struct gccmdldstate gcmofillsrc_rop_ldst =
+	GCLDSTATE(gcregRopRegAddrs, 1);
+
+struct gcmofillsrc {
+	/* gcregSrcRotationConfigRegAddrs */
+	struct gccmdldstate rotation_ldst;
+
+		/* gcregSrcRotationConfigRegAddrs */
+		union {
+			struct gcregsrcrotationconfig reg;
+			unsigned int raw;
+		} rotation;
+
+		/* gcregSrcConfigRegAddrs */
+		union {
+			struct gcregsrcconfig reg;
+			unsigned int raw;
+		} config;
+
+		/* Alignment filler. */
+		unsigned int _filler;
+
+	/* gcregSrcRotationHeightRegAddrs */
+	struct gccmdldstate rotationheight_ldst;
+
+		/* gcregSrcRotationHeightRegAddrs */
+		union {
+			struct gcregsrcrotationheight reg;
+			unsigned int raw;
+		} rotationheight;
+
+	/* gcregRopRegAddrs */
+	struct gccmdldstate rop_ldst;
+
+		/* gcregRopRegAddrs */
+		union {
+			struct gcregrop reg;
+			unsigned int raw;
+		} rop;
+};
+
+/*******************************************************************************
+** Modular operations: fill
+*/
+
+static const struct gccmdldstate gcmofill_clearcolor_ldst =
+	GCLDSTATE(gcregClearPixelValue32RegAddrs, 1);
+
+struct gcmofill {
+	struct gcmodst dst;
+	struct gcmofillsrc src;
+
+	/* gcregClearPixelValue32RegAddrs */
+	struct gccmdldstate clearcolor_ldst;
+
+		/* gcregClearPixelValue32RegAddrs */
+		union {
+			struct gcregclearcolor reg;
+			unsigned int raw;
+		} clearcolor;
+
+	struct gcmostart start;
+};
+
+#endif
diff --git a/gcbv/gcx.h b/gcbv/gcx.h
new file mode 100644
index 0000000..17bcf91
--- /dev/null
+++ b/gcbv/gcx.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2011, Texas Instruments, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Texas Instruments, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL TEXAS INSTRUMENTS, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef GCX_H
+#define GCX_H
+
+#include "gcerror.h"
+#include "gcreg.h"
+
+/* Debug print prefixes. */
+#define GC_INFO_MSG	stdout, DEV_NAME ": %s(%d)"
+#define GC_ERR_MSG	stderr, DEV_NAME ": %s(%d)"
+
+#endif