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| author | Paul Mackerras <paulus@samba.org> | 2007-10-03 14:41:15 +1000 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2007-10-09 21:00:48 +1000 |
| commit | 84fdde5af1eca5ff170d1dff7e2681b0a50a9ecb (patch) | |
| tree | 950f8b4208a76503f3149fc711baedd7b167d068 | |
| parent | cd6eed3718b1b32c60a6ee5658ae6341de3177d9 (diff) | |
| download | kernel_goldelico_gta04-84fdde5af1eca5ff170d1dff7e2681b0a50a9ecb.zip kernel_goldelico_gta04-84fdde5af1eca5ff170d1dff7e2681b0a50a9ecb.tar.gz kernel_goldelico_gta04-84fdde5af1eca5ff170d1dff7e2681b0a50a9ecb.tar.bz2 | |
[POWERPC] Use cache-inhibited large page bit from firmware
Discussions with firmware architects have confirmed that the bit in
the ibm,pa-features property that indicates support for
cache-inhibited large (>= 64kB) page mappings does in fact mean that
the hypervisor allows 64kB mappings to I/O devices.
Thus we can now enable the code that tests that bit and sets our
CPU_FTR_CI_LARGE_PAGE feature bit.
Signed-off-by: Paul Mackerras <paulus@samba.org>
| -rw-r--r-- | arch/powerpc/kernel/prom.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index 172dcc3..9f329a8 100644 --- a/arch/powerpc/kernel/prom.c +++ b/arch/powerpc/kernel/prom.c @@ -531,10 +531,7 @@ static struct ibm_pa_feature { {CPU_FTR_CTRL, 0, 0, 3, 0}, {CPU_FTR_NOEXECUTE, 0, 0, 6, 0}, {CPU_FTR_NODSISRALIGN, 0, 1, 1, 1}, -#if 0 - /* put this back once we know how to test if firmware does 64k IO */ {CPU_FTR_CI_LARGE_PAGE, 0, 1, 2, 0}, -#endif {CPU_FTR_REAL_LE, PPC_FEATURE_TRUE_LE, 5, 0, 0}, }; |