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| author | Mike Turquette <mturquette@ti.com> | 2011-10-07 00:52:59 -0600 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2011-10-07 00:52:59 -0600 |
| commit | addf888c6945c6e3cff135e7e3bb72cc708d1ca4 (patch) | |
| tree | 873acad636451e62614c7df2fe5a0d44088f0d51 | |
| parent | a1900f2efe2d75e0fe5b871421a2f2de2fa68b4e (diff) | |
| download | kernel_goldelico_gta04-addf888c6945c6e3cff135e7e3bb72cc708d1ca4.zip kernel_goldelico_gta04-addf888c6945c6e3cff135e7e3bb72cc708d1ca4.tar.gz kernel_goldelico_gta04-addf888c6945c6e3cff135e7e3bb72cc708d1ca4.tar.bz2 | |
ARM: OMAP3+: dpll: use DPLL's round_rate when setting rate
omap3_noncore_dpll_set_rate uses omap2_dpll_round_rate explicitly. Instead
use the struct clk pointer's round_rate function to allow for DPLL's with
special needs.
An example of a clock that requires this is DPLL_ABE on OMAP4 which
can have a 4x multiplier on top of the usual MN dividers depending on
register settings. This requires a special round_rate function that
might yield a rate different from the initial target.
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: split rate assignment portion into a separate patch]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
| -rw-r--r-- | arch/arm/mach-omap2/dpll3xxx.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index f77022b..6b0fa37 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -455,7 +455,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) new_parent = dd->clk_bypass; } else { if (dd->last_rounded_rate != rate) - omap2_dpll_round_rate(clk, rate); + clk->round_rate(clk, rate); if (dd->last_rounded_rate == 0) return -EINVAL; |