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| author | Martin Fuzzey <mfuzzey@gmail.com> | 2009-06-01 09:19:37 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-06-02 22:36:15 +0100 |
| commit | eb5f4ca9536ba297c98721ecbbdf41ec5b987bd5 (patch) | |
| tree | fb1b7dcf66f2f4d00b99776968dca1293f74b8c8 | |
| parent | d9244b5d2fbfe9fa540024b410047af13ceec90f (diff) | |
| download | kernel_goldelico_gta04-eb5f4ca9536ba297c98721ecbbdf41ec5b987bd5.zip kernel_goldelico_gta04-eb5f4ca9536ba297c98721ecbbdf41ec5b987bd5.tar.gz kernel_goldelico_gta04-eb5f4ca9536ba297c98721ecbbdf41ec5b987bd5.tar.bz2 | |
[ARM] 5534/1: kmalloc must return a cache line aligned buffer
Define ARCH_KMALLOC_MINALIGN in asm/cache.h
At the request of Russell also move ARCH_SLAB_MINALIGN to this file.
Signed-off-by: Martin Fuzzey <mfuzzey@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| -rw-r--r-- | arch/arm/include/asm/cache.h | 16 | ||||
| -rw-r--r-- | arch/arm/include/asm/page.h | 7 |
2 files changed, 16 insertions, 7 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index cb7a9e9..feaa75f 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -7,4 +7,20 @@ #define L1_CACHE_SHIFT 5 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +/* + * Memory returned by kmalloc() may be used for DMA, so we must make + * sure that all such allocations are cache aligned. Otherwise, + * unrelated code may cause parts of the buffer to be read into the + * cache before the transfer is done, causing old data to be seen by + * the CPU. + */ +#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES + +/* + * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. + */ +#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) +#define ARCH_SLAB_MINALIGN 8 +#endif + #endif diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h index e6eb8a6..7b52277 100644 --- a/arch/arm/include/asm/page.h +++ b/arch/arm/include/asm/page.h @@ -202,13 +202,6 @@ typedef struct page *pgtable_t; (((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \ VM_READ | VM_WRITE | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) -/* - * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. - */ -#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) -#define ARCH_SLAB_MINALIGN 8 -#endif - #include <asm-generic/page.h> #endif |