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author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-06-04 13:49:01 +0300 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-06-06 13:45:08 +0200 |
commit | f440eb1354bc92855bbbff08d3ac4a93029c3097 (patch) | |
tree | 421f8e3e6eeacb591d8a3dcefbd3354cf5609f2a | |
parent | 5c38d48cd8dfb3332c072a257bc2a6dab1e5dc3b (diff) | |
download | kernel_goldelico_gta04-f440eb1354bc92855bbbff08d3ac4a93029c3097.zip kernel_goldelico_gta04-f440eb1354bc92855bbbff08d3ac4a93029c3097.tar.gz kernel_goldelico_gta04-f440eb1354bc92855bbbff08d3ac4a93029c3097.tar.bz2 |
drm/i915: Enable the overlay right after primary and cursor planes
Again follow the same sequence for all generations, because doing
otherwise just doesn't make sense.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 532a4fa..bf8fe81 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3622,11 +3622,11 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) intel_enable_plane(dev_priv, plane, pipe); intel_crtc_update_cursor(crtc, true); - intel_update_fbc(dev); - /* Give the overlay scaler a chance to enable if it's on this pipe */ intel_crtc_dpms_overlay(intel_crtc, true); + intel_update_fbc(dev); + mutex_unlock(&dev_priv->dpio_lock); } @@ -3664,11 +3664,11 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) if (IS_G4X(dev)) g4x_fixup_plane(dev_priv, pipe); - intel_update_fbc(dev); - /* Give the overlay scaler a chance to enable if it's on this pipe */ intel_crtc_dpms_overlay(intel_crtc, true); + intel_update_fbc(dev); + for_each_encoder_on_crtc(dev, crtc, encoder) encoder->enable(encoder); } |