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| author | Steven J. Hill <sjhill@mips.com> | 2012-08-28 23:20:08 -0500 |
|---|---|---|
| committer | Steven J. Hill <sjhill@mips.com> | 2012-09-13 15:43:52 -0500 |
| commit | 625c0a21700bdb90844d926a1508a17a77e369c9 (patch) | |
| tree | cda27e3f4b541e91d92788fa18985bfa20a6b119 /CREDITS | |
| parent | 3234f4466934f08136736790e3de3c6debc71271 (diff) | |
| download | kernel_goldelico_gta04-625c0a21700bdb90844d926a1508a17a77e369c9.zip kernel_goldelico_gta04-625c0a21700bdb90844d926a1508a17a77e369c9.tar.gz kernel_goldelico_gta04-625c0a21700bdb90844d926a1508a17a77e369c9.tar.bz2 | |
MIPS: Avoid pipeline stalls on some MIPS32R2 cores.
The architecture specification says that an EHB instruction is
needed to avoid a hazard when writing TLB entries. However, some
cores do not have this hazard, and thus the EHB instruction causes
a costly pipeline stall. Detect these cores and do not use the EHB
instruction.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
Diffstat (limited to 'CREDITS')
0 files changed, 0 insertions, 0 deletions