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| author | Manuel Lauss <manuel.lauss@googlemail.com> | 2012-01-21 18:13:15 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2012-07-23 13:53:38 +0100 |
| commit | 6c2be5cf1d4e70e98d995f9c403b5fbe7b5f2a80 (patch) | |
| tree | bc9779db5aa6443289fe8dcedf28ea1308949504 /Documentation/scheduler | |
| parent | 278bf05cf68a6e5e965c85217ddc1318d18fcbf7 (diff) | |
| download | kernel_goldelico_gta04-6c2be5cf1d4e70e98d995f9c403b5fbe7b5f2a80.zip kernel_goldelico_gta04-6c2be5cf1d4e70e98d995f9c403b5fbe7b5f2a80.tar.gz kernel_goldelico_gta04-6c2be5cf1d4e70e98d995f9c403b5fbe7b5f2a80.tar.bz2 | |
MIPS: Alchemy: handle db1200 cpld ints as they come in
Remove the loop in the cascade handler and instead unconditionally
handle just the first set interrupt coming from the CPLD.
This gets rid of a lot of spurious interrupts being triggered for
the SMSC91111 ethernet chip especially under high(er) IDE load:
"eth0: spurious interrupt (mask = 0xb3)"
Verified on DB1200 and DB1300.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3288/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'Documentation/scheduler')
0 files changed, 0 insertions, 0 deletions