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| author | David Howells <dhowells@redhat.com> | 2006-04-10 22:54:24 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-04-11 06:18:44 -0700 |
| commit | c14038c39ddd9c14225907a05a6ac4d91d645ef1 (patch) | |
| tree | a9f57acaaf9764b35ab9e50f370b8e6859f9501e /Documentation | |
| parent | dbc8700e27a94621de9d22c506c67913e0121501 (diff) | |
| download | kernel_goldelico_gta04-c14038c39ddd9c14225907a05a6ac4d91d645ef1.zip kernel_goldelico_gta04-c14038c39ddd9c14225907a05a6ac4d91d645ef1.tar.gz kernel_goldelico_gta04-c14038c39ddd9c14225907a05a6ac4d91d645ef1.tar.bz2 | |
[PATCH] Improve data-dependency memory barrier example in documentation
In the memory barrier document, improve the example of the data dependency
barrier situation by:
(1) showing the initial values of the variables involved; and
(2) repeating the instruction sequence description, this time with the data
dependency barrier actually shown to make it clear what the revised
sequence actually is.
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/memory-barriers.txt | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index 528d52f..92f0056 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -610,6 +610,7 @@ loads. Consider the following sequence of events: CPU 1 CPU 2 ======================= ======================= + { B = 7; X = 9; Y = 8; C = &Y } STORE A = 1 STORE B = 2 <write barrier> @@ -651,7 +652,20 @@ In the above example, CPU 2 perceives that B is 7, despite the load of *C (which would be B) coming after the the LOAD of C. If, however, a data dependency barrier were to be placed between the load of C -and the load of *C (ie: B) on CPU 2, then the following will occur: +and the load of *C (ie: B) on CPU 2: + + CPU 1 CPU 2 + ======================= ======================= + { B = 7; X = 9; Y = 8; C = &Y } + STORE A = 1 + STORE B = 2 + <write barrier> + STORE C = &B LOAD X + STORE D = 4 LOAD C (gets &B) + <data dependency barrier> + LOAD *C (reads B) + +then the following will occur: +-------+ : : : : | | +------+ +-------+ |