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authorArnd Bergmann <arnd@arndb.de>2013-02-19 17:22:34 +0100
committerArnd Bergmann <arnd@arndb.de>2013-02-19 17:22:34 +0100
commit4a9226a3d192c38493106dcaf5f47f291ede9ed5 (patch)
treef5791e3147b713e02b69c528644a8a2d41b3ea7f /arch/arm/mach-imx/clk-imx6q.c
parent7839c281edd9f4744be58ff0b29aabc64aabde31 (diff)
parente5f9dec8ff5ff3f6254412abed1f68d758f6616b (diff)
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Merge branch 'imx/cpuidle' into late/dt
This resolves one non-obvious merge conflict between the imx cpuidle patches and the imx DT changes for 3.9. Conflicts: arch/arm/mach-imx/mach-imx6q.c Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-imx/clk-imx6q.c')
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 905bec2..7b025ee 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -54,9 +54,18 @@
#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
+#define CGPR 0x64
+#define BM_CGPR_CHICKEN_BIT (0x1 << 17)
+
static void __iomem *ccm_base;
-void __init imx6q_clock_map_io(void) { }
+void imx6q_set_chicken_bit(void)
+{
+ u32 val = readl_relaxed(ccm_base + CGPR);
+
+ val |= BM_CGPR_CHICKEN_BIT;
+ writel_relaxed(val, ccm_base + CGPR);
+}
int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
{
@@ -68,6 +77,7 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
break;
case WAIT_UNCLOCKED:
val |= 0x1 << BP_CLPCR_LPM;
+ val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
break;
case STOP_POWER_ON:
val |= 0x2 << BP_CLPCR_LPM;