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author | Shawn Guo <shawn.guo@linaro.org> | 2013-05-03 10:55:46 +0800 |
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committer | Shawn Guo <shawn.guo@linaro.org> | 2013-05-12 21:39:51 +0800 |
commit | de78a23d73ba7f1d08f3e1aeaa0a03cb912c62a0 (patch) | |
tree | 545b9e4391d149ba3261bd57b0223000351368af /arch/arm/mach-imx | |
parent | 087bb28329f3ccda4e50cb4cf297542d7e773e20 (diff) | |
download | kernel_goldelico_gta04-de78a23d73ba7f1d08f3e1aeaa0a03cb912c62a0.zip kernel_goldelico_gta04-de78a23d73ba7f1d08f3e1aeaa0a03cb912c62a0.tar.gz kernel_goldelico_gta04-de78a23d73ba7f1d08f3e1aeaa0a03cb912c62a0.tar.bz2 |
ARM: imx: fix typo in gpu3d_shader_sels
There is no clock pll2_pfd9_720m. Instead it should be pll3_pfd0_720m.
Fix the typo in gpu3d_shader_sels.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Diffstat (limited to 'arch/arm/mach-imx')
-rw-r--r-- | arch/arm/mach-imx/clk-imx6q.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index f2e1c62..dda9a2b 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -186,7 +186,7 @@ static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd static const char *gpu_axi_sels[] = { "axi", "ahb", }; static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; -static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", }; +static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", }; static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; static const char *ldb_di_sels[] = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; |