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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-11-26 12:56:21 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-12-14 14:53:22 +0000 |
| commit | 2c9b9c8490b60428fa2d1c64042f7c7caed93940 (patch) | |
| tree | c8af289af8c801193eea924db0cd81f09068ddb9 /arch/arm/mm/cache-v4wt.S | |
| parent | ccaf5f05b218e5eb41e2f5cdfd26b18dce4a0218 (diff) | |
| download | kernel_goldelico_gta04-2c9b9c8490b60428fa2d1c64042f7c7caed93940.zip kernel_goldelico_gta04-2c9b9c8490b60428fa2d1c64042f7c7caed93940.tar.gz kernel_goldelico_gta04-2c9b9c8490b60428fa2d1c64042f7c7caed93940.tar.bz2 | |
ARM: add size argument to __cpuc_flush_dcache_page
... and rename the function since it no longer operates on just
pages.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/cache-v4wt.S')
| -rw-r--r-- | arch/arm/mm/cache-v4wt.S | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S index c54fa2c..b3b7410 100644 --- a/arch/arm/mm/cache-v4wt.S +++ b/arch/arm/mm/cache-v4wt.S @@ -117,17 +117,18 @@ ENTRY(v4wt_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_page(void *page) + * flush_kern_dcache_area(void *addr, size_t size) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - page aligned address + * - addr - kernel address + * - size - region size */ -ENTRY(v4wt_flush_kern_dcache_page) +ENTRY(v4wt_flush_kern_dcache_area) mov r2, #0 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache - add r1, r0, #PAGE_SZ + add r1, r0, r1 /* fallthrough */ /* @@ -180,7 +181,7 @@ ENTRY(v4wt_cache_fns) .long v4wt_flush_user_cache_range .long v4wt_coherent_kern_range .long v4wt_coherent_user_range - .long v4wt_flush_kern_dcache_page + .long v4wt_flush_kern_dcache_area .long v4wt_dma_inv_range .long v4wt_dma_clean_range .long v4wt_dma_flush_range |