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| author | Will Deacon <will.deacon@arm.com> | 2013-01-22 19:11:38 +0000 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2013-03-26 09:55:34 +0000 |
| commit | 794fe85da484353dedcb5dc6da14d923d0645fc3 (patch) | |
| tree | 1ff3789f25c67e71815afb731e1c5501e622a78c /arch/arm/mm | |
| parent | 3ef52f2a00efc5f83ae6d40e55cae96ce275893f (diff) | |
| download | kernel_goldelico_gta04-794fe85da484353dedcb5dc6da14d923d0645fc3.zip kernel_goldelico_gta04-794fe85da484353dedcb5dc6da14d923d0645fc3.tar.gz kernel_goldelico_gta04-794fe85da484353dedcb5dc6da14d923d0645fc3.tar.bz2 | |
ARM: mm: remove broken condition check for v4 flushing
There's no point having a conditional cache flush if we don't know the
state of the condition beforehand.
This patch makes the cacheflush in v4_flush_user_cache_range
unconditional.
signed-off-by: will deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/cache-v4.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S index 43e5d77..a7ba68f 100644 --- a/arch/arm/mm/cache-v4.S +++ b/arch/arm/mm/cache-v4.S @@ -58,7 +58,7 @@ ENTRY(v4_flush_kern_cache_all) ENTRY(v4_flush_user_cache_range) #ifdef CONFIG_CPU_CP15 mov ip, #0 - mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache + mcr p15, 0, ip, c7, c7, 0 @ flush ID cache mov pc, lr #else /* FALLTHROUGH */ |