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| author | Eric W. Biederman <ebiederm@xmission.com> | 2009-11-17 01:01:34 -0800 |
|---|---|---|
| committer | Eric W. Biederman <ebiederm@xmission.com> | 2009-11-17 01:01:34 -0800 |
| commit | bb9074ff58fe745e4f244f76209241909c82ec9c (patch) | |
| tree | cf6be00ab88b1e315f6b74a896a370440f677599 /arch/arm/plat-omap/dma.c | |
| parent | 4739a9748e1bd7459f22f7e94e7d85710ca83954 (diff) | |
| parent | 156171c71a0dc4bce12b4408bb1591f8fe32dc1a (diff) | |
| download | kernel_goldelico_gta04-bb9074ff58fe745e4f244f76209241909c82ec9c.zip kernel_goldelico_gta04-bb9074ff58fe745e4f244f76209241909c82ec9c.tar.gz kernel_goldelico_gta04-bb9074ff58fe745e4f244f76209241909c82ec9c.tar.bz2 | |
Merge commit 'v2.6.32-rc7'
Resolve the conflict between v2.6.32-rc7 where dn_def_dev_handler
gets a small bug fix and the sysctl tree where I am removing all
sysctl strategy routines.
Diffstat (limited to 'arch/arm/plat-omap/dma.c')
| -rw-r--r-- | arch/arm/plat-omap/dma.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index b53125f..68eaae3 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -691,13 +691,16 @@ static inline void disable_lnk(int lch) static inline void omap2_enable_irq_lch(int lch) { u32 val; + unsigned long flags; if (!cpu_class_is_omap2()) return; + spin_lock_irqsave(&dma_chan_lock, flags); val = dma_read(IRQENABLE_L0); val |= 1 << lch; dma_write(val, IRQENABLE_L0); + spin_unlock_irqrestore(&dma_chan_lock, flags); } int omap_request_dma(int dev_id, const char *dev_name, @@ -799,10 +802,13 @@ void omap_free_dma(int lch) if (cpu_class_is_omap2()) { u32 val; + + spin_lock_irqsave(&dma_chan_lock, flags); /* Disable interrupts */ val = dma_read(IRQENABLE_L0); val &= ~(1 << lch); dma_write(val, IRQENABLE_L0); + spin_unlock_irqrestore(&dma_chan_lock, flags); /* Clear the CSR register and IRQ status register */ dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch)); @@ -1108,6 +1114,14 @@ int omap_dma_running(void) { int lch; + /* + * On OMAP1510, internal LCD controller will start the transfer + * when it gets enabled, so assume DMA running if LCD enabled. + */ + if (cpu_is_omap1510()) + if (omap_readw(0xfffec000 + 0x00) & (1 << 0)) + return 1; + /* Check if LCD DMA is running */ if (cpu_is_omap16xx()) if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN) |