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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-08-09 21:01:11 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-08-09 21:01:11 -0700 |
| commit | 0fc2f137226eff4c9dd90864dda5c237474c3ec5 (patch) | |
| tree | 50ec67f1f9d144a3ceb5ccff45a37bc5005f6c3d /arch/blackfin/Kconfig | |
| parent | dcded10f6dce10411b16134ce9cc87bfdf75c13f (diff) | |
| parent | aab2393e2ec52c74b419af7c26a12e21584e483b (diff) | |
| download | kernel_goldelico_gta04-0fc2f137226eff4c9dd90864dda5c237474c3ec5.zip kernel_goldelico_gta04-0fc2f137226eff4c9dd90864dda5c237474c3ec5.tar.gz kernel_goldelico_gta04-0fc2f137226eff4c9dd90864dda5c237474c3ec5.tar.bz2 | |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (32 commits)
Blackfin: gpio: add a debounce stub
Blackfin: update defconfigs
Blackfin: remove CONFIG_MEM_GENERIC_BOARD
Blackfin: dpmc: punt unnecessary RTC_ISTAT clearing
Blackfin: unify rotary encoder bitmasks
Blackfin: unify SDH/RSI bitmasks
Blackfin: BF54x: tweak DMAC MMR naming to match other ports
Blackfin: TWI: clean up the MMR names
Blackfin: add EVT_OVERRIDE/IPRIO core MMR helpers
Blackfin: add support for dynamic ftrace
Blackfin: add support for LZO compressed kernels
Blackfin: portmux: fix peripheral map overflow when requesting pins
Blackfin: document SPI CS limitations with CPHA=0
Blackfin: remove useless and outdated documentation
Blackfin: BF51x/BF52x: support GPIO Hysteresis/Schmitt Trigger options
Blackfin: gpio/portmux: clean up whitespace corruption
Blackfin: make sure mmiowb inserts a write barrier with SSYNC
Blackfin: fix DMA/cache bug when resuming from suspend to RAM
Blackfin: BF51x: fix handling of PH8 (the "internal" SPI0SEL4 pin)
Blackfin: add a GPIO_DEFAULT_BOOT_SPI_CS
...
Diffstat (limited to 'arch/blackfin/Kconfig')
| -rw-r--r-- | arch/blackfin/Kconfig | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index c88fd35..5a3152b 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -25,6 +25,8 @@ config BLACKFIN def_bool y select HAVE_ARCH_KGDB select HAVE_ARCH_TRACEHOOK + select HAVE_DYNAMIC_FTRACE + select HAVE_FTRACE_MCOUNT_RECORD select HAVE_FUNCTION_GRAPH_TRACER select HAVE_FUNCTION_TRACER select HAVE_FUNCTION_TRACE_MCOUNT_TEST @@ -32,6 +34,7 @@ config BLACKFIN select HAVE_KERNEL_GZIP if RAMKERNEL select HAVE_KERNEL_BZIP2 if RAMKERNEL select HAVE_KERNEL_LZMA if RAMKERNEL + select HAVE_KERNEL_LZO if RAMKERNEL select HAVE_OPROFILE select ARCH_WANT_OPTIONAL_GPIOLIB @@ -328,11 +331,6 @@ config BF53x depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) default y -config MEM_GENERIC_BOARD - bool - depends on GENERIC_BOARD - default y - config MEM_MT48LC64M4A2FB_7E bool depends on (BFIN533_STAMP) @@ -850,6 +848,18 @@ config CPLB_SWITCH_TAB_L1 If enabled, the CPLB Switch Tables are linked into L1 data memory. (less latency) +config CACHE_FLUSH_L1 + bool "Locate cache flush funcs in L1 Inst Memory" + default y + help + If enabled, the Blackfin cache flushing functions are linked + into L1 instruction memory. + + Note that this might be required to address anomalies, but + these functions are pretty small, so it shouldn't be too bad. + If you are using a processor affected by an anomaly, the build + system will double check for you and prevent it. + config APP_STACK_L1 bool "Support locating application stack in L1 Scratch Memory" default y |